JPH0199152A - Dma control circuit - Google Patents

Dma control circuit

Info

Publication number
JPH0199152A
JPH0199152A JP62257839A JP25783987A JPH0199152A JP H0199152 A JPH0199152 A JP H0199152A JP 62257839 A JP62257839 A JP 62257839A JP 25783987 A JP25783987 A JP 25783987A JP H0199152 A JPH0199152 A JP H0199152A
Authority
JP
Japan
Prior art keywords
writing
main memory
control circuit
overlap
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62257839A
Other languages
Japanese (ja)
Inventor
Masami Tomioka
富岡　政美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62257839A priority Critical patent/JPH0199152A/en
Publication of JPH0199152A publication Critical patent/JPH0199152A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To operate a write inhibition without fail by detecting the overlap of a gate driving signal to gate an access signal and inhibiting a writing to a main storage when the overlap is recognized. CONSTITUTION:Concerning the writing from I/O devices 1 and 2 to a main storage 3, the gate driving signal to gate the access signal is inputted to respectively applicable overlapping detecting circuits 41 and 42, and the overlap is detected by the overlapping detecting circuits 41 and 42. When the overlap of either data on a data signal line or an address on an address signal line is detected, the sending of a writing signal from a main memory writing control circuit 5 for executing a writing control to the main storage 3 is inhibited, and an erroneous writing is prevented. Thus, the erroneous writing to the main memory device due to the trouble of hardware, etc., can be inhibited, and the runaway of a program can be prevented beforehand.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明はＤＭＡ制御回路に関し、特に主記憶装置への誤
書込みの禁止に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a DMA control circuit, and particularly to prohibiting erroneous writing to a main memory.

（従来の技術） 従来、この種の誤書込み禁止回路においては、メモリの
成る特定の大きさのブロックを形成する比較的大きい領
域に関して、書込みを禁止している。(Prior Art) Conventionally, this type of erroneous write prohibition circuit prohibits writing to a relatively large area forming a block of a specific size of a memory.

（発明が解決しようとする問題点） 上述した従来の誤書込み禁止回路では、大きな領域で書
込みの禁止が指示されているため、ハードウェアの障害
などにより書込みエリアの障害や誤動作があったとき罠
は書込みが確実に禁止されないと云う欠点がある。(Problems to be Solved by the Invention) In the conventional accidental write prohibition circuit described above, write prohibition is instructed in a large area, so if there is a failure or malfunction in the write area due to a hardware failure, etc. has the disadvantage that writing is not reliably prohibited.

本発明の目的は、主記憶装置へのアクセス信号をゲート
するゲート駆動信号の重複を検出し、検出信号により上
記重複が認められたならば主記憶装置への書込みを禁止
することによりて上記欠点を除去し、確実に書込み禁止
が動作できるように構成したＤＭＡ制御回路を提供する
ことにある。An object of the present invention is to detect duplication of gate drive signals that gate access signals to the main memory, and if the detection signal detects the duplication, prohibit writing to the main memory, thereby eliminating the above-mentioned drawbacks. It is an object of the present invention to provide a DMA control circuit which is configured so that the write inhibit function can be reliably operated.

（問題点を解決するための手段） 本発明によるＤＭＡ制御回路は複数の重複検出回路と、
主記憶書込み制御回路とを具備して構成したものである
。(Means for Solving the Problems) A DMA control circuit according to the present invention includes a plurality of duplication detection circuits,
This configuration includes a main memory write control circuit.

複数の重複検出回路は、主記憶装置の各記憶エリアへＤ
ＭＡ方式によりデータを書込むとき罠、アクセス信号を
ゲートするゲート駆動信号の重複を検出するためのもの
であり、上記各エリアに対応したものである。The plurality of duplication detection circuits are connected to each storage area of the main storage device.
This is for detecting duplication of gate drive signals for gating traps and access signals when writing data using the MA method, and corresponds to each of the above areas.

主記憶書込み制御回路は、複数の重複検出回路の出力に
従って、ＤＭＡ方式による主記憶装置の指定されたエリ
アへの書込みを禁止するためのものである。The main memory write control circuit is for inhibiting writing to a designated area of the main memory device using the DMA method according to the outputs of the plurality of duplication detection circuits.

（実施例） 次に、本発明について図面を参照して説明する。(Example) Next, the present invention will be explained with reference to the drawings.

第１図は、本発明によるＤＭＡ制御回路の一実施例を示
すブロック図である。FIG. 1 is a block diagram showing one embodiment of a DMA control circuit according to the present invention.

第１図において、１，２はそれぞれＩ１０装置、３は主
記憶装置、４１．４２はそれぞれ重複検出回路、５は主
記憶書込み制御回路である。In FIG. 1, 1 and 2 are I10 devices, 3 is a main memory, 41 and 42 are duplication detection circuits, and 5 is a main memory write control circuit.

Ｉ１０装置１，２からの主記憶装置３への書込みに関し
て、アクセス信号をゲートするゲート駆動信号をそれぞ
れ該当する重複検出回路４１゜４２へ入力し、重複検出
回路４１．４２によりその重複を検出する。Regarding writing to the main memory device 3 from the I10 devices 1 and 2, gate drive signals for gating access signals are respectively input to the corresponding duplication detection circuits 41 and 42, and the duplication is detected by the duplication detection circuits 41 and 42. .

重複検出回路４１．４２によってデータ信号線上のデー
タ、あるいはアドレス信号線上のアドレスの重複が検出
されたならば、主記憶装置３への書込み制御を行うため
の主記憶書込み制御回路５からの書込み信号の送出を禁
止して誤書込みを防止する。If the duplication detection circuits 41 and 42 detect duplication of the data on the data signal line or the address on the address signal line, a write signal is sent from the main memory write control circuit 5 for controlling the write to the main memory device 3. This prevents erroneous writing by prohibiting the sending of the data.

（発明の効果） 以上説明したように本発明は、主記憶装置へのアクセス
信号をゲートするゲート駆動信号の重複を検出し、検出
信号により上記重複が認められたならば主記憶装置への
書込みを禁止することによりて、ハードウェアの障害な
どによる主記憶装置への誤書込みを禁止し、これによる
プログラムの暴走を未然に防ぐことができるという効果
がある。(Effects of the Invention) As explained above, the present invention detects duplication of the gate drive signal that gates the access signal to the main memory, and if the above duplication is recognized by the detection signal, write to the main memory is performed. This has the effect of prohibiting erroneous writing to the main memory due to hardware failures and preventing program runaway due to this.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本発明によるＤＭＢ制御回路の一実施例を示
すブロック図である。 １．２−・・Ｉ１０装置 ３・・・主記憶装置 ４・・・重複検出回路 ５−・・主記憶書込み制御回路 特許出願人　　日本電気株式会社 代理人弁理士　井　ノ　ロ　　　壽 第１図FIG. 1 is a block diagram showing one embodiment of a DMB control circuit according to the present invention. 1.2--I10 device 3--Main memory device 4--Duplicity detection circuit 5--.Main memory write control circuit Patent applicant: NEC Corporation Patent attorney Hisashi Inoro Figure 1

Claims (1)

【特許請求の範囲】[Claims] 主記憶装置の各記憶エリアへＤＭＡ方式によりデータを
書込むときにアクセス信号をゲートするゲート駆動信号
の重複を検出するための前記エリアに対応した複数の重
複検出回路と、前記複数の重複検出回路の出力に従って
前記ＤＭＡ方式による前記主記憶装置の指定されたエリ
アへの書込みを禁止するための主記憶書込み制御回路と
を具備して構成したことを特徴とするＤＭＡ制御回路。a plurality of duplication detection circuits corresponding to the areas for detecting duplication of gate drive signals for gating access signals when writing data to each storage area of the main memory device using the DMA method; and a plurality of duplication detection circuits corresponding to the areas. and a main memory write control circuit for inhibiting writing to a specified area of the main memory device by the DMA method according to the output of the DMA control circuit.
JP62257839A 1987-10-13 1987-10-13 Dma control circuit Pending JPH0199152A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62257839A JPH0199152A (en) 1987-10-13 1987-10-13 Dma control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62257839A JPH0199152A (en) 1987-10-13 1987-10-13 Dma control circuit

Publications (1)

Publication Number Publication Date
JPH0199152A true JPH0199152A (en) 1989-04-18

Family

ID=17311856

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62257839A Pending JPH0199152A (en) 1987-10-13 1987-10-13 Dma control circuit

Country Status (1)

Country Link
JP (1) JPH0199152A (en)

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