JPH0197082A - Device for regenerating teletext signal - Google Patents

Abstract

PURPOSE:To accurately sample character information by generating gate pulse from synchronizing signal and vertical synchronizing signal, fetching clock line signal, multiplying horizontal synchronizing pulse obtained from the synchronizing signal in a PLL circuit, and correcting the signal by means of signal which can be obtained from the clock line signal. CONSTITUTION:Video reproduced signal passed through a pulse gate 13 is two- multiplied in a two-multiplier 16 and supplied to an input terminal on one side of a phase comparator 17. Signal fetched from the output side of a variable delay line 19 is supplied to an input terminal on the other side of the phase comparator 17. The output is inputted to a sample-hold circuit 18, and the outputs of the phase comparator are held and are given to the variable delay line 19 only in case of existing a teletext signal. The phase of the signal is adjusted so that character information can be sampled most sufficiently based on the clock line signal and the signal is supplied to the variable delay line 11 as sampling clock signal f1'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a teletext signal reproducing device for extracting a teletext signal from a video signal containing the teletext signal.

[Conventional technology]

Teletext broadcasting is a horizontal scanning period in which there is no video signal during a part of the vertical retrace period of the video signal, for example, 14 in an odd field.
-16H, 21H, 277 to 279 for even fields
The character broadcasting signal is superimposed on H, 284H, and the character signal in one horizontal scanning period is usually composed of color burst CB and 16-bit data 1, as shown in Figure 9.
It consists of a synchronization section consisting of a clock run-in signal CR expressed as 010101010101010 and a framing code FC, and a data packet section DP consisting of a bfix, a 22-byte data block, and a check code.

FIG. 10 is a block diagram showing the configuration of a reproducing device (decoder) for extracting character signal data among conventional teletext signal reproducing devices.

The frequency of the sampling clock for extracting character signal data is set to, for example, 5.72727 MHz, and this clock frequency is set to two PLL (phase locked loop) circuits 20 based on the color burst CB in the video signal. and 30. That is, the color burst in the input video signal is 3.58
A color burst signal CB is extracted through a MHz bandpass filter 1 and a burst gate 2, and the first PLL circuit 20 outputs a V signal using a 3.58MHz crystal oscillator 21.
A 3.58 MHz signal synchronized with the phase of the color burst signal is created by the XO 22 and the phase detector 23 and sent to the second PLL circuit 30.

The second PLL circuit 30 has a clock frequency of 5.727M.
Hz is 815 times the frequency of the color subcarrier, 3.579 MHz, and 364 times the horizontal scanning frequency f11. , phase detector 3
4 and 115 for dividing the output of the first PLL circuit 20.
The counter 35 generates a sampling clock fx having a frequency of 5.727-MHz.

This sampling clock signal fx is input to a framing code detection circuit 7 including a frame pulse flywheel circuit via a variable delay line 11 controlled by the sub CPU10.

Further, a synchronizing signal is separated from the video signal by a synchronizing signal separation circuit 3, and this synchronizing signal is delayed by a pulse delay circuit 4 and inputted to the above-mentioned burst gate 2, and is manually inputted to a framing code detection circuit 9. Furthermore, only the vertical synchronizing signal is extracted by the vertical synchronizing signal separation circuit 4 and inputted to the framing code detecting circuit 7.

The framing code detection circuit 7 generates a pulse for a period including the line on which the teletext signal is superimposed from the fall of the synchronization signal or the rise of the vertical synchronization signal, and detects the framing code from the horizontal synchronization signal only during the generation period of this pulse. This generates a pulse with a period including Character data is extracted from the video signal by the AGC and data slicing circuit 6, and stored in a shift register in the framing code detection circuit according to the sampling clock, and when the address specified by the output of the shift register 7 matches the framing code. It is designed to output pulses only when the

An error correction circuit 8 is provided to correct errors in extracted character data, and includes a separated synchronization signal, a vertical synchronization signal, the output of the AGC and data slice circuit 6, and the output of the framing code detection circuit 7. In addition to each input, the above-mentioned sampling clock ty is also input, and the sub CPU l0 changes the delay amount of the variable delay line 11 so as to minimize the error amount, thereby realizing the minimum error amount. .

However, it may be difficult for such a decoder to decode teletext signals recorded on a VTR.

Home video tape recorders have made remarkable progress in recent years, and some have achieved a horizontal resolution of 400 lines or more with a luminance signal band of 5 MHz or more. In the case of the hybrid system currently used in Japan, the spectrum of teletext signals is
As shown in the figure, the upper limit of the spectrum is 4.5MHz, and within the transmission band it is possible to sufficiently transmit teletext signals using a video tape recorder, but for the following reasons, it is not always possible to transmit teletext signals. Good teletext data is not extracted.

In other words, in the low-frequency conversion color one-way system, considering the relationship between the color burst and the luminance signal, the color burst is frequency-converted to 3,579 MHz with jitter compensation, but the frequency of the color burst is converted to 3,579 MHz, which has been passed through the luminance signal system. Luminance signals including teletext signals are not compensated for jitter, so
It still has jitter and the time axis fluctuates. Therefore, character information fluctuates following jitter, whereas the sampling clock is generated from color bursts, so the optimum locking phase is completely different for each field.

As mentioned above, the optimal phase of the sampling clock can be determined by adjusting the delay amount of the delay line 13, but this adjustment function requires a quick response that matches the phase within the range of the clock run-in signal of each data packet. If the information not only does not have the characteristics but also has a different phase, it may not be treated as character information.

[Problem that the invention seeks to solve]

In this way, conventional teletext signal reproducing devices are insufficient in removing the effects of jitter included during recording, so -
This method has a problem in that the teletext signal cannot be accurately extracted from the video signal containing jitter obtained after recording.

The present invention has been made to solve these problems, and provides a teletext signal reproducing device that has a simple configuration and generates a well-phased sampling clock to enable accurate extraction of character information. The purpose is to

[Means for solving problems]

According to the present invention, a teletext signal is generated from a video playback signal in which a clock run-in signal is superimposed together with a teletext signal on at least one line of a vertical retrace interval using a sampling clock generated by a sampling clock generator. A teletext signal reproducing device for extracting a teletext signal, comprising a multiplying means for obtaining a multiplied signal from a horizontal synchronizing signal, a clock run-in signal extracting means for extracting a clock run-in signal from a video playback signal, and a multiplied signal obtained by the multiplication means. The present invention is characterized by comprising a phase adjusting means for generating a sampling clock for extracting a teletext signal by correcting the phase so as to have a substantially constant phase with respect to the phase of the clock run-in signal.

[For production]

The clock run-in signal extraction means generates a gate pulse for extracting the clock run-in signal from the synchronization signal and the vertical synchronization signal, thereby extracting the clock run-in signal. On the other hand, the horizontal synchronization pulse obtained by removing the equalization pulse from the synchronization signal is multiplied by a PLL circuit, and this signal is corrected by the signal obtained from the clock run-in signal. Therefore, data extraction is performed accurately.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a teletext signal reproducing apparatus according to the present invention, and the same parts as in FIG. 10 are given the same numbers and detailed explanation thereof will be omitted.

Since the synchronization signal output from the synchronization signal separation circuit 3 includes an equalization pulse, the half H pulse killer circuit 12 removes the equalization pulse and sends only the horizontal synchronization signal fH to the PLL circuit 40 and the clock run-in signal. It is supplied to the gate pulse generation circuit 50. The vertical synchronization signal fv extracted by the vertical synchronization signal separation circuit 5 is also input to the clock run-in signal gate pulse generation circuit 50.
The gate pulse fG is generated at the timing when the clock run-in signal should be extracted from both synchronization signals. To generate this gate pulse, for example, as shown in FIG. 3(b), a pulse that becomes high level is generated at the timing when the clock-hen-in signal is inserted, and further, as shown in FIG.
The period including the line on which the teletext signal is transmitted in the vertical retrace period shown in C), for example from 4H to 21H.
It is only necessary to generate a pulse that reaches a high level from the vertical synchronizing signal, and to perform the logical product of both pulses.

This gate pulse fg is applied to a pulse gate 13 into which the video signal is input as is, and when this gate is opened, a clock run-in signal is taken out. In this case, the gate may open even on lines where teletext signals are not being transmitted during the vertical retrace period, but since a bandpass filter is provided as described later, this is a test signal for the transmission line. Even if something other than a character signal such as a VITS signal is superimposed, the output level will be very low and there will be no problem.

On the other hand, the output of the half H pulse killer 12 is output from the phase comparator 4.
4 is also supplied to one input terminal of the counter 43, and the output of a counter 43 having a frequency division ratio of 1/364, for example, is supplied to the other input terminal. A voltage corresponding to the phase difference between the two input signals is output from the phase comparator 44, and the high frequency component is removed by the low-pass filter 41, and the voltage is inputted to the VCO 42 to control its oscillation frequency, and the oscillation output is sent to the counter. 43 to form a PLL circuit as a whole. The output signal f1 of this VCO 42 is input to the variable delay line (2) 19.

FIG. 2 is a circuit diagram showing a specific example of the variable delay line 19. This circuit includes a plurality of inductances Ll-Ln connected in series, and an anode connected to each connection point.
It consists of a plurality of varicap diodes VDI-VD,n whose cathodes are commonly connected and to which a control signal Cv is supplied.
By changing the capacitance of D, the amount of delay is changed.

The video playback signal passing through the pulse gate 13 is 2.86
2.86MHz by MHz bandpass filter 14
This signal is taken out, and after being doubled by the doubler 16, it is supplied to one side input terminal of the phase comparator 17. A signal taken out from the output side of the variable delay line (2) 19 is supplied to the other input terminal of the phase comparator 17, and the output thereof is input to the sample/hold circuit 18 and detected by the level detector 15. 2, 8
The phase comparator output is held only when the level of the output signal of the 6 MHz bandpass filter 14 is high, that is, when there is a teletext signal, and the variable delay line (2)
given to 19.

According to such a configuration, if the frequency division ratio of the counter 43 is set to 1/364 as described above, the signal f of 5,727 MHz, which is the horizontal periodic frequency multiplied by 364, is
1 will be obtained as the output of the VCO 42. The phase of this signal is adjusted based on the clock run-in signal so that character information can be extracted best, and the signal is output as a sampling clock signal fl' to the variable delay line 11.
It will be supplied to the system and used for extracting character information data. This fl' is a signal whose frequency fluctuation follows the jitter of the input video signal, and whose phase has a constant relationship with respect to the clock run-in signal of the teletext broadcast.

Therefore, in this example, the sampling clock is obtained based on the clock run-in signal from a signal obtained by multiplying the horizontal synchronization signal including jitter, and the phase is corrected in the clock run-in signal section close to the data section. The sampling clock follows jitter, making it possible to extract character information accurately.

In the above embodiment, two variable delay lines are used, but the variable delay line (2) 19
If it is possible to obtain a signal having a phase value sufficiently accurate relative to the clock run-in signal, the phase adjustment by the variable delay line (1) 11 can be omitted.

FIG. 4 is a block diagram showing another embodiment of the present invention,
The difference from the embodiment shown in FIG. 1 is that the output fl of the VCO 42 is input to a phase switching circuit 47.
7 is generated from the clock run-in signal. That is, the signal extracted by the pulse gate 13 is converted into a 2.86 MHz clock run-in signal (FIG. 5(A)) by the 2.86 MHz band-pass filter 14, and this clock run-in signal is converted by the waveform shaper 45. The waveform is shaped to make the edge clear (Fig. 5 (B)), and the rise of this first pulse causes the monostable multi-by-break 46
Pulse CRI that lasts for a predetermined time (Fig. 5 (C)
), which is used as the phase switching signal CRI.

Note that 2 in FIG. 5(B) is required to obtain the pulse CRI.
You may use the rising edge of the waveform after the th waveform.

FIG. 6 is a circuit diagram showing the detailed configuration of the phase switching circuit 47.

According to the figure, the phase switching circuit 47 has two D-type latches 51 and 52 that operate with the output signal CRI of the monostable multi-by-break 46 as a common clock input, and their Q outputs f and g, respectively, at the input terminal A. and a data selector 53 that selects four signals by inputting them from B. This data selector obtains an output signal as described later in response to a combination of input signal states to input terminals A and B.

The D-type latch and data selector are Texas Fist Instrument's TTLIC 74LS.
74 and 74LS153.

The 5,727 MHz signal a, which is the output signal of the VCO 42, is input to the D input terminal of the D type latch 51, and the output signal of V6O13 is input to the D input terminal of the D type latch 52.
A signal is input via a delay line 54 which delays the signal by a period.

The data selector 53 also has the output signal a of the VCO 42.
is applied to the input terminal C1, a signal C obtained by inverting this by the inverter 55 is applied to the input terminal C2, and a signal d obtained by inverting this by the inverter 56 is applied to the input terminal C3 of the output of the delay 54. They are respectively input to input terminals co.

FIG. 7 shows input signals a input to the data selector 53,
FIG. 3 is a waveform diagram showing the phase relationship between b, c, and d. According to this, signal S is delayed by 90'' with respect to signal a, and signal C and signal d are further delayed by 906''.Furthermore, the data selector is connected to input terminals A and B.
It generates outputs as shown in the table for combinations of input signal states.

Table 8 is a timing chart showing the operation of the data selector 53.

As mentioned above, the phase of the input signal a and the phase of the input signal S are 90" out of phase, and at the time the signal CRI rises, the D input of the D latch 51 is H, and the D input of the D latch 52 is L.
Therefore, the signal f is H1, the signal g is L, and according to the table, the output is C1, and the signal a is taken out as the output.

Next, the phase of signal a is shifted with respect to signal CRI, and signal C
When the rising edge signal a of RI is within the range indicated by ■ in FIG. 5, the signal f is L1, the signal g is H, the output is C2 according to Table 1, and the signal C is taken out as the output. Therefore, the phase switching circuit 19 outputs an output whose phase difference from the horizontal synchronizing signal is within 1/4 period.

In the above embodiment, the phase switching circuit selects the one closest to the horizontal synchronization signal from four different phase signals, but the number of different phase signals to be selected can be determined arbitrarily. The more there are, the more effective the phase adjustment will be.

Further, the phase switching circuit obtains the output of gS f for a plurality of edges among the eight edges of the pulse (B), and the output is used to convert signals of a plurality of phases based on glf of combinations that appear many times again. It may be something that can be selected from among them and output.

Furthermore, the device of the present invention may be incorporated in a video playback device, in the form of an adapter, or in a television receiver.

〔Effect of the invention〕

As described above in detail based on the embodiments, according to the teletext signal reproducing apparatus according to the present invention, a signal obtained by multiplying the horizontal synchronization signal obtained from the synchronization signal is reproduced by the signal obtained from the clock run-in signal. Since the phase is corrected near the data portion to obtain the sampling clock for extracting the teletext signal, a sampling clock that follows jitter and has a substantially constant phase with respect to the clock run-in signal can be obtained. Therefore, it becomes possible to extract the teletext signal accurately and reliably even from a video playback signal containing jitter.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a teletext signal reproducing apparatus according to the present invention for extracting a character signal from a VTR reproduced video signal, and FIG. 2 shows the configuration of the variable delay line in FIG. 1. A circuit diagram, FIG. 3 is a waveform diagram illustrating gate pulse generation for extracting a clock run-in signal, FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention, and FIG. 5 is a data extraction clock signal. FIG. 6 is a circuit diagram showing the detailed configuration of the phase switching circuit.
FIG. 7 is a waveform diagram showing each signal input to the data selector, FIG. 8 is a timing chart showing the operation in the data selector, and FIG. 9 is a diagram showing the configuration of a teletext signal.
FIG. 10 is a block diagram showing the configuration of a conventional teletext signal sampling section, and FIG. 11 is a spectrum diagram of the teletext signal. 3... Synchronization signal separation circuit, 4... Vertical synchronization signal separation circuit, 11... Variable delay line (1), 12...
・Half H pulse killer, 13...gate, 14...
・Band pass filter, 17.44...phase comparator,
19...Variable delay line (2), 20°30.
40...PLL circuit, 41...LPF. 42... vCO143... Counter, 50... Clock run-in signal gate pulse generation circuit, 51. 5
2...D latch, 53...Data selector. Applicant's Representative Sato - Male Fig. 6 Fig. 7 Nine-winged Knee - Fig. 8

Claims (1)

[Claims] 1. Teletext broadcasting using the sampling clock generated by the sampling clock generator from a video playback signal in which a clock run-in signal is superimposed together with the teletext signal on at least one line of the vertical blanking period. A teletext signal reproducing device for extracting a signal, comprising: a multiplying means for obtaining a multiplied signal from the horizontal synchronizing signal; a clock run-in signal extracting means for extracting the clock run-in signal in the video playback signal; and a phase adjustment means for generating a sampling clock for extracting the teletext signal by correcting the phase of the multiplied signal so as to have a substantially constant phase with respect to the phase of the extracted clock run-in signal. Teletext signal reproducing device. 2. The teletext signal reproducing apparatus according to claim 1, wherein the multiplication means includes a PLL circuit that controls the frequency in a predetermined relationship with respect to the horizontal synchronization signal obtained from the video signal. 3. The clock run-in signal extraction means includes a selection gate and a gate pulse generation circuit that generates a signal for opening the selection gate from the horizontal synchronization signal and the vertical synchronization signal to the video signal including the clock run-in signal. A teletext signal reproducing device according to claim 1, characterized in that: