JPH0196751A - Input/output controlling device - Google Patents

Abstract

PURPOSE:To carry out the transfer of data with no consciousness of the byte boundaries by changing the width of the data transferred between a bus interface circuit and an internal bus according to the type of the data which is transferred to the bus interface circuit. CONSTITUTION:When data are transferred to a buffer memory 2 from a main memory 21 via a system bus 20 these data are stored in a bus interface circuit 4. The received data are sent to an internal bus switching circuit 6 under the control of a DMA control circuit 5. The circuit 6 writes data to the memory 2 under the control of the circuit 5. The 4-byte width of data transferred via the bus 20 is converted into the 1-byte width with an internal bus 10. Thus it is possible to transfer data with no consciousness of the byte boundaries of the transfer start addresses of both memories 21 and 2.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an input/output control device for an information processing system.
In particular, the present invention relates to an input/output control device having a buffer memory for buffering data.

Conventionally, as shown in Figure 1, in this type of input/output control device, the transfer start byte boundary of the main memory to be transferred is different from the transfer start byte boundary of the data held in the buffer memory. Because of this possibility, after reading the data from the processor buffer memory, aligning the data by shift operations, etc., and generating the data to be written to the main memory, the data is written to the main memory via the bus interface control circuit. Alternatively, the data transfer width between the path interface circuit, the processor, and the buffer memory is set to 1 byte, and the bus interface control circuit aligns the data to be written to the main memory.

Problems to be Solved by the Invention In the former case, the conventional input/output control device performs data transfer using firmware, so it is not possible to increase the data transfer ability; Since the data transfer operation can be realized by DMA, the data transfer capacity can be increased.

Since the operation of reading the channel command word and writing the end status can only be performed in byte units, there is a drawback that the overhead of the firmware before and after the data transfer operation becomes large.

The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a novel input/output control device that makes it possible to eliminate the above-mentioned drawbacks inherent in the conventional technology.

Means for Solving the Problems In order to achieve the above objects, an input/output control device according to the present invention includes a processor for executing microinstructions, a batza memory for storing microinstructions, input/output data, and control tables, and an input/output control device. 1, which is configured with a bus interface circuit that controls the interface with the device and an internal bus switching circuit that changes the internal bus data width. (Depending on the type of data transferred to the interface circuit,
It is characterized by changing the data width transferred between the bus interface circuit and the internal bus.

EXAMPLE Hereinafter, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

Figure 1! , 7, and the reference drawings show an embodiment of the present invention. Among them, FIG. 1 is a block diagram showing an embodiment of the input/output control device according to the present invention, and FIG. 3 is similar to FIG. 1. FIG. 1 is a block diagram showing a specific example of the path interface circuit 6 shown in FIG. 1. FIG.

Referring to FIG. 1, 0gJ, and FIG. 1, when data is transferred between the main memory CO I and the buffer memory CO as shown in FIG.

In the case of a data transfer where the byte boundary of the main memory CO's ISO transfer start address and the byte boundary of the transfer start address of the data held in the X7 memory record match, it is possible to transfer the data in the same arrangement. As shown in the figure, for data transfer r when the byte boundaries of the transfer start addresses are different, it is necessary to rearrange the data arrangement.

The input/output control lA4 according to the present invention allows data transfer without being aware of the byte boundary of the transfer start address.

From Fig. 7, when data is transferred from the main memory CO to the Batza memory CO via the system bus, the data sent from the main memory CO is transferred to the path interface circuit shown in Fig. 3). The received data storage area is stored in /J/. Next icDMA control circuit! Under the control of , the received data is transferred one byte at a time to the internal path switching circuit 6 via the bitcoder 31 reception buffer 13da according to the transfer count number according to the start address of the reception data storage area lJl.

Next, as shown in FIG. 3, the internal path switching circuit 6, under the control of the DMA control circuit 3, transfers the 1 byte data transferred from the data line 3/.

According to the start address 1, transfer to either bit O-7 transmit data switch ios, or bit t-/3 transmit data switch 106° or bit l&-3 transmit data switch 10, or bit coter 3/transmit data switch 10t. .

It is written to Batza memory under the control of processor l. Once the number of counts has been written, it becomes the primary.

Under the control of the processor l, data is sent from the Bazza memoryco via the input/output interface circuit 3.

Output to input/output device t.

From Figure 1, conversely, when transferring data from the buffer memory co to the main memory l, under the control of the processor l, the data of 9 l bytes transferred from the buffer memory co is transferred according to the byte boundary of the starting address as shown in figure 1. bits 17-7, or bits t-/j of the internal bus io,
or bit/4-23. or transferred to either Bitcoder 37. The 91 bytes of data transferred is DMA.
Under the control of the control circuit 3, the internal path switching circuit 6
The received data is transferred to bit 2'l-J/ of the bus interface circuit section through 24-3/reception data switching 10da.

Next, from FIG. 3, l transferred to bit 2II-3/
The byte data passes through the transmission data selector 133 of the path interface circuit section, and, under the control of the DMA control circuit S, is set to bit O-7° or bit f- of the transmission data storage area lcoJ according to the byte boundary of the start address. /
j, or beep)/A-u, or beep) 24! -J/. When the data is stored in the area of the pit coder 31, it is written to the main memory l via the system bus as 12 pieces of transmission data.

As described above, by transferring data as 3-byte wide data on the system bus and converting it as 1-byte wide data on the internal bus 10, the byte boundary of the transfer start address of the main memory J/ and the transfer start address of the Puffer Memory Co. Data transfer is possible without being aware of byte boundaries.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, in the case of data transfer between memories via a system bus, where the byte boundaries of the transfer start addresses are different, the byte boundaries of the transfer start addresses can be changed. Data transfer can be done unconsciously, and since it is executed in hardware, the effect of improving processing power can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing one embodiment of an input/output control device according to the present invention, the FA diagram is a diagram for explaining the conventional technology, and FIG. 3 and FIG. FIG. 2 is a specific block configuration diagram of a bus interface circuit and an internal bus switching circuit shown to explain data transfer of the control device. l...processor, co...backer memory, 3...
- Input/output interface circuit, da... bus interface circuit, j... DMA control circuit, 6... internal bus switching circuit, r... input/output control device of the present invention, t...
Input/output device, 10...internal bus, ii...DMA
Control signal, ,
103...Beep)/A-JJ reception data switching, IO4
+...Beep) Review-,? /Receive data switching. 10! ! ... bit 0 - transmission data switching, 106.
...Beep) f-/j transmission data switching, IO-0. Pi\/6-3 transmission data switching, tar...Pit review-31 transmission data switching, l-〇...reception data, lkoto...reception data storage area, /l...transmission data,
lco3...transmission data storage area, 13co...bit l-1! Reception buffer, /30...bit-$
-3/receive buffer, /8...transmit data selector,
A, B, C, D, F, G... I byte data transferred

Claims (1)

[Claims] In an input/output control device of an information processing system, a processor that executes microinstructions, a buffer memory that stores microinstructions, input/output data, and a control table, an input/output interface circuit that controls an interface with an input/output device, and a system It has a bus interface circuit that controls the interface with the bus and an internal bus switching circuit that changes the internal bus data width. An input/output control device characterized by changing the width of data transferred between the input and output control devices.