JPH0195870U - - Google Patents
Info
- Publication number
- JPH0195870U JPH0195870U JP19129487U JP19129487U JPH0195870U JP H0195870 U JPH0195870 U JP H0195870U JP 19129487 U JP19129487 U JP 19129487U JP 19129487 U JP19129487 U JP 19129487U JP H0195870 U JPH0195870 U JP H0195870U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- int
- flop
- flip
- converted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 claims 3
- 238000005070 sampling Methods 0.000 claims 3
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Picture Signal Circuits (AREA)
- Transforming Electric Information Into Light Information (AREA)
Description
第１図は本考案のブロツク構成図、第２図は本
考案の原理を説明するための回路図、第３図及び
第４図はそれぞれ第２図の回路の具体的な回路構
成図、第５図ａ乃至ｆはそれぞれ第２図の回路の
各部の出力波形を示す図、第６図は従来の輪郭強
調回路の回路構成図である。
１，１０，１１，２０，２１……フリツプフロ
ツプ、２……演算手段、３０，４０……除算回路
、５０，６０……減算回路、５１，６１……アダ
ー、５２，６２……インバータ。
Figure 1 is a block configuration diagram of the present invention, Figure 2 is a circuit diagram for explaining the principle of the invention, Figures 3 and 4 are specific circuit configuration diagrams of the circuit in Figure 2, respectively. 5a to 5f are diagrams showing output waveforms of various parts of the circuit of FIG. 2, respectively, and FIG. 6 is a circuit configuration diagram of a conventional edge enhancement circuit. 1, 10, 11, 20, 21... flip-flop, 2... calculation means, 30, 40... division circuit, 50, 60... subtraction circuit, 51, 61... adder, 52, 62... inverter.
Claims (1)
を構成し、上記走査電極に走査信号を供給すると
共に、映像信号をサンプリングしてデイジタル信
号に変換し、サンプリングしたそれぞれを対応す
る電圧信号に変換して上記信号電極に供給するマ
トリクス型表示装置に於いて、上記デイジタル信
号に変換された映像信号を一時記憶するフリツプ
フロツプと、このフリツプフロツプの所定サンプ
リングタイムの出力信号Ｄｎ及びこの所定サンプ
リングタイムの出力信号Ｄｎを使つて遅延させた
信号Ｄｎ＋１及びＤｎ＋２に対し、 Ｄ′ｎ＋１＝｛（１−２２Ｘ）Ｄｎ＋１｝ＩＮ
Ｔ ＋〔（２２ＸＤｎ＋１）ＩＮＴ −｛（Ｄｎ２Ｘ）ＩＮＴ＋（Ｄｎ＋２２
Ｘ）ＩＮＴ｝〕 （但し、Ｘは自然数、ＩＮＴは整数分のみを表
す）の演算を実行する演算手段とを有し、上記演
算手段の演算処理によつて得られた出力信号Ｄ′
ｎに対応する電圧信号を上記信号電極に供給する
ようにしたことを特徴とするマトリクス型表示装
置に於ける輪郭強調回路。[Claims for Utility Model Registration] A matrix panel is constituted by scanning electrodes and signal electrodes, and a scanning signal is supplied to the scanning electrodes, and a video signal is sampled and converted into a digital signal, and each of the sampled signals is converted to a corresponding digital signal. In a matrix type display device that converts the video signal into a voltage signal and supplies it to the signal electrode, there is a flip-flop that temporarily stores the video signal converted into the digital signal, and an output signal Dn of the flip-flop at a predetermined sampling time and the output signal Dn of the flip-flop at a predetermined sampling time. For the signals D n+1 and D n+2 delayed using the sampling time output signal D n , D' n+1 = {(1-22X) D n+1 }IN
T + [(22XD n+1 ) INT −{(D n 2X) INT+(D n+2 2
X) INT}] (where X is a natural number and INT represents only an integer part);
An outline enhancement circuit in a matrix type display device, characterized in that a voltage signal corresponding to n is supplied to the signal electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19129487U JPH0195870U (en) | 1987-12-18 | 1987-12-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19129487U JPH0195870U (en) | 1987-12-18 | 1987-12-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0195870U true JPH0195870U (en) | 1989-06-26 |
Family
ID=31482213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19129487U Pending JPH0195870U (en) | 1987-12-18 | 1987-12-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0195870U (en) |
-
1987
- 1987-12-18 JP JP19129487U patent/JPH0195870U/ja active Pending