JPH0195557A - Manufacture of heterojunction bipolar transistor - Google Patents

Abstract

PURPOSE:To enhance a current gain by a method wherein an emitter layer is formed by laminating microcrystalline silicon (muc-Si) under a specific condition by using a plasma CVD method. CONSTITUTION:An n<+> silicon wafer 1 where an n<-> silicon epi layer 2 has been formed is thermally oxidized; an SiO2 film 4 is formed; this SiO2 film 4 is patterned. In succession, boron is diffused on the surface; a P-region 3 is formed. The SiO2 film 4 is patterned again; a junction face 5' of the P-region 3 and an emitter layer is formed. After that n<+> muc-Si:H 5 is laminated by using a plasma CVD method under the following conductions: 0< concentration of SiH4/H2<=0.1%; 0.01%< concentration of PH3<10%; a gas pressure of 0.01-5Torr; a substrate temperature of room temperature -600 deg.C; a power to be impressed of more than 1mW/cm<2> and less than 100mW/cm<2>. By this setup, a current gain is enhanced.

Description

Detailed Description of the Invention - (Industrial Application Field) The present invention provides an optimal emitter layer manufacturing method for obtaining a heterojunction bipolar transistor having a high current amplification factor and good switching characteristics. It is something that takes place in between.

(Prior Art) In order to speed up the device operation of silicon bipolar transistors, it has been proposed to adopt a hetero-emitter structure.

Heterojunction bipolar transistors, which utilize heterojunctions made by joining dissimilar semiconductor materials, have many advantages over conventional homojunction bipolar transistors made using a single material.

For example, by making the semiconductor material constituting the emitter layer have a wider bandgap than the semiconductor material constituting the base layer, the impurity concentration in the emitter region and the impurity concentration in the base region can be reduced without reducing the emitter injection efficiency. Concentration can be set independently.

Therefore, since the impurity concentration of the base layer can be increased, the base resistance can be lowered and a thin base layer can be formed.

Similarly, since the impurity concentration of the emitter layer can be lowered, the emitter capacitance can be reduced.

Due to these advantages, heterojunction bipolar transistors have the potential to be extremely superior in high frequency characteristics and switching characteristics compared to conventional homojunction bipolar transistors.

When actually constructing such a heterojunction bipolar transistor, it has been proposed to use amorphous silicon carbide (hereinafter referred to as a-5iC:H) for the emitter layer. (Spring Society of Applied Physics, 1988) Figure 5 shows a cross-sectional view of a conventional heterojunction bipolar transistor.

+N silicon epitaxial layer 2 is grown on the n silicon wafer l. Next, a SiO□ film 4 is formed, and after patterning by photolithography, boron is doped by ion implantation or the like to form a P region 3. Subsequently, n''a-Sic:H7 is laminated by plasma CVD method.Finally, SiO is deposited.

Aluminum metal 6 is laminated and wired on the upper surface of the contact hole region 3 and n''a-5i C:H5' on the film 4 by photolithography.

In such a structure, the n-silicon wafer 1 is the collector,
The P region 3 serves as a base, and the na-5iC:H5' serves as an emitter, forming a bipolar transistor.

(Problems to be Solved by the Invention) A-5iC:H used in the emitter layer of a conventional heterojunction bipolar transistor has low conductivity and poor injection efficiency, resulting in a decrease in current gain.

In addition, high frequency characteristics and switching characteristics are inferior.

Furthermore, when the C composition ratio increases, the open level density increases, which may cause deterioration of transistor characteristics and reduction of current gain.

Due to the above-mentioned drawbacks, a hetero bipolar transistor using a-8iC:H in the emitter layer has not been put into practical use.

An object of the present invention was made in view of the above-mentioned problems, and it is an object of the present invention to provide an optimal manufacturing method for forming an emitter layer in order to obtain an element having a high current amplification factor and good switching characteristics. It is.

(Means for Solving the Problems) In order to solve the above problems, the emitter layer of the silicon heterojunction bipolar transistor of the present invention is formed by a plasma CVD method under the following conditions a) 0 < S I H4/
Ht degree ≦0.1%, 0.01% PH H88 degree <10
%, gas pressure 0.01 to 5 T or rb) Substrate temperature Room temperature to 600°C C) Applied RF power 1 mW/cm” or more and 100 W/cm2 or less, microcrystalline silicon (
It is formed by laminating μc-5t).

(Function) μc-5i produced using the above conditions can obtain a high conductivity of 5Ω·C or more. Therefore, a silicon heterojunction bipolar transistor completed using this in the emitter layer has high injection efficiency, high current gain, and has excellent switching characteristics.

(Example) Hereinafter, a method for manufacturing a silicon heterojunction bipolar transistor of the present invention will be described with reference to the drawings.

FIG. 1 shows a manufacturing process diagram of a silicon heterojunction bipolar transistor of the present invention.

As shown in Figure 1(a), n-silicon with a resistance of 0.5 to 5Ω·C is deposited on an n-silicon wafer l with a resistance of 0.02Ω·0 or less.
Using iC14, the n-silicon epitaxial layer 2 is formed by growing to a thickness of about 5 μm at 1150° C.

Next, as shown in FIG. 1(b), the n-silicon epi layer 2
The n-silicon wafer 1 on which the
An iO□ film 4 is formed, and as shown in FIG. 1(C), the SiO□ film 4 is patterned by photolithography.

Subsequently, apply a sufficient amount of B20 to the surface. After adhering, as shown in Fig. 1(d), 10
Perform boron diffusion at 00°C for 20 minutes to achieve a surface concentration of 10"/mouth 1.
, a P region 3 having a depth of about 0.5 μm is formed.

Then, as shown in FIG. 1(e), photolithography is performed again to pattern the SiO film 4, and P
A bonding surface 5' between the region 3 and the emitter layer is formed.

Thereafter, as shown in FIG. 1(f), using the plasma CvD method, a) O<SiH,/HJ degree≦0.1%, 0.01%
<PH, concentration<to%, gas pressure 0.01~5''r
orrb) Substrate temperature, room temperature to 600℃ C) Applied power 1mW/era" or more and 100W/e+n" or less nμc-5i of 5Ω゛1・(to): H5
are stacked at 5000A.

Furthermore, as shown in FIG. 1(g), photolithography is carried out to pattern the SiO film 4 and form a bonding surface 6' between the aluminum metal and the P region 3.

Finally, as shown in FIG. 1(h), aluminum metal 6 is vapor-deposited on the JP region 3 on the nμc-5i:H5 on the back surface of the n-silicon wafer 1, and wiring is performed.

Through the above steps, the silicon heterojunction bipolar transistor of the present invention is completed, with the n silicon wafer 1 serving as the collector, the P region 3 serving as the base, and the nμc-Si:H serving as the emitter.

The μc-Si:H described in this example has a structure containing a microcrystalline phase in amorphous silicon, as shown in FIG. The periphery of the microcrystal is terminated with hydrogen atoms.

FIG. 3 shows the bandgap of μc-Si:H. From the figure, the band gap of μc-Si is 1.95 eV, which is a wide band gap like a-SiC:H. Therefore, the impurity concentration in the emitter region and the impurity concentration in the base region can be set independently without reducing the emitter injection efficiency. Therefore, since the impurity concentration of the base layer can be increased, the base resistance can be lowered and a thin base layer can be formed. Similarly, since the impurity concentration of the emitter layer can be lowered, the emitter capacitance can be reduced.

FIG. 4 shows the relationship between the conductivity of μc-Si:H and RF power. When carried out with an RF power of 60 W or more, a very high value of 5 Ω-1·dl can be obtained.

Therefore, an emitter layer with a wide bandgap, high carrier density, and low resistance can be obtained.

Because the carrier density in the emitter layer is high, if a forward voltage is applied between the emitter and base while applying a reverse voltage between the base and collector, voltage will be injected from the emitter to the base. However, the injection of electrons at this time is a
This is larger than when −9iC:H is used as an emitter.

(Injection efficiency is improved) And since the resistance of the emitter is low, the current gain is improved.

Furthermore, since μc-Si:H does not contain a foreign atom such as carbon (C), there is no increase in localized level density due to lattice strain as in a-9iC:H.

In this example, S i H4/H is added to the raw material gas.
, but instead of H2, He I A r t
A similar emitter layer can be obtained using NLtXe.

(Effects of the Invention) By using the manufacturing method of the present invention, it is possible to form a μC-5i emitter layer with high carrier density and low resistance.

Therefore, the injection efficiency and current gain are improved, and the high frequency characteristics and switching speed of the device are improved, so that a high-speed switching device can be obtained.

Furthermore, the heat resistance of μc-Si is 5% higher than that of a-SiC:H.
Since the temperature rises by about 0℃, post-process heat treatments such as aluminum sintering can be performed at high temperatures, increasing the degree of freedom in process design, and by performing aluminum sintering at high temperatures, it is possible to lower contact resistance. becomes.

[Brief explanation of the drawing]

Figure 1 is a manufacturing process diagram of the silicon heterojunction bipolar transistor of the present invention. Figure 2 is a structural diagram of μc-9i:H. Figure 3 is a diagram showing the band gap of μc-Si:H. FIG. 5, which shows the relationship between conductivity and RF power, is a cross-sectional view of a conventional silicon heterojunction bipolar transistor. 1.φ.n silicon wafer 2...n-silicon layer 3...P region 4...SiO, film 5=nBc-St:H6...aluminum metal

Claims (2)

[Claims] (1) A first step of crystal-growing upper n^- silicon on an n^+ type silicon substrate to form a collector region, and a second step of selectively doping the n silicon layer with boron to form a base region. 2 steps, and a 3rd step of laminating microcrystalline silicon on the base region through a partially etched silicon oxide film so as to bring the base region and the emitter region into contact to form an emitter region. A method for manufacturing a heterojunction bipolar transistor. (2) The step of stacking the microcrystalline silicon is performed using the plasma CVD method under the following conditions a) 0<SiH_4/H_2 concentration≦0.1%, 0.01
%<PH_3 concentration<10%, gas pressure 0.01-5To
rr b) Substrate temperature Room temperature ~ 600℃ c) Applied RF power 1mW/cm^2 or more, 100W
2. A method for manufacturing a heterojunction bipolar transistor according to claim 1, wherein the manufacturing method is performed at a temperature of /cm^2 or less.