JPH09260692A - Compound semiconductor wafer and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a semiconductor wafer from deteriorating in peak current density, even if it is subjected to a thermal treatment. SOLUTION: An I-type compound semiconductor layer 14 which is different in lattice constant from an N<+> -type compound semiconductor layer 13 and a P<+> -type compound semiconductor layer 15 and high in chemical bonding power is provided between the compound semiconductor layer 13 and 15, whereby N-type impurities and P-type impurities are restrained from being diffused through an interface between the layers 13 and 15, when a thermal treatment is carried out for processing a wafer. So that an impurity concentration gradient is kept steep in a semiconductor wafer of this constitution, and the semiconductor wafer is hardly deteriorated in peak tunnel current density. The I layer 14 is formed of Inx Ga1-x As or Inx Ga1-x Asy P1-y , large in chemical bonding power and different in lattice constant from GaAs, whereby N-type impurities and P-type impurities are restrained from being diffused through lattice defects, and a tunnel peak current is hardly dropped in density.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tunnel junction formed by joining ap ⁺ type compound semiconductor layer containing a high concentration of p type impurities and an n ⁺ type compound semiconductor layer containing a high concentration of n type impurities. The invention relates to a compound semiconductor wafer and a semiconductor device.

[0002]

2. Description of the Related Art FIG. 4 is a sectional view of a conventional semiconductor device.

As shown in FIG. 1, the semiconductor device is formed on the n-type compound semiconductor substrate 1 in order by high concentration of n-type impurities by using metal organic vapor phase epitaxy, liquid phase epitaxy or molecular beam epitaxy. To the tunnel junction (p ⁺ -type compound semiconductor layer) 2 and the compound semiconductor (p ⁺ -type compound semiconductor layer) 3 to which a high-concentration p-type impurity having a high carrier concentration is added. ^After forming the compound semiconductor wafer 4 having a ⁺ n ⁺ junction) and cutting the compound semiconductor wafer 4 into a predetermined size, the n-type compound semiconductor substrate 1 and p ⁺
Electrodes 5 and 6 are connected to the type compound semiconductor layer 3, respectively.

[0004]

By the way, in the conventional semiconductor device described above, when the heat treatment is performed when connecting the wirings or the like during the growth process of the respective semiconductor layers 1 to 3, the semiconductor device becomes the n ⁺ type compound semiconductor layer 2 The diffusion of the dopant at the interface with the p ⁺ type compound semiconductor layer 3 allows the n ⁺ type compound semiconductor layer 2 to be diffused.
The interface at deteriorates steepness of the dopant between the p ⁺ -type compound semiconductor layer 3, a low carrier concentration at the interface between the n ⁺ -type compound semiconductor layer 2 and the p ⁺ -type compound semiconductor layer 3 with it Therefore, the tunnel peak current density is reduced in the IV (current-voltage) characteristic.

FIG. 5 shows a conventional semiconductor device at about 700.degree.
It is a figure which shows the IV characteristic before heat-processing and after heat-processing. In the figure, the horizontal axis represents voltage (V),
The horizontal axis represents the current density (A / cm ² ). Solid line L ₃
Indicates the measurement result before the heat treatment, and the broken line L ₄ indicates the measurement result after the heat treatment.

From the figure, the peak current density before heat treatment is 2.
8 A / cm ² and only 0.8 A / c after heat treatment
It can be seen that m ² is reduced to about 30% before the heat treatment.

Therefore, an object of the present invention is to solve the above problems and provide a compound semiconductor wafer and a semiconductor device in which the peak current density does not decrease even if heat treatment is performed.

[0008]

In order to achieve the above object, the compound semiconductor wafer of the present invention has a p ⁺ -type compound semiconductor layer containing a high concentration of p-type impurities and a high concentration of an n-type impurity. in the compound semiconductor wafers by joining a n ⁺ -type compound semiconductor layer to form a tunnel junction, between the p ⁺ -type compound semiconductor layer and the n ⁺ -type compound semiconductor layer, p ⁺
The i-type compound semiconductor layer is formed by differentiating the lattice constant between the type compound semiconductor layer and the n ⁺ type compound semiconductor layer, and having a strong chemical bonding force and no added impurities.

In addition to the above structure, in the compound semiconductor wafer of the present invention, GaAs is used for the p ⁺ type compound semiconductor layer and the n ⁺ type compound semiconductor layer, and In _x Ga is used for the i type compound semiconductor layer.
_1-x As is used.

In addition to the above structure, in the compound semiconductor wafer of the present invention, GaAs is used for the p ⁺ type compound semiconductor layer and the n ⁺ type compound semiconductor layer, and In _x Ga is used for the i type compound semiconductor layer.
_1-x As _y P _1-y is used.

In order to achieve the above object, a semiconductor device of the present invention comprises a p ⁺ type compound semiconductor layer doped with a high concentration of p type impurities and an n ⁺ type compound semiconductor layer doped with a high concentration of n type impurities. in the bonded semiconductor device forming the tunnel junction, between the p ⁺ -type compound semiconductor layer and the n ⁺ -type compound semiconductor layer, the lattice constant a p ⁺ -type compound semiconductor layer and the n ⁺ -type compound semiconductor layer The i-type compound semiconductor layer is different and has a strong chemical bonding force and no impurities are added.

In addition to the above structure, the semiconductor device of the present invention has p
⁺ -Type compound GaA the semiconductor layer and the n ⁺ -type compound semiconductor layer
s, and In _x Ga _1-x As is used for the i-type compound semiconductor layer.

In addition to the above structure, the semiconductor device of the present invention has p
⁺ -Type compound GaA the semiconductor layer and the n ⁺ -type compound semiconductor layer
In _x Ga _1-x As _{y on} the i-type compound semiconductor layer
P _1-y is used.

With the above structure, diffusion of p-type impurities and n-type impurities due to heat treatment during wafer processing at the interface between the p ⁺ -type compound semiconductor layer and the n ⁺ -type compound semiconductor layer is suppressed, and the change in impurity concentration is suppressed. Since the steepness is maintained, the tunnel peak current density does not decrease. Further, the i-type compound semiconductor layer has a strong chemical bonding force and is made of GaAs.
And In _x Ga _1-x As or In _x with different lattice constants
By using Ga _1-x As _y P _{1- y} , the diffusion of n-type impurities and p-type impurities diffused through lattice defects is suppressed and the tunnel peak current density is not reduced.

[0015]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a sectional view showing an embodiment of a semiconductor device using the compound semiconductor wafer of the present invention.

The compound semiconductor wafer 10 is made of n-type GaAs.
On the compound semiconductor substrate 11, G added with an n-type impurity
aAs compound semiconductor layer (hereinafter referred to as “n layer”) 12, n
⁺ Type GaAs compound semiconductor layer (hereinafter referred to as “n ⁺ layer”) 13 in which a type impurity is added at a high concentration, and an In _x Ga _{1 -x} As compound semiconductor layer (hereinafter, referred to as “n ⁺ layer”) as an i-type compound semiconductor layer in which no impurity is added. 14), a p ⁺ type GaAs compound semiconductor layer (hereinafter referred to as “p ⁺ layer”) 15 to which a p-type impurity is added at a high concentration, and a Ga to which a p-type impurity is added.
As compound semiconductor layers (hereinafter referred to as “p layers”) 16 are sequentially stacked.

An n-type GaAs compound semiconductor electrode 17 is formed on the back surface of the n-type GaAs compound semiconductor substrate 11,
A p-type GaAs compound semiconductor electrode 18 is formed on the surface of the p-layer 16.

FIG. 2 shows the semiconductor device shown in FIG.
I-before heat treatment at 0 ° C. for 2 hours and after heat treatment
It is a figure which shows a V characteristic. In the figure, the horizontal axis is voltage (V)
And the vertical axis represents the current density (A / cm ² ).

From the figure, even after the heat treatment at 700 ° C. for 2 hours, the peak current density was reduced by 10%.
As compared with the conventional technique shown in FIG. 5, the effect of suppressing the decrease in current density due to heat treatment could be confirmed.

Next, the optimum conditions will be described.

FIG. 3 is a diagram showing the relationship between the mixed crystal ratio x of the In _x Ga _{1 -x} As compound semiconductor and the magnitude of the lattice constant (angstrom).

The lattice constant of GaAs is 5.654 Å, and when the mixed crystal ratio x becomes 0.4 or more, GaA
Since the s compound semiconductor and the In _x Ga _1-x As compound semiconductor have different lattice lengths, lattice defects occur at the interface between different semiconductors, and a large tunnel current density cannot be obtained.

Therefore, the mixed crystal ratio x of the i-type compound semiconductor layer is set to 0.1 to 0.4, and the thickness of In _x Ga _{1- x} As is set to 0.
By setting the thickness to 8 nm to 3 nm, the mismatch of the lattice constant is gradually relaxed from the interface of GaAs, and the generation of lattice defects is suppressed. Therefore, GaA diffuses through lattice defects.
The diffusion of the n-type impurities and the p-type impurities in s is suppressed, the tunnel peak current density is not reduced, and a large tunnel current density is obtained.

Next, a method of using this embodiment will be described.

A tunnel junction is used as a method of reducing the electric resistance when growing different kinds of compound semiconductors on a compound semiconductor solar cell or when connecting solar cells. By the way, in order to grow a solar cell on a tunnel junction, tunnel characteristics are difficult to appear depending on the growth temperature. However, by using the compound semiconductor wafer or the semiconductor device of the present invention, it is possible to suppress the decrease of the peak current density, and it is possible to reduce the electric resistance in the connection between the solar cells. Therefore, a solar cell with a high output voltage can be obtained by connecting the solar cells in series.

As described above, according to the present embodiment, p ⁺
Between the layer and the n ⁺ layer, different lattice constant from the p ⁺ layer and the n ⁺ layer, and, since the form i-layer chemical bond strength without added strong impurities, even when the heat treatment peak It is possible to provide a compound semiconductor wafer and a semiconductor device in which the current density does not decrease.

In this embodiment, the n ⁺ type, i type, and p ⁺ type compound semiconductors are sequentially formed on the n type compound semiconductor substrate, but the present invention is not limited to this. A p ⁺ -type, an i-type, and an n ⁺ -type compound semiconductor may be sequentially formed thereon. Further, in the present embodiment, In is formed in the i layer.
_Although the case of using _x Ga _1-x As has been described, the present invention is not limited to this, and In _x Ga _1-x As _y P _1-y may be used.

In _x Ga _1-x As _y P _1-y is 0 <x <
It is lattice-matched with GaAs when 0.5 and y = 2x. The optimum film thickness is 0.5 nm to 2.5 nm. In
Since GaAsP has a wide selection range of the mixed crystal ratio, it is possible to control the tunnel current.

[0030]

In summary, according to the present invention, the following excellent effects are exhibited.

Since the i-type compound semiconductor layer is formed between the p ⁺ -type compound semiconductor layer and the n ⁺ -type compound semiconductor layer, it is possible to provide a compound semiconductor wafer and a semiconductor device in which the peak current density does not decrease even if heat treatment is performed. Can be realized.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a semiconductor device using a compound semiconductor wafer of the present invention.

FIG. 2 is a diagram showing IV characteristics before and after heat treatment of the semiconductor device shown in FIG. 1 at about 700 ° C. for 2 hours.

FIG. 3 is a diagram showing a relationship between a mixed crystal ratio x of an In _x Ga _1-x As compound semiconductor and a magnitude of a lattice constant.

FIG. 4 is a cross-sectional view of a conventional semiconductor device.

FIG. 5 is a diagram showing IV characteristics before and after heat treatment of a conventional semiconductor device at about 700 ° C. for 2 hours.

[Explanation of symbols]

10 compound semiconductor wafer 11 n-type GaAs compound semiconductor substrate 12 GaAs compound semiconductor layer (n layer) 13 n ⁺ type GaAs compound semiconductor layer (n ⁺ layer) 14 In _x Ga _1-x As compound semiconductor layer (i layer) 15 p ⁺ GaAs type compound semiconductor layer (p ⁺ layer) 16 GaAs compound semiconductor layer (p layer) 17 n-type GaAs compound semiconductor electrode 18 p-type GaAs compound semiconductor electrode

Claims (6)

[Claims] 1. A compound semiconductor wafer having a tunnel junction formed by joining a p ⁺ -type compound semiconductor layer containing a high concentration of p-type impurities and an n ⁺ -type compound semiconductor layer containing a high concentration of an n-type impurity. In the above, the p ⁺ type compound semiconductor layer and the n ⁺ type compound semiconductor layer have different lattice constants from each other and a chemical bonding force between the p ⁺ type compound semiconductor layer and the n ⁺ type compound semiconductor layer. A compound semiconductor wafer having an i-type compound semiconductor layer which is not strongly doped. 2. The p ⁺ type compound semiconductor layer and the n ⁺
Using GaAs on type compound semiconductor layer, a compound semiconductor wafer according to claim 1, wherein using the In _x Ga _1-x As in the i-type compound semiconductor layer. 3. The p ⁺ type compound semiconductor layer and the n ⁺
Using GaAs on type compound semiconductor layer, according to claim 1 using the _{In x Ga 1-x As y} P 1-y in the i-type compound semiconductor layer
The compound semiconductor wafer described. 4. A semiconductor device in which a tunnel junction is formed by joining a p ⁺ -type compound semiconductor layer containing a high concentration of p-type impurities and an n ⁺ -type compound semiconductor layer containing a high concentration of an n-type impurity. , The p ⁺ type compound semiconductor layer and the n
⁺ Between the mold compound semiconductor layer different in lattice constant between the p ⁺ -type compound semiconductor layer and the n ⁺ -type compound semiconductor layer,
A semiconductor device having an i-type compound semiconductor layer having a strong chemical bond and no added impurities. 5. The p ⁺ type compound semiconductor layer and the n ⁺
The semiconductor device according to claim 4, wherein GaAs is used for the type compound semiconductor layer, and In _x Ga _1-x As is used for the i type compound semiconductor layer. 6. The p ⁺ type compound semiconductor layer and the n ⁺ type compound semiconductor layer.
Using GaAs on type compound semiconductor layer, according to claim 4 using _{In x Ga 1-x As y} P 1-y in the i-type compound semiconductor layer
13. The semiconductor device according to claim 1.