JPH0194674A - Heterojunction field-effect transistor - Google Patents

Abstract

PURPOSE:To prevent Cr diffusions or crystalline defects from occurring by providing a buffer layer whose conductive type is different from a undoped semiconductor channel between the semi-insulating crystalline substrate and a nondoped semiconductor channel layer. CONSTITUTION:A heterojunction field-effect transistor comprises a semi- insulating crystalline layer 1; an undoped semiconductor channel layer 3 formed on such semi-insulating crystalline substrate 1; an electron supplying layer 5 formed on such undoped semiconductor channel layer 3; and a control electrode 7 formed on such electron supplying layer 5. Such heterojunction field-effect transistor further comprises a buffer layer 2 whose conductive type is different from the nondoped semiconductor channel layer 3 between the semiinsulating crystalline substrate 1 and the nondoped semiconductor channel layer 3. For example, a P-type GaAs layer 2, a undoped GaAs layer 3, an undoped AlxGal-xAs layer 4 are formed on a semi-insulating GaAs substrate 1. Further, after growing an Si-doped AlxGa1-xAs layer 5, a source electrode 6a, a drain electrode 6b, and a gate electrode 7 are formed.

Description

[Detailed description of the invention] (a) Field of industrial application The present invention relates to a heterojunction field effect transistor using two-dimensional electron gas at the interface of a frame-heterojunction. A heterojunction field effect transistor (hereinafter referred to as a heterojunction FET) frame in which semiconductor crystals with a large forbidden band width are stacked, is known to form a two-dimensional electron gas at the heterojunction interface under certain conditions. High electron mobility transistors (HEMTs), which have recently attracted attention as high-speed semiconductor devices, are also devices that utilize the two-dimensional electron gas at the heterojunction interface (for example, Journal of Crystal Gro
wth 56 (1982) 455-463, North
Ho1land Poolishing Compa
ny)0 Figure 3 is a schematic cross-sectional structural diagram of a conventional HIIT using a HAIGaAs-GaAs heterojunction, and the figure shows ρ
The manufacturing method will be explained below.

First, we applied molecular beam epitaxy (M8fC) or organometallic epitaxy (QM) on a semi-insulating GaAS substrate (111).
VP] li: ) Technology zp, Nondo 7G a A
The S layer σ21 was grown to a thickness of 1 μm, and then the non-doped 1GaAsJil (on top of the non-doped 7AlxGa
Grow to a thickness of t-XASJiiσ31-60A,
Next, on the non-doped AlxGa1-xAs@σ3
Do7” AlXGa1-XAS layer (S i 4y;
The total composition of AlAs in xHAl Ohmic metal consisting of Au-Ge-Ni etc.
After lifting off @Kxv, the source electrode forming part and the drain are left in the electrode forming part, and alloying is performed to form an ohmic region t-S edge AlxGa1-xAs layer α.
4. Form a source electrode (15a) and a drain electrode (15b) by penetrating the non-doped 1Al xAs layer (1
Shityabaria on 41? Along with the metal (Al) to be formed, gold (Ti-Pt-Au, etc.)'/-X electrode (15a)
= The gate electrode σe6 is formed by selectively depositing the drain 7 between the electrode (tso) by a lift-off method.

In the eHEM fabricated by the above-described manufacturing method, a two-dimensional electron gas channel (17) is formed on the nucleus layer 1121 side of the heterojunction interface between the non-doped 1AlxGat-xAs1σJ and the non-doped GaAs layer α2. $1
The do-yAlxGa 1-xAs layer (t41 is the gate electrode i16) is depleted in the phosphor or surface level, and the non-do-1AlxG is added to the positively ionized impurity.
When electrons with negative charges occur at the heterojunction interface with the a t-xAs layer a31 and the GaAs layer O2, a two-dimensional electron gas channel (171) is formed. Figure 4 shows a conventional HEMT. Gate electrode-81 doped Al
XGa + -XAS layer - non-doped AlxGa1-xA
FIG. 2 is a conduction band energy diagram spanning an s layer and a non-doped GaAs layer. In the figure, in the A1 region, S1 do 7” Al x Ga 1-
xAs layer fi4) Ic4A2 region 41/7 F-p Al
xGa 1-XAS layer σ3, two-dimensional electron gas channel 171 in A3 region, non-doped 7G a in A4 region
A 5ljJr17J respectively, and the prohibited band [i
Al machining A2 area is approximately 1.80eV, A5o:
and n17t where the A4 region is #1.43eV, the interface between the A2 region and the A5 region, that is, Al xGa t -x”
S ml (131tG a A , S !a (1
21t<7) Het Q junction interface + 7) E conduction band energy difference is approximately 0.32 e V □ At the hetero junction interface r
zAlxGa 1-xAs/IF (131 and GaAsm
Both a'a and a'a are non-doped 1, and the ionized impurities are extremely small because they are separated from the ionized impurities of the S1 doped 7Al x Ga t -XAS layer αΦ. Therefore, the source electrode (152L) and the drain electrode (152L)
51)) When the full voltage is applied between
The dimension electron gas concentration rls is approximately 5×10 Cm.

By controlling all the electrons passing through the two-dimensional electron gas channel by the electric field effect of the gate electrode [161], the device shown in FIG. 2 performs a transistor operation as a HEMT. In other words, the concentration of L two-dimensional electron gas can be controlled by the gate-source electrode voltage VGs applied to the gate electrode σG. The -12-dimensional electron gas concentration nS and the gate-source electrode voltage VG8 have the following relationship □ AVG3 n S ”” n 60 + □ Friend, the two dimensions when nao: V'Ga-0 are child gas a degrees CA: Si do-7"AlXGa1-XAaN
The electrostatic capacitance q : is the charge of the child 1 Problems to be solved by the invention
2 is a thin, semi-insulating GaAS substrate (Cr from Lll)
◎ On the other hand, to avoid the influence of diffusion of Cr or crystal defects of the substrate (II+), it is necessary to thicken the non-doped GaAS layer a7JS. For career guidance in the sexual area (area B in Figure 4),
In view of the above-mentioned problems, the present invention has been designed to reduce the amount of Cr diffusion or crystallization without creating the entire neutral region. The purpose of the present invention is to provide a heterojunction zero field effect transistor that can avoid the effects of defects and the like.

(b) Means for solving all the problems in the world The present invention includes a semi-insulating crystal substrate, a non-doped semiconductor chill layer provided on the semi-insulating crystal substrate, and a non-doped semiconductor chill layer provided on the non-doped semiconductor channel layer. an electron supply layer;
In a heterojunction field effect transistor comprising a control @electrode provided on the electron supply layer, the node-1 semiconductor is provided between the semi-insulating crystal substrate II and the non-doped semiconductor chill layer. It is a heterojunction field effect transistor characterized by a buffer layer having a conductivity type different from that of the channel layer. Since different L-shaped buffer layers are provided, a PN junction is formed between this buffer layer and the non-doped semiconductor chill layer, and
The buffer layer prevents the diffusion of Cr in the semi-insulating crystal substrate and the effects of wart crystal defects.

(f) Example FIG. 1 is a schematic sectional view of a HEMT using a heterojunction according to the present invention, and the manufacturing method thereof will be explained below.

First, a semi-insulating GaAs substrate (1+ for semi-insulating crystal substrates)
Using molecular beam epitaxy (MBF) technique W, P-type Ga
As layer (loose Nj) is grown to a thickness of 12+i 3 am □Next, 3 non-beef GaA layers (non-doped semiconductor chill layer) are grown on #P type GaAS layer 12
+31'k was grown to a thickness of 1 μm, and non-doped AlxG was further grown on the non-doped 7G a A 8913+.
Grow to the thickness of a1-xAs notification 14+Q60A◎
A two-dimensional electron channel (8+) is formed on the n13+ side of the heterojunction interface between the non-doped 1A1xGa1-XAS5141 and the non-doped 7'' Ga AS layer I3I.

Next, Nondo 7” AlXGa 1-XASW14J
Mf3E technique q4VcLr), Si)'-pAlx
Ga 1- x A S m ('M, child-income group) 1
5+i 0.1 μm (7) When grown in a thick square, the S1 concentration is 2×1018am−”r,sp,x
HA 1xGa 1-x This is a numerical value indicating the composition of AlAs in Asjil, approximately 0.3. After that, an ohmic metal made of Au-Ge-Ni etc. is placed on the heteroepitaxial substrate formed by these two. The metal is deposited using the lift-off method, leaving all of the metal in the drain electrode forming area, and then performing the alloying process to form the ohmic area.
-XAS layer (source electrode (6a) penetrated into 51,
After forming the drain electrode (6o), the metal (A1) for forming the SiGtki barrier on the KSi'-7'' AlXGa1-XAS layer 15+ is gold [(
T1-Pt-Au) etc. are selectively deposited between all the source electrodes (6a) and the source electrodes (6b) by the lift-off method, and the gate electrode (control electrode) 17+f is formed. In the hall, Nondo 7G a A S Calendar 131
A p-N junction is formed between the non-beef GaAs layer 13+ and the P-type caAs layer +21, and no neutral region is generated in the non-beef GaAs layer 13+.

Figure 2 shows the gate electrode of HEMT according to the present invention - AIXG.
a 1-XAS@-No゛'/AG a A
s H-1)"i≠-4 This is a conduction band energy diagram spanning the GaAs layer ◎A1 region rC8iF'-1AlxG in the figure
a1-xAs layer (51 d, A2 region tl'X/7 do 7
Al xGat -xA1 layer 14+, two-dimensional electron gas channel (8) in A3 region, non-doped 7G in A4 region
The aAS layer +3; corresponds to the As region and the P-type GaAs layer 121, respectively, and the prohibited belt singing frame A1 and A2 regions are approximately 1.80 e V% A3 and A4 regions are approximately 1.43.
eVte;h le, -1 to 2, the interface between the A2 region and the A3 region, that is, the AlxGat-xAs layer 141 and the Ga
The conduction band energy difference at the heterojunction interface with A s M+3+ is approximately 0.32'e\. It is clear from this figure that no neutral region is generated, and only the two-dimensional electron gas generated at the heterojunction interface becomes a current, making pinch-off possible.

It, the influence of Cr diffusion of semi-insulating GaA3 substrate + II, crystal defects, etc. is also P-type Ga As N1121
It can be prevented by

In the above example, the MBE method was used to grow each layer.
There are many methods that can form a steep heterojunction interface, such as metal organic epitaxy (QMVPE) technology.

Furthermore, t non-do 7Alx is interposed as a spacer layer.
It is also possible to omit the Ga+-xAs layer+3+i.

Furthermore, it is obvious that the present invention can be applied to rzInGaAs-In AI As heterojunctions, InP-1nGaAs junctions, etc., and can be applied not only to two-dimensional electron gas but also to two-dimensional hole gas heterojunction field effect transistors using gold. Effects of the Invention As is clear from the above description, there is a buffer layer between the semi-insulating crystal substrate and the non-doped semiconductor chill layer, which has a different conductivity type from the non-doped semiconductor chill layer Since the layer is provided, there is no P between the non-doped semiconductor chill layer and the buffer layer.
-8 Junction is formed and no active region is generated. Therefore, only the two-dimensional electron gas generated at the heterojunction interface becomes a current, making pinch-off possible. In addition, the effects of δ crystal defects and the like can be prevented by the buffer layer, and mobility does not decrease.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of a heterojunction FET according to the present invention, FIG. 2 is a conduction band energy diagram of a heterojunction FET according to the present invention, and FIG. 3 is a schematic cross-sectional view of a conventional heterojunction FET. FIG. 4 is a conduction band energy diagram of a conventional heterojunction FET. Mountain: Semi-insulating GaA19 substrate (semi-insulating crystal substrate)
, +21-...P-type GaAs layer (buffer layer), +31
-...Non-doped 7" GaAS layer (non-doped semiconductor chill layer), (4)...Non-doped 7" Al xGa
1-x AsNJ, +5l-8i door 1AlxGa
t-xAs# (child supply layer, (6a)...source electrode, (61))...drain electrode, (71...
Gate electrode, 18+...2-dimensional electron gas channel. Applicant Sanyo Electric Co., Ltd. Agent Patent attorney Takuji Nishino [1 other person] Figure 1 Figure 2 2 Enemy Figure 3 Figure 4 Δfug

Claims (1)

[Claims] 1. A semi-insulating crystal substrate, a non-doped semiconductor channel layer provided on this semi-insulating crystal substrate, an electron supply layer provided on this non-doped semiconductor channel layer, and this electron supply a control electrode provided on a layer, a buffer layer having a conductivity type different from that of the non-doped semiconductor channel layer is provided between the semi-insulating crystal substrate and the non-doped semiconductor channel layer. A heterojunction field effect transistor characterized by: