JPH0194589A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To surely execute refreshing operation without damaging read/write operation even when a refreshing cycle is made to be long by setting a term gently charging a sense amplifier activating signal longer at the time of the refreshing operation than that at the time of normal operation. CONSTITUTION:At the refreshing time, the term gently charging the sense amplifier activating signal, the inverse of phis is set time (tc) longer than the normal read/write term (tb). Therefore, even when the charge of a memory cell capacitor C1 is lost to some degree by various leak current caused by the long refreshing cycle accompanied with making a device to be bigger capacity, detection and amplification can be sufficiently executed. Besides, at the normal read/write time, as the first transition operation of the signal, the inverse of phis is executed at an usual speed, the normal read/write operation is not damaged in the least. Thus, the refreshing operation can be surely executed even in the refreshing cycle which is made to be longer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device having a refresh function, and particularly to refresh control of a dynamic RAM.

[Conventional technology]

As a conventional refresh control circuit, IEICE Transactions (C), vol, J-66C, 1, DD, 62
-69° (January 1982).

FIG. 5 is a block diagram thereof.

In the figure, 1 is a refresh control circuit, 2 is a timer, 3 is a refresh control section, 4 is a refresh address counter, 5 is a multiplexer, 6 is a RAS control section, 7
is a CAS control unit. REF is the refresh control signal, which is generated by the input signal from the dedicated human power bin or a combination of other input signals. Also, A.

~A6 is an address input signal, RAS is a row address strobe signal, and CAS is a column address strobe signal.

The refresh address counter 4 includes a multi-stage toggle flip-flop FF as shown in the detailed circuit diagram of FIG.
It is used as a refresh address only during internal refresh.

Further, as shown in FIG. 6, the multiplexer 5 inputs the address input signal A-A6, which is an external signal, through the transistors T,1 to the output signal Q of the refresh address counter 4, which is an internal signal. -06 to transistor "r2"
It is connected to the input part of the address buffer 8 via
By sending the multiplex inversion signal MUX to the control electrode of the transistor Tr1 and the multiplex signal MUx to the control electrode of the transistor "r2, any signal (Ao
-80 or Q-Q6) is valid. Also, address input signal A. -A6. A transistor Tr3 is provided between the multiplexers 5 to which an address latch signal φAL is applied to a control electrode.

FIG. 7 is a waveform diagram showing the refresh operation of the dynamic RAM having the refresh control circuit shown in FIGS. 5 and 6. The operation will be explained below with reference to the same figure.

After the signal RAS changes from “L II” to “H”, the signal @
After a time equal to the precharge time of RAS has elapsed, the refresh control signal REF is allowed to change from "H" to 'L'. This time is the time required to precharge the sense amplifier system (not shown). Yes, auto-refresh occurs at time t.

The process starts by changing the signal REF from "H11" to 'L', and the sequence is as follows.

Time t; multiplex signal MUX becomes HI1,
The multiplex inversion signal MUX becomes LIT and the multiplexer 5 outputs the output Q from the refresh address counter 4. -06 is input to address buffer 18. When the signal M (JX' whose rise is delayed by several ns from the signal MUX) from the refresh control unit 3 is input to the RAS control unit 6 via the Nant gate, the internal RAS signal (
Int, RAS) changes from “L II” to “H”.

Time t2: Address buffer 8 is activated by signals Int and RAS as triggers, and a combination of addresses determined by refresh address counter 4 is input to a row decoder (not shown). Then, the word line clock φX rises from "L" to "HII".In terms of circuit design,
If the refresh address counter 4 starts counting up from this point, the address buffer 8
Since the data loading is completed at time t1, this count-up can be made to have no effect on the address buffer 8.

Time t3: The sense amplifier is activated, the information in the memory cell is determined by the sense amplifier, and the memory cell is rewritten, that is, refreshed.

Time t: RAS control unit 6 sends refresh end signal R
EF END is generated in the refresh control unit 3, and when this is triggered, the signal MUX' returns from LIT to "H". Therefore, the signal 1nt, RAS changes from H'' to L'', and precharging of the sense amplifier system is started again to prepare for the next memory operation or refresh operation.

In addition, in the case of a refresh cycle in which internal refresh is automatically started by timer 2, the refresh request signal REF R from timer 2 is sent instead of the signal REF.
The EQ performs an internal refresh cycle.

(Problems to be Solved by the Invention) Since the conventional dynamic RAM refresh control circuit is configured as described above, the operation after the word line clock φ8 rises in the refresh cycle is a normal read operation. /write cycle, and the sensitivity of the sense amplifier that senses and amplifies the minute potential difference between bit line potentials is also the same.

However, as the capacity of dynamic RAM increases, the refresh cycle becomes longer, and when performing a refresh operation by reading the storage charge of memory cells lost due to various leakage currents to the bit line, the same sense as a normal read/write cycle is required. There was a problem with the amplifier's sensitivity that the possibility of erroneous detection and amplification increased.
This invention has been made to solve the above-mentioned problems, and provides a semiconductor memory device that can reliably perform refresh operations even when the refresh cycle becomes longer without impairing read/write operations. With the goal.

[Means for solving problems]

In the semiconductor memory device according to the present invention, the period m during which the sense amplifier activation signal is gently discharged is set to be longer during the refresh operation than during the normal operation.

[Effect]

In the present invention, the period for slowly discharging the sense amplifier activation signal during the refresh operation is set to be longer than during the normal operation, so that the minute potential difference that occurs between the bit lines is amplified even during the normal operation.

〔Example〕

FIG. 1 shows a dynamic RAM which is an embodiment of the present invention.
FIG. 2 is a circuit configuration diagram showing a sense amplifier system in FIG. In the figure, MC is a memory cell, which is composed of one transistor Q1 and a memory capacitor C1 connected in series, and a constant voltage V, - is applied to one electrode of the memory capacitor C1. Further, one electrode of the transistor Q1 is connected to a bit line 8m (BL), and a control electrode is connected to a word line WL.

Reference numeral 11 denotes a sense amplifier, which constitutes a balanced flip-flop using transistors Q2 and Q3. One sense amplifier is provided between bit lines 8L and 81, and detects and amplifies the potential difference between bit lines BL and BL.

Specifically, one electrode of the transistor Q2 and the control electrode of the transistor Q3 are connected to the bit line BL, and the bit line B
One electrode of transistor Q3 and transistor Q2 are connected to L.
, and connect the control electrodes of transistors Q2. The other electrode of Q3 is commonly connected to the connection point N. Further, each sense amplifier 11 is connected to a connection line via a connection point N.

12 is a discharge circuit, which is connected to the connection line and receives the word line clock φ゛, the refresh control signal REF,
REF is used as an input signal.

In the discharge circuit 12, there is a transistor Q4 with a connecting line connected to one electrode and a ground level connected to the other electrode. Q5 is provided, and the channel width of transistor Q4 is small (the channel width of transistor Q5 is set to be large. Also, the word line clock φ is connected to transistor Q via the slow path 13
4 is applied as a signal $1 to the control electrode of delay circuit 13.
．． A delay circuit 13° switch SW2 . The switch SW1, which is applied as the signal S2 to the control electrode (path R2) of the transistor Q5 via the delay circuit 15.16, receives the refresh control signal REF -II
The switch SW2 is closed when the refresh control signal REF is at the "L" level (REF is at the HI! level). Therefore, switches SW1 and SW2 are never closed at the same time. Further, the delay circuit 13 is for time t3, the delay circuits 14 and 15 are for time tb, and the delay circuit 16 is for time t. This is a circuit that delays signal propagation.

FIG. 2 shows a normal read/write operation when the refresh control circuit shown in FIG. 1 is used (FIG. 2(a)).

FIG. 3 is a waveform diagram showing a refresh operation (FIG. 2(b)).

The operation will be explained below with reference to the same figure.

First, normal read/write operations will be explained. At this time, the signal REF is “L” level, and the signal REF is “H” level.
''' level, switch SW1 closes and switch S
W2 is open. Therefore, the propagation path of the signal $2 becomes the path R1. In a normal read/write operation, as shown in FIG.
'' level, and the potential of the selected word line WL rises.

Then, the transistor Q1 in the memory cell MC whose control electrode is connected to the word line WL whose potential has increased becomes conductive, and the charge accumulated in the memory capacitor C1 is transferred to the bit line B.
Take it out to L or BL.

After word line lock φ8 rises, word line WL.

Considering the time constants of bit lines BL and 8L, bit line B'L
, in order to provide enough time for the change in potential of BL to reach the control electrodes of transistors Q2 and Q3, the HIT level signal @S1 is transmitted to the transistors in the discharge circuit 12 at time t1 delayed by time t via the delay circuit 13. Applied to the gate of Q4. Then, the transistor Q4 with a small channel width becomes conductive, and the sense amplifier activation signal φ goes to ii Hto level.

discharges slowly. The sensitivity of the sense amplifier is determined by the length of this gradual discharge period. If this period is long, the bit lines 81 to 81. This is because the minute potential difference occurring between all is further amplified.

From time t1 through the delay circuit 14 on path R1, time t,
At delayed time t2, an H'' level signal S2 is applied to the gate of a transistor Q5 with a large channel width, which turns on the sense amplifier activation signal φ.
, discharge rapidly. Therefore, the period for slowly discharging the sense amplifier activation signal φ is at time t ``”' t
2, that is, the delay time t caused by the delay circuit 14 on the path R1, and this time tb is long enough to prevent malfunction during normal reading/writing.

It is set to amplify the potential difference between 81 and 81.

Next, the refresh operation will be explained. At this time, since the signal REF is at the "L" level and the signal @REF is at the "H11 level," the switch SW2 is closed and the switch SW1 is open. Therefore, the propagation path of the signal S2 becomes the path R2. The refresh l operation is performed at time t, as shown in FIG.
. The word line clock φ8 rises to the "H" level, and the potential of the selected word line WL rises. Then, the transistor Q1 in the memory cell MC whose control electrode is connected to the word IaWL whose potential has increased becomes conductive. The charge accumulated in the memory capacitor C1 is transferred to the bit line 8L or B.
Take it out to L. Time t. After that, time t is delayed by passing through the delay circuit 13.

An "H" level signal S1 is applied to the gate of a transistor Q4 having a small channel width. Then, transistor Q4 becomes conductive, and sense amplifier activation signal φ8 at "H" level is slowly discharged. The operation up to this point is the same as normal reading/writing.

Delay circuit 15 on route R2 from time t1. ．． At time t3 delayed by time (tb+tC) through 16, the "H" level signal S2 is applied to the gate of the transistor Q5 having a large channel width, and the transistor Q5 becomes conductive, rapidly discharging the sense amplifier activation signal φ. Therefore, the period for slowly discharging the sense amplifier activation signal φ is from time t1 to
t3, that is, the delay time (1b+16) caused by the delay circuit 15.16 on the path R2, and the bit line BL,
Even if the potential difference between BL is quite small, the difference can be amplified to the extent that it does not malfunction, and the sensitivity of the sense amplifier is set to be extremely high.

In this way, the period during which the sense amplifier activation signal φ is slowly discharged during refresh is set to a time t longer than the period tb during normal read/write. By setting this value to be longer, even if the charge in the memory cell capacitor C1 is lost to some extent due to various leakage currents due to a longer refresh cycle due to an increase in capacity, it can be sufficiently sensed and amplified. Furthermore, during normal writing/reading, the fall operation of the sense amplifier activation signal φ8 is performed at the conventional speed, so that normal reading/writing operations are not impaired in any way.

FIG. 3 shows Dynamink R which is another embodiment of this invention.
FIG. 2 is a circuit configuration diagram showing a sense amplifier system in AM. Hereinafter, only the points different from the embodiment shown in FIG. 1 will be described. This sense amplifier system has two types of transistors, Q4a (during normal operation) and Q4b (
(during refresh) is provided, and a delay circuit 13a with a delay time t8 is provided.
is provided between the switch SW2 on the path R1 and the u delay circuit 14, and a delay circuit 13b having the same delay time ta is provided between the switch SW2. It is provided between the delay circuits 15. The channel width of transistor Q4a is the same as that of transistor Q4 in FIG.
The channel width of transistor Q4b is set to be even smaller than that of transistor Q4a.
A signal S1 is applied from the delay circuit 13a to the control electrode of the transistor Q4a, and a signal 81' from the delay circuit 13b is applied to the control electrode of the transistor Q4b.

With this configuration, as shown in the waveform diagram in Figure 4, the waveforms are different during normal operation ((a) in the figure) and during freshness (((a) in the figure).
b)), a period during which the sense amplifier activation signal φ is slowly discharged (during normal operation: t).

During refresh: tb + tC> In addition, during this period, only transistor Q4a is made conductive during normal operation, and only transistor Q4b is made conductive during refresh.
The slope of gentle discharge (2 during normal operation, 2' during refresh, IKI>IK' 1) is also changed. In this way, the sense amplifier sensitivity can also be improved,
This makes it easier to optimize the discharge of the sense amplifier activation signal φ.

Note that in these embodiments, N
Although the description has been made using a MOS sense amplifier, the present invention can also be applied to a dynamic RAM using a folded bit line type sense amplifier, one using a 0MO3 sense amplifier, or the like. Further, the connection of the delay circuit and the delay time setting are not limited to these embodiments.

〔Effect of the invention〕

As explained above, according to the present invention, by limiting the period during which the sense amplifier activation signal is gradually discharged during the refresh operation to be longer than during normal operation, the sense amplifier sensitivity is set to be highly accurate only during the refresh operation. Therefore, without impairing normal read/load operations,
Refresh operations can be performed reliably even in longer refresh cycles.

[Brief explanation of the drawing]

FIG. 1 shows a dynamic RAM which is an embodiment of the present invention.
2 is a waveform diagram showing the operation of the dynamic RAM shown in FIG. 1, and FIG. 3 shows a sense amplifier system of a dynamic RAM according to another embodiment of the present invention. 4 is a waveform diagram showing the operation of the dynamic RAM shown in FIG. 3, FIG. 5 is a block diagram showing the refresh control circuit of a conventional dynamic RAM, and FIG. 6 is a detailed diagram of FIG. 5. FIG. 7 is a waveform diagram showing the operation of a conventional dynamic RAM. In the figure, 11 is a sense amplifier, 12 is a discharge circuit, 1
3 to 16 are delay circuits, Q4. Q4a, Q4b, and Q5 are transistors, SW1 and 8W2 are switches, and φ8 is a word line clock, REF, and RE activation signals. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) A semiconductor memory device having a refresh function, characterized in that a period during which a sense amplifier activation signal is slowly discharged during a refresh operation is set longer than during a normal operation. (2) The semiconductor memory according to claim 1, wherein during a period in which the sense amplifier activation signal is slowly discharged during refreshing, the potential drop rate of the sense amplifier activation signal is slower than during normal operation. Device.