JPH06150696A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To detect a marginal memory cell and hence to enhance the reliability by stopping the operation of a circuit for boosting a word line at the time of a test mode, intentionally performing a marginal write-in and judging whether the write-in has properly been performed or not. CONSTITUTION:At the time of the test mode, a test mode signal TE is at an L-level while an output of an AND circuit 11 is also at an L-level, and the boosting operation is stopped by a delay circuit 9. Now, when R' and RAS' signals are at an L-level respectively, and word line activating signals X and XL are boosted up to a voltage Vcc at the time of t0, and then a word line WL1 is boosted up to the voltage Vcc at t1, data of a memory cell is transmitted to bit lines BL1 and 0. However, because of stoppage of the boosting operation of the circuit 9, data is hardly transmitted between the marginal cell and the bit line. Under this condition, marginal write-in and read-out are intentionally performed, and the marginal memory can be detected out depending on whether these operations have properly been performed or not. Thus, the reliability is enhance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of detecting a memory cell having no margin in reliability of data writing or reading operation and obtaining high reliability. It relates to the device.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional semiconductor memory device D
It is a circuit diagram showing a memory cell of RAM. In the figure, 1 indicates one unit of a memory cell, and word lines WL0, WL1 and bit lines BL0, B provided orthogonally to each other.
It is provided near the intersection of L1. 2 is a transistor whose gate is connected to the word line WL1, 3 is a capacitor connected to the source of this transistor 2, 4
Is a parasitic resistance whose one end is connected to the bit line BL0 and whose other end is connected to the drain of the transistor 2, and these transistor 2, capacitor 3 and parasitic resistance 4 constitute a memory cell. Further, 5 is a sense amplifier connected to the bit lines BL0 and BL0 bar, and 6 is the bit lines BL1 and B
It is a sense amplifier connected to the L1 bar.

Although not shown here, the bit line BL
0, BL1 and the like are composed of two lines respectively transmitting signals of opposite polarities, and the sense amplifiers 5 and 6 differentially amplify these signals.

FIG. 8 is a circuit diagram showing a booster circuit in a conventional semiconductor memory device. Reference numeral 7 is a signal formed based on an external row address strobe signal (hereinafter referred to as RAS bar signal) and synchronized with the RAS bar signal. An input terminal to which X is input, 8 is an output terminal that outputs a boosted voltage to a word line (not shown), 9 is a delay circuit whose input side is connected to the input terminal 7, and 8 is an output of the delay circuit 9 at one end. Is a capacitor connected to the output terminal 8 at the other end.

Next, the operation will be described with reference to FIG. When the RAS bar signal becomes low level at time t = t0, the boosted voltage V _CC + α is transmitted to the word line WL1 at t = t1 from the booster circuit. Word line W
When the voltage of L1 becomes V _CC + α, the charges accumulated in the capacitor 3 of the memory cell 1 are transferred to the bit lines BL0 and BL1. Further, at t = t2, the sense amplifiers 5 and 6 start operating and the potentials of the bit lines BL0 and BL1 are amplified.

[0006]

By the way, in recent years, as the capacity of semiconductor memory devices, especially DRAMs has been increased and the size of memory cells has been reduced, the capacity of transistors and capacitors forming a memory cell array is likely to vary. In some memory cells, there is a margin (hereinafter referred to as marginal) in which there is no margin in reliability of data writing or reading operation. For example, in the circuit operation of FIG. 7 described in FIG. 9, when the parasitic resistance 4 is too large due to variations in the memory cell 1, a marginal memory cell is generated in which the accumulated charge of the memory cell is not sufficiently transmitted. Sometimes. In such a case, the data may be correctly amplified like BL1 (BL1 bar) shown in (E) of FIG. 9, or like BL0 (BL0 bar) shown in (F) of FIG. Data may be amplified by mistake.

Therefore, the reliability of the semiconductor memory device is guaranteed,
In order to obtain a highly reliable semiconductor memory device, it is necessary to detect these marginal memory cells and, for example, replace these memory cells with a memory cell having a margin. Due to the above-mentioned configuration, there is a problem that a marginal memory cell cannot be detected and therefore high reliability cannot be guaranteed.

The present invention has been made to solve the above-mentioned problems, and can detect marginal memory cells. Therefore, for example, these marginal memory cells are replaced with redundant memory cells. Therefore, the object is to obtain a highly reliable semiconductor memory device.

[0009]

A semiconductor memory device according to the present invention is provided with means for intentionally performing marginal writing in a test mode, and for example, by judging whether or not the writing has been correctly performed. It is designed to detect a marginal memory cell.

That is, in the semiconductor memory device according to the first aspect of the present invention, the word line is set in the test mode for detecting a memory cell having no margin in reliability of data writing or reading operation among the plurality of memory cells. A stop means for stopping the boosting operation of the boosting circuit for boosting is provided.

According to a second aspect of the present invention, the semiconductor memory device uses the data line in the test mode for detecting a memory cell having no margin in reliability of data write or read operation among the plurality of memory cells. It is provided with a means for shortening the data transfer time.

Further, according to a third aspect of the present invention, in the semiconductor memory device, the word line is set in the test mode in which a memory cell having no margin in reliability of data write or read operation is detected among the plurality of memory cells. It is provided with means for shortening the operating time of the booster circuit for boosting.

[0013]

According to the semiconductor memory device of the first aspect of the present invention, the stop means stops the boosting operation of the booster circuit for boosting the word line in the test mode, so that the marginal operation is intentionally performed in the test mode. Writing can be performed, and a marginal memory cell can be detected by, for example, determining whether the writing has been performed correctly.

According to the semiconductor memory device of the second aspect of the present invention, the means for shortening the data transfer time by the data line can intentionally perform the marginal write in the test mode. A marginal memory cell can be detected by determining whether or not writing has been correctly performed.

According to the semiconductor memory device of the third aspect of the present invention, the means for shortening the boosting operation of the booster circuit for boosting the word line can intentionally perform the marginal write in the test mode. For example, it is possible to detect a marginal memory cell by determining whether or not the writing has been correctly performed.

[0016]

【Example】

Example 1. 1 is a circuit diagram showing a first embodiment of a semiconductor memory device according to the present invention. In the figure, 7 to 10 are shown in FIG.
It is the same as that explained in. Reference numeral 11 denotes an AND circuit whose one input terminal is connected to the input terminal 7 of the booster circuit and whose output terminal is connected to the delay circuit 9. The other input terminal of this AND circuit 11 is connected to the other terminal in the test mode. The input terminal 12 for the test mode signal TE that is at a low level is connected.

Next, the operation of the first embodiment will be described with reference to FIG. In the test mode in which a marginal memory cell is detected, the test mode signal TE is at low level, and the output of the AND circuit 11 to which this test mode signal TE is input is also at low level. Therefore, the delay circuit 9 is in a state where its operation is stopped. Now, in t = t0, RAS bar signal goes low, the word line activation signal X, XL rises to the voltage V _CC, when the word line WL1 to t = t1 rises to V _CC,
Although the data of the memory cell is transmitted to the bit lines BL1 and BL0, since the operation of the delay circuit 9, that is, the boosting operation of the booster circuit is stopped, the level of the word line remains at V _CC and becomes V _CC + α. Don't Therefore, in the marginal memory cell, the bit line data is less likely to be transmitted to the memory cell at the time of writing, while the data of the memory cell is less likely to be transmitted to the bit lines BL1 and BL0 at the time of reading the data. As shown in, even if the sense amplifier is activated at t = t2, it becomes difficult to read data.

Therefore, according to the first embodiment, it is possible to intentionally perform marginal writing and reading by stopping the boosting operation of the boosting circuit in the test mode. For example, the write data and the read data are written. It is possible to check whether or not the writing and reading have been correctly performed by checking whether or not the two match, and thus it is possible to detect a marginal memory cell.

Example 2. FIG. 3 is a circuit diagram showing a second embodiment of the present invention. In the figure, 15 is a write buffer, 1
Reference numeral 6 denotes a data line I / O line, a transistor switch provided between the I / O bar line and the write buffer 15, and 17
Is a bit line BL0, BL0 bar and a data line I / O line, I
/ O bar line, and a transistor switch which is opened / closed by a selection signal of the bit line selection line Y0, 18 is a bit line BL1, BL1 bar and a data line I / O line, I / O
A transistor switch provided between the O-bar line and opened / closed by the selection signal of the bit line selection line Y1, 19 is connected to the gate of the transistor switch 16, and a write control that transmits a write control pulse as the opening / closing signal of the transistor switch 16. The pulse line, 20 has its output side connected to the gate of the transistor switch 16, and a short pulse generation circuit to which the write signal W0 and the test mode signal TE are input. 21 has its output side the transistor switch 16
Is a long pulse generation circuit that is connected to the gate of and receives the write signal W0 and the test mode signal TE.

Next, the operation of the second embodiment will be described.
The short pulse generation circuit 20 generates a short pulse in the test mode by the write signal W0 and the test mode signal TE. On the other hand, the large pulse generation circuit 21 generates a long pulse in the normal mode other than the test mode by the write signal W0 and the test mode signal TE. In the timing chart showing the write operation shown in FIG. 4, when the RAS bar signal becomes low level at t = t0, the word line W is set at t = t1.
L1 becomes the boosted voltage V _CC + α, and the data of the memory cell is read to the bit line. After that, the data is amplified by the sense amplifier, but when the write signal W0 is activated at t = t2 and the write control pulse signal W becomes high level at t = t3, the data of the bit line is written in the write buffer 15.
Is forcibly replaced by write data. Then, when the write control pulse signal W becomes low level thereafter, the stored data in the memory cell is amplified again by only the sense amplifier. Therefore, in the test mode, the short pulse generation circuit 20 is operated to close the switching transistor 16 for a short interval with a pulse shorter than the pulse (indicated by a broken line) in the normal state as shown by a solid line in FIG. By shortening the data transfer time by the lines I / O and I / O bar, it is possible to intentionally perform marginal writing. For example, by checking whether the written data and the read data match. , It is possible to check whether or not the writing has been correctly performed, and thereby a marginal memory cell can be detected.

Example 3. FIG. 5 is a circuit diagram showing Embodiment 3 of the present invention. In the figure, 7 to 10 are the same as those shown in FIG. 25 is a short pulse generation circuit to which the RAS bar signal and the test mode signal TE are input at its input side and whose output side is connected to the input terminal 7 of the booster circuit, and 26 is the RAS bar signal and test mode signal TE at its input side.
Is input and the output side is a long pulse generation circuit connected to the input terminal 7 of the booster circuit.

Next, the operation of the third embodiment will be described.
The short pulse generation circuit 25 generates a short pulse in the test mode according to the RAS bar signal and the test mode signal TE. On the other hand, the long pulse generation circuit 26 generates a short pulse in the normal mode other than the test mode by the RAS bar signal and the test mode signal TE. That is, in the third embodiment, in the test mode, the short pulse generation circuit 25 is operated to generate a normal pulse (generated from the long pulse generation circuit 26).
The booster circuit 9 is operated with a shorter pulse over a short interval. In the first embodiment, the boosting operation of the boosting circuit is stopped, whereas the output operation itself of the boosting circuit is shortened to intentionally perform marginal writing in the test mode. After that, the marginal memory cell can be detected in the same manner as in the first embodiment.

Example 4. 6 is a diagram showing a circuit configuration different from that of FIG. 4 in order to shorten the output operation itself of the booster circuit as in the third embodiment. In the figure, 7 to 10 are the same as those shown in FIG. 7, and 15 to 18 are the same as those shown in FIG. 28 is R at its three input terminals
Signal X synchronized with AS bar signal, test mode signal T
E, a NAND circuit of three-terminal input to which the write control pulse signal W is input, and the output terminal of this NAND circuit 28 is connected to the input terminal 7 of the booster circuit.

In such a circuit configuration, by temporarily setting the test mode signal TE to the low level in the test mode, the same operation as that of the third embodiment can be performed, and the same operation as that of the third embodiment is performed. It is possible to obtain various effects.

[0025]

As described above in detail, in the semiconductor memory device according to claim 1 of the present invention, among the plurality of memory cells,
In the test mode in which a memory cell having no margin in reliability of data write or read operation is detected, stop means for stopping the boosting operation of the booster circuit for boosting the word line is provided, so that a marginal memory cell can be detected. Therefore, for example, these marginal memory cells can be replaced with redundant memory cells, and a highly reliable semiconductor memory device can be obtained.

According to a second aspect of the present invention, the semiconductor memory device uses the data line in the test mode for detecting a memory cell having no margin in reliability of data write or read operation among the plurality of memory cells. Since the means for shortening the data transfer time is provided, it is possible to detect marginal memory cells, and thus, for example, it is possible to replace these marginal memory cells with redundant memory cells, which is highly reliable. The semiconductor memory device can be obtained.

Further, according to a third aspect of the present invention, in the semiconductor memory device, the word line is set in the test mode in which a memory cell having no margin in reliability of data write or read operation is detected among the plurality of memory cells. Since the means for shortening the operation time of the booster circuit for boosting is provided, it is possible to detect marginal memory cells. Therefore, for example, it becomes possible to replace these marginal memory cells with redundant memory cells, which is reliable. The effect is that a highly reliable semiconductor memory device can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a timing diagram illustrating the operation of the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a timing diagram illustrating the operation of the second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 7 is a diagram showing a conventional semiconductor memory device.

FIG. 8 is a diagram showing a conventional booster circuit.

FIG. 9 is a timing diagram illustrating an operation of the conventional semiconductor memory device.

[Explanation of reference numerals] 9 delay circuit 10 capacitor 11 AND circuit 16 switching transistor 19 write control pulse line 20 short pulse generation circuit 21 long pulse generation circuit 25 short pulse generation circuit 26 long pulse generation circuit 28 NAND circuit

Claims (3)

[Claims] 1. A semiconductor memory device comprising a plurality of memory cells, comprising a booster circuit for boosting a word line at the time of writing or reading data to or from these memory cells. A semiconductor memory device comprising: a stop unit for stopping the boosting operation of the booster circuit in a test mode in which a memory cell having no margin in read operation reliability is detected. 2. A semiconductor memory device comprising a plurality of memory cells, wherein the semiconductor memory device comprises a switch for transferring data to a data line when writing data to these memory cells. A semiconductor memory device comprising means for shortening a data transfer time by the switch in a test mode for detecting a memory cell having no margin in read operation reliability. 3. A semiconductor memory device comprising a plurality of memory cells, comprising a booster circuit for boosting a word line at the time of writing or reading data to or from these memory cells. A semiconductor memory device comprising means for shortening an operation time of the booster circuit in a test mode for detecting a memory cell having no margin in read operation reliability.