JPH0193815U - - Google Patents
Info
- Publication number
- JPH0193815U JPH0193815U JP18836687U JP18836687U JPH0193815U JP H0193815 U JPH0193815 U JP H0193815U JP 18836687 U JP18836687 U JP 18836687U JP 18836687 U JP18836687 U JP 18836687U JP H0193815 U JPH0193815 U JP H0193815U
- Authority
- JP
- Japan
- Prior art keywords
- distortion
- amplifier
- section
- detection signal
- input level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 3
- 238000006243 chemical reaction Methods 0.000 claims 2
- 230000007423 decrease Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
第１図は本考案の実施例の回路図、第２図は本
考案の減衰特性図、第３図は本考案の歪改善特性
図である。
FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is an attenuation characteristic diagram of the present invention, and FIG. 3 is a distortion improvement characteristic diagram of the present invention.
Claims (1)
歪に対応したパルス幅を有する検出信号を出力す
る歪検出部２と、該検出信号をアナログ波形に変
換する充放電型の波形変換部３と、該波形変換部
の出力電圧が一定値以下に低下すると動作し、該
増幅器の入力レベルを歪の度合に応じて減衰させ
る減衰制御部４とを備えてなることを特徴とする
歪改善回路。 Detect distortion from the difference in input and output waveforms of amplifier 1,
A distortion detection section 2 that outputs a detection signal having a pulse width corresponding to the distortion, a charge/discharge type waveform conversion section 3 that converts the detection signal into an analog waveform, and an output voltage of the waveform conversion section that is lower than a certain value. 1. A distortion improvement circuit comprising: an attenuation control section 4 which operates when the input level of the amplifier decreases and attenuates the input level of the amplifier according to the degree of distortion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18836687U JPH0193815U (en) | 1987-12-11 | 1987-12-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18836687U JPH0193815U (en) | 1987-12-11 | 1987-12-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0193815U true JPH0193815U (en) | 1989-06-20 |
Family
ID=31479463
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18836687U Pending JPH0193815U (en) | 1987-12-11 | 1987-12-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0193815U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6110304A (en) * | 1984-06-26 | 1986-01-17 | Fujitsu Ten Ltd | Distortion preventing circuit |
-
1987
- 1987-12-11 JP JP18836687U patent/JPH0193815U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6110304A (en) * | 1984-06-26 | 1986-01-17 | Fujitsu Ten Ltd | Distortion preventing circuit |
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