JPS6110304A - Distortion preventing circuit - Google Patents

Distortion preventing circuit

Info

Publication number
JPS6110304A
JPS6110304A JP59131743A JP13174384A JPS6110304A JP S6110304 A JPS6110304 A JP S6110304A JP 59131743 A JP59131743 A JP 59131743A JP 13174384 A JP13174384 A JP 13174384A JP S6110304 A JPS6110304 A JP S6110304A
Authority
JP
Japan
Prior art keywords
distortion
amplifier
input
output
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59131743A
Other languages
Japanese (ja)
Other versions
JPH0519843B2 (en
Inventor
Keikichi Okada
岡田 景吉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Ten Ltd
Original Assignee
Denso Ten Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Ten Ltd filed Critical Denso Ten Ltd
Priority to JP59131743A priority Critical patent/JPS6110304A/en
Publication of JPS6110304A publication Critical patent/JPS6110304A/en
Publication of JPH0519843B2 publication Critical patent/JPH0519843B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/34Negative-feedback-circuit arrangements with or without positive feedback

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To prevent distortion of an output of an amplifier without so much reduction in the decrease in the feeling of maximum sound volume even at an excess of input by suppressing a low frequency component among amplifier inputs in response to an output of distortion detection of an amplifier. CONSTITUTION:An input signal IN is fed to an amplifier 12 via a tone control circuit 20 controlling the frequency characteristic. An input/output signal of the amplifier 12 is fed to input terminals 2, 1 of the distortion detector 21 and outputted from an output terminal 3 as a distortion detection signal. The distortion detection signal is used as a low sound frequency control signal of the tone control circuit 20 to suppress the low frequency component of the input signal IN. The more or less of deterioration in sound quality is caused, but the amplitude decrease of the frequency component sensing to ears is prevented and the distortion is prevented without reducing the feeling of sound volume.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、オーディオ用パワーアンプ等における過大入
力時の歪防止回路に関し、特に歪防止措置を講じても最
大音量低下感がさほど生じないようにするものである。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a distortion prevention circuit at the time of excessive input in audio power amplifiers, etc. The present invention relates to a distortion prevention circuit in the case of excessive input in audio power amplifiers, etc. It is something to do.

〔従来の技術〕[Conventional technology]

第6図に示すように、スピーカ11をパワーアンプ12
で駆動するオーディオシステムでは、パワーアンプ12
の過大入力時でも出力OUTが歪まないように歪低減回
路13を設けている例もある。この例で示す歪低減回路
13は、アンプ12の出力OUTのレベルを検出するレ
ベル検出器14と、その検出出力を制御入力として、ア
ンプ12に供給す名オーディオ信号λカINを適度に減
衰させる電子アッテネータ15とからなるAGC回路で
ある。従って、外部からの入力INが過大でもアンプ1
2に入力するまでに減衰させておくことができるので、
出力OUTに歪が生じないで済む。
As shown in FIG. 6, the speaker 11 is connected to the power amplifier 12.
In an audio system driven by a power amplifier 12
In some cases, a distortion reduction circuit 13 is provided so that the output OUT is not distorted even when an excessive input is applied. The distortion reduction circuit 13 shown in this example includes a level detector 14 that detects the level of the output OUT of the amplifier 12, and uses the detection output as a control input to appropriately attenuate the audio signal λKIN supplied to the amplifier 12. This is an AGC circuit consisting of an electronic attenuator 15. Therefore, even if the external input IN is excessive, the amplifier 1
Since it can be attenuated before inputting to 2,
No distortion occurs in the output OUT.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところが、このようなAGO機能はパワーアンプ12の
最大出力が小さい場合には音量感の低下を伴ない、聴感
的に迫力がなくなる欠点がある。
However, such an AGO function has the disadvantage that when the maximum output of the power amplifier 12 is small, the sense of volume is reduced and the sound is not audibly impressive.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、歪防止のための利得低減動作を一様に行うの
ではなく、エネルギ分布の大きいわりに音量感への貢献
度が低い部分に対して選択的に行うことで上記の欠点を
改善しようとするものである。このため本発明は、増幅
器の歪を検出するための歪検出器または歪の発生を予知
するための動作レベル検出器と、該検出器の出力を受け
て前記増幅器入力のうち低音部を抑圧する周波数特性制
御回路とを備えてなることを特徴とするものである。
The present invention aims to improve the above-mentioned drawbacks by not performing the gain reduction operation uniformly to prevent distortion, but selectively performing it on parts that have a large energy distribution but have a low contribution to the sense of loudness. That is. For this reason, the present invention provides a distortion detector for detecting distortion of an amplifier or an operation level detector for predicting the occurrence of distortion, and a method for suppressing the bass part of the amplifier input based on the output of the detector. The present invention is characterized in that it includes a frequency characteristic control circuit.

〔作用〕[Effect]

音声信号のスペクトラムは通常、低音部に大振幅成分が
分布する。また振幅一定な信号に対する聴感上の音量感
は低音部では低下する。そこで歪防止のための利得低減
動作を低音部に対して選択的に行うと、多少の音質劣化
は伴なうが、耳に感じやすい他の周波数成分の振幅低下
を防止でき、音量感を低下させることなく歪防止をする
ことができる。周波数特性制御回路は低音ブースト機能
を有するトーンコントロール回路やラウドネスコントロ
ール回路で良く、これらが装備されているシステムでは
兼用して実施することができる。
The spectrum of an audio signal usually has large amplitude components distributed in the bass region. Furthermore, the auditory sense of volume for a signal with a constant amplitude decreases in the bass range. Therefore, if a gain reduction operation is performed selectively on the bass range to prevent distortion, it will cause some deterioration in sound quality, but it will prevent the amplitude of other frequency components that are more perceptible to the ear from decreasing, reducing the perceived volume. Distortion can be prevented without causing damage. The frequency characteristic control circuit may be a tone control circuit or a loudness control circuit having a bass boost function, and in a system equipped with these, they can be used together.

〔実施例〕〔Example〕

以下、図面を参照しながら本発明の詳細な説明する。 Hereinafter, the present invention will be described in detail with reference to the drawings.

第1図は本発明の一実施例を示すブロック図で、20は
電子トーンコントロール回路、21は歪検出器である。
FIG. 1 is a block diagram showing an embodiment of the present invention, in which 20 is an electronic tone control circuit and 21 is a distortion detector.

トーンコントロール回路20は低音用と高音用に分かれ
、本例ではこのうち低音用を歪低減動作に用いる。歪検
出器21は2つの入力端子1.2を備え、これらにアン
プ12の出力と入力を取り込んで波形比較を行い、その
差から歪の発生を検知する。3は制御出力端子である。
The tone control circuit 20 is divided into a low tone circuit and a high tone circuit, and in this example, the low tone circuit is used for distortion reduction operation. The distortion detector 21 has two input terminals 1.2, which input the output and input of the amplifier 12, compare waveforms, and detect the occurrence of distortion from the difference. 3 is a control output terminal.

第2図は歪検出器21の詳細図で、CMPは電圧比較器
である。この比較器CMPの入力端子1への電圧(アン
プ12の出力0UT)は可変抵抗VRでアンプ12の利
得分の1に分圧され、歪の生じていない状態で入力端子
2の電圧(アンプI2の入力)と等しくなるように設定
されている。
FIG. 2 is a detailed diagram of the distortion detector 21, where CMP is a voltage comparator. The voltage to input terminal 1 of this comparator CMP (output 0UT of amplifier 12) is divided by the gain of amplifier 12 by variable resistor VR, and the voltage at input terminal 2 (amplifier I2 input).

このようにすると、アンプ12(同相増幅器とする)の
入力が過大になって歪が生じた場合、端子1からの入力
はもはや増加しないのに対し、端子2からの入力が増大
するので、比較器CMPは出力を生ずる。コンデンサC
1,C2とダイオードDI、D2は倍圧検波回路を構成
し、その出力が端子3からの制御信号となる。この制御
信号を電子トーンコントロール回路20の低音部へ入力
してその電子ボリウム回路(WJ示せず)を制御するこ
とにより、入力INの低音部だけをしぼった歪防止がで
きる。
In this way, if the input to amplifier 12 (assumed to be a common-mode amplifier) becomes excessive and distortion occurs, the input from terminal 1 will no longer increase, but the input from terminal 2 will increase. The device CMP produces an output. Capacitor C
1 and C2 and diodes DI and D2 constitute a voltage doubler detection circuit, the output of which becomes a control signal from terminal 3. By inputting this control signal to the bass section of the electronic tone control circuit 20 and controlling its electronic volume circuit (WJ not shown), distortion can be prevented by restricting only the bass section of the input IN.

第3図は歪検出器21に代えて使用可能な他の回路例と
して、歪発生を予想するレベル検出器22を示したもの
である。この場合、端子2は空き端子で、端子1にアン
プ12の出力OUTを入力する。端子1から入力した増
幅出力OUTは可変抵抗VRで遠度に分圧され、バンフ
プアンブBUFを通して倍圧検波回路(C+、Ct、D
I、D2)に供給される。この場合は倍圧検波回路から
は常に出力が生じているが、その電圧がツェナーダイオ
ードZDのツェナー電圧を越えると初めて抵抗Rに電流
が流れ、端子3に制御電圧が生じる。従って、上記のツ
ェナー電圧を、アンプ12の歪が生じ始める出力レベル
に応じて設定しておけば、歪検出器21と同様の歪検出
ができる。
FIG. 3 shows a level detector 22 that predicts the occurrence of distortion as another example of a circuit that can be used in place of the distortion detector 21. In this case, terminal 2 is an empty terminal, and the output OUT of amplifier 12 is input to terminal 1. The amplified output OUT input from terminal 1 is voltage-divided by a variable resistor VR, and then passed through a bump amplifier BUF to a voltage doubler detection circuit (C+, Ct, D
I, D2). In this case, an output is always generated from the voltage doubler detection circuit, but only when the voltage exceeds the Zener voltage of the Zener diode ZD, current flows through the resistor R, and a control voltage is generated at the terminal 3. Therefore, if the Zener voltage described above is set according to the output level at which distortion begins to occur in the amplifier 12, distortion detection similar to that of the distortion detector 21 can be performed.

第4図は本発明の他の実施例である。本例は歪出部ハロ
ーバスフィルタ(LPF)23(!ニレベル検出器22
Lとで構成し、高音系の歪検出部はバイパスフィルタ(
)(PF)24とレベル検出器22Hとで構成しである
。低音系のレベル検出器22Lの出力は第1図と同様に
トーンコントロール回路20の低音部制御に使用される
。これに対し高音系のレベル検出器22Hの出力は、ト
ーンコントロール回路20とパワーアンプ12の間に接
続された電子アッテネータ25の減衰量制御に用いられ
る。この場合はトーンコントロール回路20による低音
部の抑圧と、電子アッテネータ25による全域の抑圧と
が混合して行われるので、両者が同時に作用するときは
第6図の回路と第1図の回路の中間的な特性が得られる
。また入力INの低音部が低く、中、高音部が過大入力
となる場合、低音′系の歪検出が作動しなくとも電子ア
ッテネータ25による全域の抑圧は行われるので、最低
限の動作(第6図と同様)は保証される。尚、レヘ/L
’&出器22 Lの出力でトーンコントロール回路20
の高音部も同時に制御すれば(中音部だけを抑圧しない
)、バランスのとれた歪防止が行われる。
FIG. 4 shows another embodiment of the invention. In this example, the distortion output halo bass filter (LPF) 23 (!Ni-level detector 22
The treble distortion detection section uses a bypass filter (
) (PF) 24 and a level detector 22H. The output of the bass level detector 22L is used to control the bass section of the tone control circuit 20 as in FIG. On the other hand, the output of the treble level detector 22H is used to control the amount of attenuation of the electronic attenuator 25 connected between the tone control circuit 20 and the power amplifier 12. In this case, the suppression of the bass region by the tone control circuit 20 and the suppression of the entire range by the electronic attenuator 25 are performed in a mixed manner, so when both act simultaneously, the circuit in FIG. 6 and the circuit in FIG. characteristics can be obtained. Furthermore, if the bass part of the input IN is low and the middle and treble parts are excessively input, the electronic attenuator 25 will suppress the entire range even if the bass distortion detection does not operate, so the minimum operation (6th (as shown in the figure) is guaranteed. In addition, Lehe/L
'& Output device 22 Tone control circuit 20 with output of L
If you control the treble range at the same time (without suppressing only the middle range), you can achieve balanced distortion prevention.

第5図は本発明の異なる実施例である。第1図または第
4図の例はいずれも電子トーンコントロール回路20を
歪防止専用に用いたが、第5図の例ではこれを手動制御
用と兼用する。つまり、TCL、TC,はトーンコント
ロール用の手動制御入力で、TCLは低音制御信号、T
C,は高音制御信号である。26は加算器で、歪検出器
21の制御出力と外部からの低音制御信号TCLを加算
してトーンコントロール回路20の低音制御入力とする
。高音制御人力TCHは直接トーンコントロール回路2
0の高音部に供給され、その電子ポリウム部(図示せず
)を制御する。
FIG. 5 shows a different embodiment of the invention. In both the examples of FIG. 1 and FIG. 4, the electronic tone control circuit 20 is used exclusively for distortion prevention, but in the example of FIG. 5, it is also used for manual control. That is, TCL, TC, are the manual control inputs for tone control, and TCL is the bass control signal, T
C, is a treble control signal. 26 is an adder that adds the control output of the distortion detector 21 and the external bass control signal TCL to provide a bass control input to the tone control circuit 20. Treble control human power TCH is direct tone control circuit 2
0 treble section to control its electronic porium section (not shown).

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、増幅器入力のうち音
量感の少ない低音部を低下させて歪防止を行なうように
したので、過大入力時でもさほど最大音量感の低下を伴
なわずに増幅器出力の歪防止を行うことができる。
As described above, according to the present invention, since distortion is prevented by lowering the bass part of the amplifier input where the sense of volume is low, even when an excessive input is applied, the amplifier can be operated without significantly reducing the sense of maximum volume. Output distortion can be prevented.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すブロック図、躬2図は
歪検出器の一例を示す回路図、第3図はレベル検出回路
の具体例を示す回路図、第4図および第5図は本発明の
他の実施例を示すブロック図、第6図は従来の歪低減回
路の一例を示すブロック図である。 図中、12は増幅器、20は電子トーンコントロール回
路、21は歪検出器、22はレベル検出器、23はロー
パスフィルタ、24はバイパスフィルタ、25は電子ア
ッテネータ、26は加算器である。 出 願 人  富士通テン株式会社 代理人弁理士  青 柳    稔 第1図 第2図     第3図 第41!1 第5図 第6図
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a distortion detector, FIG. 3 is a circuit diagram showing a specific example of a level detection circuit, and FIGS. This figure is a block diagram showing another embodiment of the present invention, and FIG. 6 is a block diagram showing an example of a conventional distortion reduction circuit. In the figure, 12 is an amplifier, 20 is an electronic tone control circuit, 21 is a distortion detector, 22 is a level detector, 23 is a low-pass filter, 24 is a bypass filter, 25 is an electronic attenuator, and 26 is an adder. Applicant Fujitsu Ten Ltd. Representative Patent Attorney Minoru Aoyagi Figure 1 Figure 2 Figure 3 Figure 41!1 Figure 5 Figure 6

Claims (2)

【特許請求の範囲】[Claims] (1)増幅器の歪を検出するための歪検出器または歪の
発生を予知するための動作レベル検出器と、該検出器の
出力を受けて前記増幅器入力のうち低音部を抑圧する周
波数特性制御回路とを備えてなることを特徴とする歪防
止回路。
(1) A distortion detector for detecting distortion of the amplifier or an operation level detector for predicting the occurrence of distortion, and frequency characteristic control for suppressing the bass part of the amplifier input based on the output of the detector. A distortion prevention circuit comprising a circuit.
(2)周波数特性制御回路が、音質調整用の電子トーン
コントロール回路を共用したものであることを特徴とす
る、特許請求の範囲第1項記載の歪防止回路。
(2) The distortion prevention circuit according to claim 1, wherein the frequency characteristic control circuit shares an electronic tone control circuit for adjusting sound quality.
JP59131743A 1984-06-26 1984-06-26 Distortion preventing circuit Granted JPS6110304A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59131743A JPS6110304A (en) 1984-06-26 1984-06-26 Distortion preventing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59131743A JPS6110304A (en) 1984-06-26 1984-06-26 Distortion preventing circuit

Publications (2)

Publication Number Publication Date
JPS6110304A true JPS6110304A (en) 1986-01-17
JPH0519843B2 JPH0519843B2 (en) 1993-03-17

Family

ID=15065148

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59131743A Granted JPS6110304A (en) 1984-06-26 1984-06-26 Distortion preventing circuit

Country Status (1)

Country Link
JP (1) JPS6110304A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0193815U (en) * 1987-12-11 1989-06-20

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5327105A (en) * 1976-08-25 1978-03-14 Applied Power Ind Inc Fluiq operated hydraulic pumps

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5327105A (en) * 1976-08-25 1978-03-14 Applied Power Ind Inc Fluiq operated hydraulic pumps

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0193815U (en) * 1987-12-11 1989-06-20

Also Published As

Publication number Publication date
JPH0519843B2 (en) 1993-03-17

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