JPH0193800A - Solid reproducer - Google Patents

Abstract

PURPOSE: To simplify the reading control of voice data and to attain sound reproducing for a long time by arranging various control data for driving the solid state reproducing device between voice data. CONSTITUTION: Voice data and various control data are stored in a ROM 20 built in a language exercising device 1 and contents of which address is specified from a control part 21 are read out from the ROM 20 and sent to a voice synthesis circuit 22 and the control part 21. The circuit 22 synthesizes a voice based upon the voice data and sends the synthetic voice to an announcing part 23. The control part 21 executes the address specification operation of the ROM 20, the stop of reading operation and the change of addresses based uon various control data. In addition, the control part 21 controls various operation based upon a signal inputted from a switch input part 24.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a solid-state playback device that is provided with a nonvolatile memory that stores audio data, reads out the audio data from this memory, converts it into an audio signal, and produces a sound. Regarding equipment.

[Prior art and its problems]

2. Description of the Related Art Conventionally, a device is known in which audio data is stored in a non-volatile memory such as a ROM, the audio data is read out from the ROM, the audio is synthesized, and a sound is generated.

For example, some clocks and the like notify the current time and alarm time by sound or voice using audio data from the ROM, and some also make voice announcements for elevators and the like.

However, in such announcements for clocks and elevators, the content that is pronounced is not very large.For example, ROMK voice data is stored and when a switch is operated, the ROM is read at a predetermined period. At the signal j@
The system is simple: the next access reads the audio data sequentially, and after the reading is complete, that is, after all the audio or the necessary audio has been generated, it waits for the next switch operation. The drawback was that it could only be played repeatedly.

In addition, in such a system, by storing a large amount of audio data, it is possible to obtain playback audio over a long period of time, and for example, it is possible to obtain something that can replace a recording tape. However, not only does the capacity of the ROM have to be extremely large, but also the reading control becomes extremely complicated.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to greatly simplify the start-up control of audio data, and to make it possible to extremely simplify the start-up control of audio data, and to save the data over an extremely long period of time compared to audio data that is stored in non-volatile memory. The object of the present invention is to obtain a solid-state regeneration device that can obtain regeneration time.

[Summary of the invention]

In order to achieve this purpose, in the present invention, various control data for controlling the operation of the device itself is arranged between audio data stored in a non-volatile memory and read out sequentially, and this control data is read out. The gist is that the system is made to perform a predetermined action when

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an external view of a solid state playback device according to the present invention, and this solid state playback device is used as a language practice device 1. However, 2 is a case made of synthetic resin, and this case 2 is formed into a card size, and has a length of 5 cm and a width of 8 cm.
CI+! , the thickness is 1α.

On one side of the case 2 is a power switch 3 that turns the power on and off, and the sound that is generated! A rotary volume switch 4 for setting the volume (volume) is provided, and an earphone jack terminal (not shown) is provided on the other side of the case 2, and an earphone jack 5 is inserted into the earphone jack terminal (not shown). 6 can be heard. In addition, on the top surface of the case 2, there is a push button type start/stop switch 7 that controls the start and stop of sound generation, a skip switch 8 that specifies the generation position of the repeated playback sound, and a position specified by this skip switch. A skip reset switch 9 is provided to cancel the repeated occurrence operation. Also, 10
is a fast-forward/fast-reverse switch that fast-forwards or fast-reverses the playback sound, and whether to perform fast-forward or fast-reverse when this switch 10 is operated is selected using the two-contact slide switch ]1. It looks like this. Further, numeral 12 is a number selection switch consisting of a slide switch for allowing the user to select the number of times the generated sound is repeated, so that the user can repeatedly listen to the same area of sound up to four times. Details of the functions of these switches will be described later.

Figure 2 shows the language practice rate in which the English text of the English language audio data generated from the language practice tool [1] shown in Figure 1 is written, and is divided into several chapters and sections. , the Japanese translation is also included, and the prenatal training equipment f
By using it together with 1, language learning is performed.

This is a ROM (read-only memory) that stores information and various control data. Note that this ROM 20 is not only a normal ROM but also an EP ROM.

EtPROM, mask ROM, etc. can also be used, and in addition to being directly attached to a circuit board (not shown) placed inside the case 2, for example, the language practice device 1
It is incorporated into a removable IC card etc. in case 2 of No. 11, and when this IC card is installed in case 2,
It is also possible to electrically connect the ROM 20 and the electronic circuit in the case 2 through contacts.

However, the ROM 20 has a control section 21 consisting of a CPU.
The data in the addressed area is read out by a read command signal from the control section 21 and sent to the speech synthesis unit (speech synthesis circuit) 22 and the control section 21. . The voice synthesis unit 22 synthesizes the received voice data based on, for example, the ADPCM algorithm, converts it into a voice waveform, and sends the voice waveform to the alarm section 23. This report section 23
Although not shown in the drawings, the device includes, for example, a bypass filter, an amplifier, a volumetric volume, an earphone terminal, an earphone jack, and an earphone, etc., and generates sound.

When the control unit 21 that specifies the address of the ROM 20 and outputs audio data receives various control data from the ROM 20, it stops the addressing operation and read operation of the ROM 20, or changes the address. . When a start code, which will be described later, is received from the ROM 20, it outputs an alarm command signal to the voice synthesis unit 22 to generate a start voice consisting of a single tone. Further, the control section 21 receives signals from a switch input section 24 made up of various switches shown in FIG. 1 to control various operations.

FIG. 4 shows details of the ROM 20 shown in FIG. 3. Address data specifying an address from the control unit 21 is divided into a large number of lower bits and a plurality of upper bits, and each is sent to an address decoder 30, 31 and decoded. 32 is a data storage unit, and the circled part indicates 1-bit information, the part that is filled in black is data "1", and the part that is not is data "0".
It shows. For example, if the value of the lower bit of the address data is rOJ, the signal line O is output from the decoder 31, and all data on this signal line 0 is read out. However, at the output end of each output line (in the horizontal direction) there are switch circuit sections 34a, 34b...
34n is provided, and these switch circuits BB34
a, 34 b..., 0N101゛F is controlled by the value of the upper bits of the address data, and 4 of one switch circuit capital is 01'
lJ (open). Therefore, when the value of address data increases sequentially from "0", 33
The 8-bit data indicated by a is outputted 11 times through the switch circuit section 34a, and after the output of this 8-bit data from 33a, the 8-bit data indicated by 33b is outputted via the switch circuit m34b. The 8-bit parallel data is sequentially stored in the ROM up to the 8-bit data indicated by 33n.
This is output as the output of 20.

However, the 8-bit data consists of audio data and control data. In the case of audio data, 4 bits out of 8 bits represent one audio data, and the remaining 4 bits represent another audio data. Each of the 4 bits is one bit, or data indicating the rise or fall of the wave carving in the ADPCM system, and the remaining 3 bits are data indicating the amplitude, that is, the proof of the change.

Therefore, in the speech synthesis unit 22, the 8-bit parallel data is temporarily stored in a buffer, etc., and then
It is designed to read out and convert into audio waveforms in batches. For this purpose, the speech synthesis unit 22 is given a signal of 16 KHz, which is twice the access frequency of the ROM 20 of 8 KHz. Further, if all eight inputted pits are "0", the speech synthesis operation is not performed.

On the other hand, the control data is output after data in which all 8 bits are '0' are output several times, for example, three times in a row.

In this embodiment, various types of control data are provided, such as start data, Bose data, Repeat 1 data, and Repeat 2 data, and the code of each data is detected by the control unit 21. It looks like this.

FIG. 5 shows details of the control m21,
The circuit excluding the ROM 20, voice synthesis unit 22, sound control circuit 35, earphone terminal 36, and various switches shown in FIG. 1 (the same numbers as in FIG. 1) are included in the 1tlJ control circuit 21. .

40 is, for example, a 4 MHz crystal oscillation circuit, and the oscillation signal of this crystal oscillation circuit 40 is sent to a timing signal generation circuit 41, and the dynamic KHz signal of each circuit, 25
A 6 KHz signal is also output. The operation signal of the start/stop switch 7 is transmitted via the one-shot circuit 42.
The one-shot pulse from this one-shot circuit is sent to the trigger terminal T of a binary flip-flop 43 whose output is alternately inverted. The output signal from the output terminal Q of this binary flip-flop 43 is applied to AND circuits 44, 45, and 46. A signal from an output terminal Q of a flip-flop 47 and an 8 KHz signal from a timing signal generation circuit 41 are input to the AND circuit 44 , and the output signal is sent to the ROM 20 via an OR circuit 48 . The signal is sent as an address update signal to an address designation circuit 49, which designates an address and is made up of, for example, an address counter. The above address designation circuit 49
counts the pulse signal of, for example, 8 KHz from the OR circuit, sends the value as an address designation signal to the ROM 20, and sends the address value to the gate circuit 50, 51, 52.
When each gate circuit is open, it is further sent to latch circuits 53, 54, and 55, respectively. This latch circuit 53
．． 54 and 55 operate as storage circuits that temporarily store sent address data, respectively, and latch circuits 53 .
54 stored address data are sent to the gate circuit 5, respectively.
6.57 is preset in the addressing circuit 49 when it is opened. Further, the latch circuit 550 is applied together with the data of the addressing circuit 49 to a match detection circuit to a delay circuit 60, and the output of the delay circuit 60 is applied to the gate circuit 57 as a signal for opening the gate.

In addition, the AND circuit 45.46 described above has 256K H
The z signal and the operation signal of the fast forward/reverse switch 10 are inputted, respectively, and the output signal of the two-contact slide switch 11 is also inputted.

Therefore, the slide switch 11 is the contact 11a on the fast forward side.
When the switch 10 is operated while in contact with the switch 10, a signal of 256KH2 is outputted from the AND circuit 45 during the operation, sent to the address designation circuit 49 via the OR circuit 48, and counted, and the address designation can be fast-forwarded. , If the switch 10 is operated while the slide switch 11 is in contact with the contact 11b on the fast forward side as shown in FIG. Since it is given as a signal), it is possible to quickly rewind the address.

Further, the operation signal of the skip switch 8 is applied to a binary flip-flop 62 via a one-shot circuit 61. The output signal of the output terminal Q%Q of the binary flip-flop 62 is applied to AND circuits 63 and 64, respectively, to which the output of the one-shot circuit 61 is applied.

The output signal of the AND circuit 63 is applied to the OR circuit 59 and is also supplied as a gate development signal to the gate circuit 11852 for sending the address data of the address designating circuits 4 and 9 to the latch teaching circuit 55. Further, the output signal of the AND circuit 64 is given as a gate open signal to the gate circuit 51 which sends the address data of the address designating circuit 49 to the latch circuit 54. Incidentally, the contents of the latch circuits 54 and 55 are reset by an operation signal of the reset switch 49 applied via the one-shot circuit 65.

The 8KHz signal outputted from the AND circuit 44 by the operation of the start fist stop switch 7 described above is completely O.
It is given to the code detection circuit 70 as an operation command signal. This all-0 code detection circuit increments the contents of the addressing circuit 49 by an 8KHz signal, and each time new 8-bit data is output from the ROM 20, the value of all 8-bit data is rOJ. Whether or not
That is, it detects whether all bits are 0'' or not. When it is detected that all bits are @0'', a detection signal is sent to the counter 71. This counter 71 is composed of, for example, an e-adic counter or the like, and sends a carry signal to the delay circuit 72 when the detection signal is counted three times. This delay circuit performs a delay operation of, for example, 8 KHz, and
The gate circuit 73 is opened in synchronization with the output of the next 8-bit data from the sound synthesis unit 22.
-[, outputs a signal that prohibits speech synthesis operation based on the input 8-bit data. That is, the ROM 20 of this embodiment has an 8-bit value "0" before the control code.
3 data are stored in succession, and control data is stored after that, and the speech synthesis operation using this control data is prohibited.

The 8-bit control data sent via the gate circuit 73 is sent to the start code detection circuit 74, the Bose code detection circuit 75, the repeat 1 code detection circuit 76, and the repeat 2 code detection circuit 77. is detected. The detection signal from the start code detection circuit 74 is sent as an operation signal to the start sound signal generation circuit 78, and the start sound signal generation circuit 78 generates a single sound of a predetermined frequency to the alarm control circuit 35 for one second, for example. Outputs a signal to Further, the detection signal from the start code detection circuit 74 is supplied to the gate circuit 50 as a gate open signal via a delay circuit 79 and an OR circuit 80. As a result, the latch circuit 53 stores the address next to the address where the start code is stored.

The Bose code detected by the pause code detection circuit is R
This is a code that stops data output from the OM20 for a certain period of time. Bose code detection signal is flip-flop 8
10 is sent to the set terminal S, and this flip-flop 81
The output of the 0 set output terminal Q is sent to the set terminal SK of the flip-flop 47, and the Q output of this flip-flop 47 is set to 0, and is input to the AND circuit 82. A 16Hz signal is also input to this AND circuit 82,
The 16 Hz signal output from this AND circuit 82 is counted by a timer circuit 83. This timer circuit 83 is
After counting the 16 Hz signals, for example, 10 seconds later, a carry signal is output, and the flip-flops 47 and 81 are reset. Therefore, when the Bose code is detected, the 7 lip-flop 47 is set and the 8KH signal from the AND circuit 44 is set.
The output of the z signal is stopped, reading of data from the ROM 20 is stopped, and after 10 seconds, the recoupling flip 70 knob 47 is reset and an 8KHz signal is sent to the address designation circuit 49, and the data reading from the ROM 20 is stopped. Data reading is restarted.

The repeat 1 code is a code that repeatedly generates a sound the number of times selected by the number selection switch 12. Therefore, the contacts of the selection switch 12 are the contact 12a that does not select the number of repetitions, and the number of repetitions of 1, 2, 3, and 3, respectively.
Contacts 12b, 12c, 12d, and 12e corresponding to the four times are provided, and the output of contact 12a is sent to an AND circuit 85 via an inverter 84.
The outputs of c, 12d, and 12e are each output from an AND circuit 86.8.
7.88.89. However, repeat 1
The detection signal from code detection circuit 76 is sent to AND circuits 85 and 911C via delay circuit 90. The output of the AND circuit 85 is given as a gate open signal to the gate circuit 56 via the OR circuit 92, causing the address ([ of the latch circuit 53 to be preset to the addressing circuit 49, and also given to the quinary counter 93 for counting. The count value of the 5th round counter 93 is decoded by a decoder 94, and the decoded outputs 1, 2, 3, 4 are sent to AND circuits 86, .
Delivered on 87.88.89. AND circuit 86.87
．． The output signals of 88 and 89 are the OR circuit 95 and the delay circuit 96.
is applied to the set terminal S of the flip-flop 96 via [. Reset output terminal Q of this clip-flop 96
The output of is given to an AND circuit 85, and the output signal of the set output terminal Q is sent to an AND circuit 91.

The output signal of the AND circuit 91 is sent to the reset terminal R of the flip-flop 97 via the delay circuit 98, and
The signal is applied to the counter 93 as a reset signal, and via the OR circuit 80 to the gate circuit 50 as a gate open signal.

The repeat code detected by the repeat 2 code detection circuit 77 is a code that causes the same part of the sentence to be repeatedly pronounced as a language practice device, regardless of the user's selection trap.
Two codes can be detected: a code indicating the first address of repetition and a code indicating the last address. In the case of the code indicating the first address, a detection signal A0 is output, and the code indicates the last address. In the case of a code, a detection signal A is output.

Therefore, the detection signal A0 is output from the binary flip-flop 99.
It is applied to the trigger terminal T of the 7-lip flop 99a, and also to the AND circuit 99b to which the Q output terminal of the 7-lip-flop 99a is applied. The output of the AND circuit 99b is supplied to the OR circuit 80@Also, the output signal of the detection signal AX is supplied to the AND circuit 99c together with the output of the output terminal Q of the binary flip-flop 99a, and the output of the AND circuit 99c is supplied to the OR circuit 80. It is supplied to circuit 92.

Next, the audio data and control data (control code) stored in the ROM 20 will be explained with reference to FIGS. 2, 4, and 6 (11), which have already been explained.

As explained in FIG. 4, the ROM 20 outputs 8-bit data from the line 33a. However, the first three data N0 to N are data in which all bits are 0'', and the next N stores a start code. This N
, to N3, and these four data are followed by three data with all 8 bits being 0", indicated by Xl, and the following four data T consisting of a Bose code.
is memorized, and furthermore, the voice data of a predetermined Bungun,
For example, the rChapterl of the practice book shown in Figure 2,
Hearing Drills, Warm-U
Audio data A called PJ is stored. below,
Similarly, one English sentence audio data B (Mr, Ad
ams-), C (Children...)...
・Data T including a Bose code is inserted between D, and at the end of each chapter, data R consisting of three all-bit "0" data and a repeat 1 code is inserted.
0 is inserted.

Furthermore, R, , R, is a repeat 2 code, which consists of a code indicating the first address and a code indicating the last address for repeatedly sounding the audio data of G, and in these as well, all bits are "0". The configuration is such that three codes are stored and then each code is attached.

〔motion〕

The operation of the fetal training device configured as described above will be explained below along with switch operations.

First, by turning on the power switch 3, the output voltage from a battery (not shown) disposed inside the case 2 is supplied to the entire circuit shown in FIG. 5, and the crystal oscillation circuit 40. The timing signal generation circuit 41 and the like start operating, and the other circuits become operable.

When the start/stop switch 7 is operated, the binary flip 70 knob 43 is set, and the 8KHz frequency signal from the AND circuit 46 is sent to the address designation circuit 49 via the OR circuit 48, and this address designation is performed. The address data of the circuit 49 is the first data N of the ROM 20.

Output sequentially from Data N0 to N of ROM20,
is a code in which all bits are 60", so this code is detected by the all-0 code detection circuit 70, and the detection signal is counted by the counter 71. When the third data N, is detected, the counter 71 outputs a carry signal, which is delayed by the delay circuit 72 and outputs the fourth data N of the ROM 20.
The gate circuit 73 is opened in synchronization with the output timing.

Since the fourth data N3 in the ROM 20 is a start code, this is detected by the start code detection circuit 74. A detection signal output by this detection is sent to a start sound signal generation circuit 78 to generate a start sound. Further, the signal outputted via the delay circuit 79 is
When the 2005th data is specified, the gate circuit 50 is opened via the OR circuit 80, so the ROM 20
Address data specifying the fifth data is preset in latch circuit '#653. The data read next from the ROM 20 is data T as shown in FIG. 6(2). The fifth to seventh data of the data T in the ROM 20 are data in which all bits are "0", and the eighth data is a Bose code.

Therefore, the fifth to seventh data are detected by the all-0 code detection circuit 70, the gate circuit 73 is opened in synchronization with the output of the eighth data, and the Bose code is detected by the Bose code detection circuit 75. Ru.

The detection signal of this Bose code detection circuit 75 causes the flip-flop 181 to be set, and the set output from the output terminal Q of this flip-flop 81 causes the flip-flop 4 to be set.
7 is set. As a result, 8 from the AND circuit 44
KHz signal output is stopped, and updating of the address of the ROM 20 and data reading from the ROM 20 are stopped. After this, when a signal is output from the timer circuit 83 after 10 seconds have passed, the flip-flop 47 is reset, and the output of the 8KHz signal from the AND circuit 44 is restarted, and the ROM2
As shown in FIG. 6 (2), from 0, the data stored from the 9th onwards, that is, the audio data A, is output, and an audible audio signal is sent to the earphone terminal 36 via the audio synthesis unit 22 and the alarm sound control circuit 35. It can be heard through earphones 6 via earphone jack 5 shown in FIG. still,
It is also possible to generate sound by providing a speaker 100 in the case 2 as shown by the broken line.

However, after the audio data A is output, the data T including the Bose code (Xi in FIG. 6 (1)) is output, so the audio is output after a 10 second stop period as described above. Data B is output.

Thereafter, in the same way, every time one English voice is output, there is a stop period, and the next voice data is sequentially displayed.

After all the audio data of Chapter 1 is read out in this way, data I (. shown by XO in FIG. 6(1)) is output, and the repeat 1 code is detected by the repeat 1 code detection circuit 76. At this time, when the number selection switch 12 selects the terminal 12a, the output of the inverter 84 is 0, so the delay circuit 90
The detection number 4i outputted through the AND circuit 85 is not outputted from the AND circuit 85, and therefore no repetitive operation is performed. On the other hand, the circuit selection switch 12 repeats the number of times 1.2.
3.4, i.e., terminals 12b, 12c, 12d
, 12e, the audio data of the entire chapter is repeatedly generated the number of times selected.

For example, when the terminal 12b (1 repetition count) is selected, the output signal from the AND circuit 85 opens the gate circuit 56 via the OR circuit 92, so that the ROM 2005 stored in the latch circuit 53 Eye data 0
Since the address data is reset by 1 to the address designation circuit 49, the ROM 20 outputs data R, as shown in FIG. 6 (4) K, followed by data T at the address X in FIG. 6 (1). and after a 10 second pause period,
Sequential reading starts again from audio code A.

On the other hand, the output of the AND circuit 85 is counted by the counter 93, and a signal line of "1" is output from the decoder 94, and this signal is delayed by the delay circuit 96 via the AND1 path 86 and the OR circuit 95, and then sent to the clip-flop. Set 27,
Next, even if there is an output from the delay circuit 90, it is prevented from being output from the AND circuit 85. In such a state, when the data R, indicated by Xo, is output again from the ROki 20, the output of the delay circuit 90 is output from the AND circuit 91, resetting the counter 93, and at the same time, the gate circuit 5
0 is opened and the first address data of the audio data D specified by the address designating circuit 49 is preset in the latch circuit 53. Further, the signal from the AND circuit 91 resets the flip-flop 97 via the delay circuit 98.

In this manner, when one repetition is selected by the number of times selection switch, the sound is repeated only once. Then, at the end of the second chapter, the R0 data is similarly stored and read out, so the same operation is performed and the sound of the second chapter starting from the sound data D is repeatedly generated.

Further, when 2, 3, or 4 times is selected by the number selection switch 12, the output signal is obtained from the AND circuit 87, 88 or 89 only after each of the counters 93 has counted that number of times, and the output signal is obtained from the flip-flop. Since 97 is set, the sound is generated repeatedly that number of times.

Next, the repetition of the GO) audio data in FIG. 6, (1) will be explained. First, when data R8 is output, a code indicating the first address of repetition is detected by the repeat 2 code detection circuit 77, and signal A is detected.

is output. Since the binary flip-flop 99a is initially in a reset state, the AND circuit 99b is activated by the signal AO.
A signal is output from the address data, and the address data at that time is stored in the latch circuit 53, and the binary flip-flop 99a is set to a set state. Subsequently, after the G audio data is output, data R7 is output, and the repeat 2 code detection circuit 77 outputs the signal A. This signal A is output from the AND circuit 99c, opens the gate circuit 56, and presets the address data stored in the latch circuit 53 into the address designation circuit 49.

That is, the address is returned to the address of data R8. As a result, the repeat 2 code detection circuit 77 outputs the signal A again.
0 is output. This signal returns the binary flip-flop 99a from the set state to the reset state so that the same operation is performed the next time there is audio data to be repeated. After this, the audio data G is output again. Incidentally, if this repeated manufacturing is performed, the latch circuit 5
3 has changed, making it impossible to repeat the chapters selected by the user as described above. To avoid this, the launch circuit that stores the address of the addressing circuit 49 by the output of the AND circuit 99b is replaced by the latch circuit 53.
It is preferable that the address designating circuit 49 is provided separately from the latch circuit and that the contents of the separately provided latch circuit are preset in the address designation circuit 49 when there is an output from the AND circuit 99C.

Finally, the operations when the skip switch 8 and the skip reset switch 9 are operated will be described. The skip switch is a switch that is operated at the beginning and end of a section that the user wants to repeat.

When the user operates the skip switch 8 for the first time, an output signal is obtained from the AND circuit 64, and the address data at that time is preset in the latch circuit 54. Next, when the skip switch 8 is operated when the last voice of the repetition is generated, an output signal is obtained from the AND circuit 63, and the address data at that time is preset in the latch circuit 55, and further passed through the delay circuit 60 to the gate circuit. 57 is opened and the first address data stored in the latch circuit 54 is preset in the address designation circuit 49. Therefore, the audio data will be generated again from the point where the skip switch 8 was first operated.

When the generated sound reaches the point where the skip switch 8 is operated for the second time, a match is detected in the match circuit 58, so a match signal is output, and the address data of the latch circuit 54 is again used to designate the address and specify the circuit. It is preset to 49. Therefore, the audio data during the period in which the skip switch 8 was operated will be repeatedly generated.

To cancel the occurrence of such repetition, operate the skip reset switch 9. By operating this skip reset switch 9, the contents of the latch circuits 54 and 55 are reset, and the above-described repetitive operation is stopped.

In this way, according to the above embodiment, an extremely large amount of audio data can be stored in the ROM 20, and the reading of the audio data can be controlled extremely easily. Above ROM2
0 has a capacity of 16M (mega) bits, for example, and is read out sequentially in 8-bit units at a bit rate of 8KHz.Moreover, there is a pause period between audio data, and there are repeated occurrences, so A total playback time of over 1 hour can be obtained.

FIG. 7 shows the circuit configuration of another embodiment of the language training machine according to the present invention. In the figure, 20 is a ROM similar to that shown in FIG. 3, 22 is a speech synthesis unit (circuit, 73 is a sound reporting section, and 24 is a switch input section.

Reference numeral 101 denotes a control unit consisting of a CPU, which controls the entire circuit. A control ROM 102 permanently stores a microprogram, and a RAM 103 temporarily stores various information. However, the control unit 101 controls the operation of the entire circuit based on a microprogram stored in the control ROM 102, and the operation will be described later.

FIG. 8 shows a storage area map of the RAM 103.

AD is an address storage unit that stores address data of the ROM 20, Mo is a repetition address storage unit that stores address data of the repeated portion, Ml is a repetition number storage unit, and M is a storage unit for the first address of skip. , Ms is a second address storage section %FO is a timer flag, and C is a timer register.

FIG. 9 shows a flowchart of the circuit according to the control ROM 1020 microprogram, and this flow is executed every 8 KHz signal.

However, step S1 is a step for determining whether or not the key switch has been operated, and if there is a key switch operation, the process proceeds to step S2, otherwise the process proceeds to step S.
, proceed to . The key processing in step 2 performs various processing according to the operated switch. For example, if audio playback is started by the start/stop switch 7, it will proceed to the subsequent flow, but if it is stopped, then When the skip switch 8 is operated, the address data at that time is stored in the memory unit M by the first operation, and the address data at that time is stored by the second operation. Address data is stored in memory section M
, to be stored.

Furthermore, by operating the skip clear switch 9, the memory section M2 is cleared.
, clear the contents of Ml.

However, in step Ss, the timer flag F.

It is determined whether or not is "0". This timer flag F0
is a flag that becomes "1" while audio output is stopped,
If this flag Fo is "0", the process proceeds to step S, and the address data in the address storage SAD of the RAM 103 is incremented by 1. In the next step S, it is determined whether the address data of the address memory sAD that has been incremented by 1 matches the last address data of the repeated voice stored in the memory section M, and if they do not match, step S.

If the advance K matches, in step S6, the memory M! is stored in the address storage AD. , that is, the first address data of the repeated voice, and proceed to Stella 1S.

In step S, the ROM 20 is addressed using the address data stored in the address memory iAD, and data at the designated address is read out. This read data is stored in steps S, ,S, ,S,
. Accordingly, it is determined whether the data is start data, pause data, repeat data, or audio data instead of any of them. If it is output data or audio data, the above flow ends and the output audio data is sent to the speech synthesis unit 22 for processing, but if it is start data, the process proceeds to step Sll. This step S. At this time, a sound start process is performed and a start sound is generated, and at the same time, the address data in the address storage section AD is transferred to the storage section M. Next step S
In step 11, the timer flag F0 is set to 1, and in step Stl, the timer time is updated. That is,
A +1 operation is performed on timer register C. Step S
If the value is 0, it is determined whether the value of the timer register C has reached 10 seconds, and if the value has reached 10 seconds, the timer flag Fo is set to 0 in step 811.

That is, in the case of start data, the step SI described above is performed in order to be in a stopped state for 10 seconds after the start sound is generated.
Therefore, the timer flag Fo is set to "1", the process proceeds from step Ss to step 81m for 10 seconds, and a stop period of 10 seconds is provided. Also, when it is determined in step S9 that the data is Bose data, the process proceeds to step Sat, where a 10-second stop is similarly performed.

However, when repeat data is detected in step 810, the number selection switch 12 is set to 0 in step S16.
, that is, a position where the number of times is not selected, and if the number of times is selected, step 81
Proceed to Ding. In step sty, the number of times is stored m M
r is incremented by +1, and in the next step SO, it is determined whether the value in the number storage section M1 is greater than the number selected by the number selection switch 12, and if it is smaller, in step S1°, Stored in address memory HAD m M
By transferring the contents of o, the voice is repeatedly generated again. Furthermore, if the value in the memory section M1 is large, in steps S and o, a value incremented by 1 in the address memory section AD is preset in the memory section M0, and the next step S! I
Then, the memory unit M is preset to "0" and the flow is ended.

As described above, the present invention is implemented based on the microprogram stored in the control ROM 102, but the present invention can also be applied to things other than language practice devices, such as audio data such as novels and poems. As an e-book that memorizes and plays back, or the sounds of birds and other animals, the sound of waves,
It can also be applied as a device for storing and reproducing audio data such as the sounds of SL locomotives, and a device for storing and reproducing audio data such as music.

In addition, the Hose code stored in the ROM 20 is used to stop the generation of the Jin voice for a certain period of time, for example 10 seconds, but this stopping time can be made variable; for example, the RO
M20 includes stop time data in each Bose code, and the timer 83 (Fig. 5) or register C
When the time measured in FIG. 8 matches the time data included in the Bose code, audio playback may be restarted.

Control codes that can be omitted from being stored in the ROM 20 include, for example, storing a volume control code to make only the sound of a certain sentence louder or softer, or storing a speed control code to make the playback speed of only a certain sentence faster or slower. or, for example, speed up the second repetition.
The control code ml is not limited to the present embodiment.

It also has a memory that can store multiple address data,
By providing a so-called cueing function for 11th playback from each address data, and by inputting data indicating each page of the practice rate shown in Figure 2, or data indicating each chapter, that page or each chapter can be selected. It is also possible to start playback from.

Furthermore, a secret amount may be stored so that only the owner of the device can use it, and the device can only be used when this number is input.

Further, in order to easily perform each of the above-mentioned functions, a keyboard consisting of a large number of keys including numeric keys may be used.

Furthermore, as mentioned in the embodiment, it may be equipped with speakers instead of earphones, but it is also possible to have two speakers, for example, so that one outputs the human voice and the other outputs the surrounding sounds simultaneously. As described above, the present invention can be applied in various ways and is not limited to the embodiments.

〔Effect of the invention〕

As detailed above, the present invention includes a non-volatile memory for storing audio data and control data, and an addressing means for specifying an address of the non-volatile memory and sequentially reading out the audio data and control data from the non-volatile memory. ,
a sound generating means for generating sound based on the sound data read from the child elastic memory; and a sound generating means for generating sound based on the sound data read from the child elastic memory; Since the apparatus is equipped with a control means for controlling the apparatus, the reproduction operation can be easily controlled even when audio data is stored and reproduced in an extremely large-scale nonvolatile memory, and the apparatus itself can be miniaturized.

[Brief explanation of the drawing]

FIG. 1 is an external perspective view of a solid state regeneration device showing an embodiment of the present invention, FIG. 2 is a book used with the solid state regeneration device shown in FIG. 1, and FIG. 3 is a circuit block diagram of the present invention. FIG. 4 is a diagram showing details of the ROM shown in FIG. 3, FIG. 5 is a diagram showing the detailed circuit configuration necessary for the third stage, FIG. 8 is a circuit configuration diagram showing another embodiment of the present invention, FIG. 8 is a diagram showing the storage area of the RAM 102 shown in FIG. 7, and FIG. 9 is a flow chart showing the operation. DESCRIPTION OF SYMBOLS 1...Language practice device, 2...Case, 3...'switch, 4...Porium switch, 7...Start strap inch, 20...ROM, 22...
・Speech synthesis unit, 24...switch input section, 49
...Address designation circuit, 53.54.55...Latch circuit, 103...Control ROM, 102...RA
M.

Claims (1)

[Claims] a non-volatile memory for storing audio data and control data; addressing means for specifying an address of the non-volatile memory to sequentially read out the audio data and control data from the non-volatile memory; The present invention is characterized by comprising a voice generating means for generating voice based on the voice data read from the non-volatile memory, and a control means for controlling the addressing by the addressing means based on the control data read from the non-volatile memory. Solid state regeneration equipment.