JPS6232791B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electronic musical instrument that allows easy performance by inputting and storing pitch and duration separately. Various automatic performance devices, particularly for keyboard instruments, have been put to practical use, but these require large devices and have not been realized with simple configurations. However, in recent years, along with the advent of microcomputers, digital systems that enable automatic performance have been put into practical use. However, there are two main types of memorization methods used in this system, one of which is:
A device that is equipped with keys (keyboards) that specify the pitch and keys that specify the length of notes such as whole notes, half notes, quarter notes, eighth notes, etc., and that specifies and memorizes the pitch and length of each note. It is. The other method is to memorize the pitch and duration of the notes played on the keyboard as they are. However, in the former case, a person who can read music scores can directly input the musical information shown on the music scores, so even if it is your first time listening to a piece, you can listen to it on an automatic performance device, but the pitch and tone It is necessary to input both pitches by key input, which increases the number of input operations.Furthermore, in addition to the keyboard that can specify the pitch, it is necessary to provide a large number of keys that are necessary only for inputting the pitch. The latter method does not require a special key for inputting the note length, but it has the disadvantage that it cannot be used at all unless you are very good at playing musical instruments. By the way, even if you have never played a musical instrument or can't read music well, you can listen to music very well with your ears, so you can memorize only the pitch in advance, regardless of the length. After that, it is relatively easy to specify performance information such as note length while playing back the music. The present invention was developed in view of the above-mentioned circumstances, and it is possible to sequentially input and memorize only the pitches in advance, and to manipulate the pitches rhythmically by simple key operations while playing back the memorized pitches. An object of the present invention is to provide an electronic musical instrument that allows input to be stored. That is, the first invention of the present invention is such that pitch information is previously input and stored in the performance information storage means using a plurality of performance keys, and then read out using at least one timing key to generate the corresponding scale note. and furthermore, the electronic musical instrument is configured to measure the operation time of a timing key to obtain tone length information corresponding to the pitch information and input it into the performance information storage means,
Separately input the pitch information and length information of the song,
Moreover, the tone length information can be made to correspond to the time interval desired by the performer by operating a timing key. The second invention of the present invention provides a plurality of keys as the timing keys, each of which is associated with a different volume or timbre, and the sound read out from the performance storage means by operating each timing key. The musical sound based on high information can be generated at a selected volume or timbre to further enhance the performance effect, and like the first invention above, the timing key operation time is measured. In this way, tone length information corresponding to the time interval desired by the performer is obtained corresponding to each pitch information, and the information is input and stored in the performance information storage means. In the third invention of the present case, a plurality of timing keys are arranged in a matrix, one of the columns or rows corresponds to a different volume, and the other corresponds to a different tone, and the selected timing key is Similar to the first and second inventions above, the pitch information set in advance in the performance storage means is read out, and the scale note is generated with the volume and timbre corresponding to the column and row to which the timing key belongs. It is now possible to generate a scale sound with a fixed volume and timbre with a single touch, and as in the first and second inventions above, the timing key operation time is measured, The tone length information corresponding to the time interval desired by the performer is obtained corresponding to each pitch information, and the information is inputted and stored in the performance information storage means. The fourth invention of the present invention is such that the timing key is constituted by a press key switch that makes after a break, and when the timing key is pressed, the time from break to make is measured to obtain press speed information. The system is designed to generate scale tones based on pitch information read out from the performance information storage means in accordance with the operation of the timing key at a volume based on the press speed status information, and the tone is generated based on the pitch information read out from the performance information storage means in accordance with the operation speed of the timing key. The volume can be changed freely, and like the first to third inventions above, the timing key operation time is measured,
The tone length information corresponding to the time interval desired by the performer is obtained corresponding to each pitch information, and the information is inputted and stored in the performance information storage means. An embodiment of the present invention will be described below based on the drawings. FIG. 1 is a block diagram showing a schematic configuration of the electronic musical instrument system, in which 1 is a musical tone control section that enables keyboard performance, and 2 is a performance control section that shows the main parts of the electronic musical instrument of the present invention. . The musical tone control section 1 includes a key input control section 4 that receives key timings for each pitch by performance operations on a keyboard 3 having a large number of performance keys;
It consists of a musical tone generator 5, a musical tone memory 6, and a selected musical tone memory 7. The key input control section 4 supplies a key sampling signal to the keyboard 3, and upon receiving the operation timing of each performance key, applies pitch code data corresponding to each performance key to the musical tone generation section 5.
The musical sound generating section 5 generates a pitch frequency based on each pitch code data, and also performs musical sound control such as timbre, volume, etc., and has a timbre control circuit, a volume control circuit, etc., and performs the musical sound control. is performed according to the musical tone designation code. In the musical tone memory 6, a large number of musical tone designating codes are converted into binary codes and fixedly stored in advance in, for example, a ROM (read-on memory). The coded musical tone elements include, for example, codes for selecting musical waveforms such as triangle waves, sawtooth waves, and square waves, codes for selecting various tone filters, and selection codes for specifying one of multiple types of volume envelope curve formats. There are specification codes, etc., and a plurality of types of musical tones are set by a combination of selection and specification of each of musical waveforms, filters, volume envelopes, etc. The selected musical tone memory 7 is composed of a rewritable memory such as a RAM (random access memory), and has four storage areas in this example.
Then, desired four musical tones can be selected from among a large number of musical tones stored in the musical tone memory 6, and the musical tone memory 6
The desired musical tone is written in the specified musical tone coded state. 4 stored in the selected musical tone memory 7
By arbitrarily selecting one of the two musical tones during performance, it is possible to perform with a desired musical tone. Therefore, in order to generate one specified musical tone among the four musical tones stored in the selected musical tone memory 7, the musical tone generator 5 electronically controls the musical tone in the form of a musical sound waveform, a filter, and a volume envelope according to the selection designation code. is carried out. The musical tone signal outputted from the musical tone generating section 5 is outputted from the speaker 10 via an output control section 9 comprising acoustic effects such as reverberation and an amplifier. The performance control section 2 includes a performance memory 11, a memory input/output control section 12, a timing input/output control section 13, a time creation control section 14, an instruction control section 15, a key distribution circuit 16, and a volume control value generation circuit 17. The performance memory 11 is composed of a RAM (random access memory), and as shown in FIG. 2, one storage area is 7 bits, and each storage area has a pitch corresponding to a musical note for the performance of one song. It has a storage capacity that is sufficient to store data for each pitch, and is also capable of storing time data corresponding to each pitch. Of this one storage area, 6 bits are a code data storage section that stores pitch code data or time code data, and the other 1 bit is the data that is stored or will be stored in the code data storage section. Type code storage unit indicating whether it is pitch code data or time code data (instruction control signal of "1" in case of pitch code data and "0" in case of time code data)
It becomes. Therefore, as shown in FIG. 3, the performance memory 11 has a large number of storage areas, and each storage area is sequentially associated with addresses 0, 1, 2, . . . . The memory input/output control unit 12 controls inputting and outputting pitch code data from the timing input/output control unit 13, time code data and instruction control signals from the time creation control unit 14 to the performance memory 11, and This is performed in response to control signals from the timing input/output control section 13 and instruction control section 15. The timing input/output control unit 13 stores the key operation timing corresponding to the pitch specified by the performance keys of the keyboard 3, obtains the corresponding pitch code data, and stores the key operation timing in the performance memory during rhythmic performance or automatic performance, which will be described later. 11. A performance sound output timing signal controlled by the time creation control section 14 is supplied to the key input control section 4 of the musical tone control section 1. That is, when a performance sound output timing signal is sent from the timing input/output control section 13 to the key input control section 4, the musical tone control section 5 outputs the selected musical tone specified in the selected musical tone memory 7 regardless of the keyboard performance on the keyboard 3. The musical tones that follow the chords are emitted from the speaker 10. The basic configuration of the time creation control unit 14 is shown in FIG. 4, and includes a counting circuit that counts a constant basic clock signal, such as a binary counter 14-1, and an initial (start) count value of the binary counter 14-1. a decoder 14-2 that detects a plurality of time elapsed count values corresponding to time intervals that expand exponentially in the time elapsed from
It consists of an OR circuit 14-3 for merging the respective time elapsed count value outputs outputted from 4-2, and a counting circuit such as a binary counter 14-4 for counting the output signal of this OR circuit 14-3. That is,
In this system, a basic clock signal that generates an output pulse every 1 ms is counted by a binary counter 14-1 consisting of 11 bit stages. Then, as shown in FIG. 5, the decoder 14-2 determines the elapsed time t ₀ at a time interval that has an exponential (not necessarily a perfect exponential relationship) spread over time.
16 time states of t ₁ , t ₂ , ..., t ₁₄ , t ₁₅ are detected (however, t ₀ is not decoded). This t ₀ ,...
The time conditions at t ₁₅ are shown in Table 1. Note that each time interval is preferably a geometric series.

[Table] Then, from the OR circuit 14-3, t ₁ , t ₂ ...
..., an output signal is obtained in the time state _t15 , and the output signal is further counted by a binary counter 14-4 consisting of 4 bits. Therefore, the output state represented by 4 bits of the binary counter 14-4 becomes associated with each of t ₀ , t ₁ , . . . t ₁₅ as the code states shown in Table 1.
Further, the binary counters 14-1 and 14-4 operate to be cleared to the initial state and restart counting in response to a clear/start signal, which will be described later. The instruction control unit 15 includes K, I, S, E, and C, which will be described later.
Various control instruction signals are sent to the memory input/output control section 12 and the timing input/output control section 13 in response to commands from each key. Here, the above K, I, S, E, C
The functions of each key are explained in Table 2.

[Table] The timing operation keys 18 are keys for playing rhythms, and are used to obtain the note length between each pitch stored in advance in the performance memory 11. In this example, there are 16 keys, as shown in FIG. Consists of press keys. In addition, in FIG. 6, the pressed keys marked with symbols , , , in the vertical column correspond to the respective storage areas of the selected tone memory 7, , , , , , , , , , , ,
, and also the horizontal rows a, b, c, d
The press keys marked with are pressed so as to give commands to the musical sound generating section 5 to specify different volume control values. That is, the timing operation key 18 is supplied to the key distribution circuit 16, so that from now on, as shown in FIG. , d commands, a key-on command, and a key-off command are output. Then, the memory selection commands, . Further, the key-on command is supplied to the timing input/output control section 13 and the volume control value generation circuit 17, and the key-off command is supplied to the memory input/output control section 12. Here, I will give an overview of the performance method in this system.In this system, you can perform normal keyboard performance by operating the keyboard 3, or play only the rhythm of the song by operating one or more timing operation keys 18. Three performance methods are possible: rhythmic performance by plucking, and automatic performance in which you can repeatedly listen to a song based on the pitch on the musical score and the memory of the rhythmic performance. Needless to say, the keyboard performance involves playing a piece of music played by operating the performance keys on the keyboard 3 with a desired musical tone by the musical tone control section 1. For rhythmic performance, turn on the K key to enter pitch input mode. For example, while looking at the musical score, press the pitch keys on keyboard 3 one after another (in the case of chords, press multiple keys at the same time). Then, each pitch code data is sequentially written into the performance memory 11. After writing everything, rhythm performance is performed while reproducing the memorized pitch using the timing operation key 18. (However, the musical tone can be changed arbitrarily by specifying each storage area of the selected musical tone memory 7 with the corresponding press key of the timing operation key 18 in FIG. 6, and the volume can also be controlled by timing. (can be controlled by pressing the corresponding press key of the operation key 18). The tone length between the pitches by the timing operation key 18 of this rhythm performance is stored in the performance memory 11 in correspondence with each pitch.
Therefore, by storing only the pitch in advance in the performance memory 11, and then using the timing operation keys 18 to play the rhythm while reproducing the memorized pitch, you can perform your own performance with simple rhythmic key operations. It is possible to play a song and memorize the length of the notes at the same time. In the case of automatic performance, by operating the timing operation key 18 during the rhythmic performance, the previous timing operation key 18
Since the note length of the time interval from the last touch to the current operation of the timing operation key 18 is sequentially stored in the performance memory 11, when you listen to the song you played again, you can automatically hear it by simply pressing the S key. It is possible to play a song (note that by memorizing not only the time interval but also the timing operation key 18 pressed each time, it is possible to automatically specify the volume control and the musical tone). It should be noted that the rhythmic performance and automatic performance described here are only summaries, and more specific operating methods and control methods will be understood from the following explanation. The specific configuration of the performance control section 2 is shown in FIG. The K, I, S, E, and C key operation signals are applied to the instruction control section 15. This instruction control section 15 sets a flip-flop circuit (hereinafter referred to as FF) 15-1 by operating the K key and outputs a pitch input mode signal, and outputs an AND gate 15 by operating the I key while the FF 15-1 is set.
A zero write command that writes "0" to the type code storage section of the RAM 11 and skips to the next address via -2, which will be described later, can be sent to the FF by operating the S key.
15-3 to issue an automatic performance start command.
When the E key is operated, FF15-4 is set and a time input mode signal is output, and when the C key is operated, a clear command is output. On the other hand, the scale counter 13-1 is the basic clock.
It is a binary counter that always counts ₁ and ₂ , and the carries of this scale counter 13-1 are counted by an octave counter 13-2. In this case, the number of performance keys on the keyboard 3 is 48 (12 x 4 matrix arrangement), so the scale counter 13-1 has 4 bits in decimal notation, and the octave counter 13-2 has 2 bits in decimal notation. Each bit output of the scale counter 13-1 and octave counter 13-2 is sent to the decoder 1, respectively.
3-3 and 13-4. Decoder 13-
3 has 12 output lines connected to the keyboard 3, and key sampling signals are supplied in counting order. 4 from decoder 13-4
The output line of the book is AND gate 13-5, 13-
6, 13-7, and 13-8, respectively, and four output lines from the keyboard 3 are connected to the other input ends, respectively. The outputs of the AND gates 13-5 to 13-8 are connected to an OR gate 13-9, and the operations of 48 performance keys can be output from the OR gate 13-9 at different key timings.
Furthermore, the key timing signal obtained from the output of the OR gate 13-9 is supplied to a dynamic shift register 13-13 via an OR gate 13-10, an AND gate 13-11, and an OR gate 13-12. This shift register 13-13 consists of 48 bits corresponding to the number of keys and receives a clock signal.
₁ and ₂ , and its output is connected to its own input side via AND gates 13-14 and OR gates 13-12. Therefore, the timing signal once input is circulated until a clear command is issued. Retained. The output of the shift register 13-13 is connected to the AND gate 13-11 by the inverter 13-11.
Since the signal inverted at 15 is supplied, at the same timing as the timing signal once input to the shift register 13-13, this AND gate 13
No output signal is obtained from -11, and only the first shot is output. Also, and gate 13-1
A clear signal is applied to 4 from a clear circuit 13-16, which will be described later, via an inverter 13-17, and when this clear signal is generated, the circulation of the shift register 13-13 is blocked, resulting in a shift. Register 13-13 is cleared. Furthermore, the output of the OR gate 13-9 is connected to the first input terminal of the AND gate 13-19 via an inverter 13-18, and the output of the shift register 13-13 is connected to the second and third input terminals, respectively. Said
The pitch input mode signal of FF15-1 is applied. Therefore, a key-off signal can be obtained from the AND gate 13-19 at the time when the performance key pressed at the time of generation of the pitch input mode signal is released. 13-20 is when inputting the pitch of each key played on keyboard 3 while looking at the score (in the case of chords, pressing multiple keys at the same time is considered as one pitch input)
This is a detection circuit to indicate the break in the pitch and to prevent chattering of key operations, and outputs an output signal 100ms after the key is released for each pitch input. That is, when the pitch input mode signal is generated, the AND gate 13 is
-11 output signal opens AND gate 13-20a, FF13-20b is set, and the set signal is supplied to AND gate 13-20c. On the other hand, the FF13-20d is set by the key-off signal of the AND gate 13-19, and the FF13-20d is set for 100 m each time via the OR gate 13-20e.
The counter 13-20f that counts the time s is cleared. When FF 13-20d is set, clock signal ₁ is output from AND gate 13-20g, and counting is started by counter 13-20f. Also, FF13-20d and counter 13-20f are respectively OR gate 13-20
AND gate 13-1 via h, 13-20e
It operates so that it is reset and cleared by the key-on signal output from 1. Therefore, counter 1
Since 3-20f is cleared each time a key-on signal and a key-off signal are generated, an output is obtained from the counter 13-20f 100 ms after the last key-off signal is released, and the AND gate 13-20c is opened for the first time. With this, FF13-20b, 1
3-20d is reset and returns to the initial state. The output signal of the AND gate 13-20c is the OR gate 13-1 of the clear circuit 13-16.
The FFs 13-16b are set through the gates 6a and the set signals are supplied to the AND gates 13-16c.
This AND gate 13-16c is opened by the carry of the octave counter 13-2, and is further opened by the carry of the FF13.
-16d and supplies the set signal to AND gates 13-16e. and gate 13
-16e is opened by the carry of octave counter 13-2, and its output signal causes FF13-1
6b and 13-16d. That is,
FF13-16d is set by the first carry signal after FF13-16b is set, and is output from AND gate 13-16e. It is reset in synchronization with the next carry signal. Therefore,
The FFs 13-16d generate output signals for one word time (one cycle time) of the shift register 13-13. The output signal of the FF 13-16d is applied as a clear signal to the AND gate 13-14 via the inverter 13-17, and is applied as a gate open signal to the AND gate 13-21. The AND gate 13-21 is further applied with the output of the shift register 13-13, a pitch input mode signal, and a signal from an erasing circuit 13-22, which will be described later. The timing signals input to the registers 13-13 are sequentially output at one word time 100 ms after all performance keys are released. The erasing circuit 13-22 is configured to erase an error by pressing the C key while the pitch input mode signal is being pressed when an incorrect pitch is input by operating a performance key while the pitch input mode signal is being generated. This prevents the timing signal input to the shift register 13-13 from being output from the AND gate 13-21. In other words, if an incorrect key is pressed when the pitch input mode signal is generated, AND gate 1 will be activated.
The key timing signal is input to the shift register 13-13 via FF1
3-20b is set and applied to the AND gate 13-22a of the erase circuit 13-22. When the C key is pressed in this state, the AND gate 13-22a is opened and the FF 13-22b is set. and,
FF13-22b is 100m after releasing the wrong key.
Since it is not reset until after the clear signal is generated after s, the key timing signal input to the shift register 13-13 is only cleared by the clear signal and the key timing signal is cleared by the AND gate 13-2.
There is no output from 1. Therefore, it is only necessary to input the correct pitch after that. Also, shift register 1
The output of 3-13 is also connected to the AND gate 13-23 which is opened during rhythmic performance and automatic performance. The key timing signal input to the shift register 13-13 output from the AND gate 13-21 is supplied to the AND circuit 12-1, the AND gate 12-2, and the AND gate 12-3 as a gate output timing signal. Ru. Each bit output (pitch code data) of the scale counter 13-1 and octave counter 13-2 is applied to the AND circuit 12-1, and a "1" signal is constantly applied to the AND gate 12-2. . Therefore, from the AND circuit 12-1, the shift register 13-1
3, the pitch code data corresponding to the pressed key is outputted and passed through the OR circuit 12-4.
It is supplied to RAM11. Further, a "1" signal is also supplied from the AND gate 12-2 to the RAM 11 in synchronization with the key timing signal input to the shift register 13-13. That is, the pitch code data is stored as "1" in the 6-bit code data storage section of the RAM 11 as shown in FIG.
The signal is stored in the type code storage section.
The AND gate 12-3 outputs a signal in synchronization with the clock signal ₁ , and outputs the signal through the OR gate 12-5.
RAM11 address counter (ADC) 12-6
It operates to advance by "+1". As a result, the pitch code data and "1" are stored in RAM11.
Address counter 12-6 after writing the signal
is controlled to advance the RAM 11 address by one and wait. The address counter 12-6 is connected to the AND gate 13- of the clear circuit 13-16.
One shot circuit 1 receives the output signal of AND gate 12-7 to which the one word time end signal from 16e is applied, and the output of AND gate 15-2 of instruction control section 15 opened by pressing the I key.
It is also incremented by "+1" by the output of 2-8. I
When a key is operated, the address is changed to 1 by simply writing "0" to the type code storage section of RAM11.
Operates to move forward. Note that the address counter 12-6 is the FF15- of the instruction control unit 15.
1, 15-3, and 15-4, it is reset (to the "0" address state) via the OR gate 12-9. The FF 12-10 gives write and read commands to the RAM 11, and a write command is "0" and a read command is "1". When a pitch input mode signal is generated by operating the K key, FF12- is output via OR gate 12-11.
10 is in a reset, ie write command state. Next, it will be set when you operate the E key.
The set output of FF15-4 is OR gate 12-1
In order to set the FF 12-10 to the set state via the FF 12-10, a read command is applied to the RAM 11 from its Q side output, and at the same time, the address counter 12-6 is reset via the OR gate 12-9. Furthermore, it is supplied as a gate control signal to the AND gates 12-13, 12-14, and also to the AND gates 12-16, 12-17 and the AND gate 13-23 via the OR gate 12-15. When a read command is given to the RAM 11, the address counter 12-6 is incremented by "+1" by the clock signal output from the OR gate 12-18, and the buffer registers 12-19, 12-20 are
The contents of the RAM 11 are written in synchronization with the clock signal. The 6 bits of the code data storage section are written into the buffer register 12-19, and the contents of the type code storage section are written into the buffer register 12-20. When the timing operation key 18 is operated, a key-on signal is output from the key distribution circuit 16 no matter which key is operated, and the OR gate 13-16a of the clear circuit 13-16 of the timing input/output control section 13 is output.
Set FF13-16b via. For this reason, the shift register 13-13 is cleared by a clear signal of one word time as described above. The one word time end signal output from the AND gate 13-16e is supplied to the OR gate 12-18 as an increment signal for the address counter 12-6 via the AND gate 12-17 and the AND gate 12-21a. 1-bit delay circuit 1
2-22 to the binary counters 14-1 and 14-4 of the time creation control section 14 as a clear/start signal. Therefore, when the timing operation key 18 is operated, the shift register 13 is first activated.
-13 is cleared, and after the clearing, the binary counter 14-1 starts counting operation. and,
This operation is repeated every time the timing operation key 18 is pressed. Each time the timing operation key 18 is pressed, the contents of the storage area of the RAM 11 written in the buffer registers 12-19, 12-20 are supplied to the coincidence circuit 12-23. This matching circuit 12-
23 is supplied with pitch code data which is the count contents of the scale counter 13-1 and the octave counter 13-2. That is, when the buffer register 12-20 has a "1" signal, the matching circuit 12-23 detects a match between the contents of the buffer register 12-19 and the pitch code data obtained by the counters 13-1 and 13-2. The matching timing signal is sent to the OR gate 13-10 of the timing input/output control section 13 via the AND gate 12-16.
is supplied to Therefore, shift register 13-1
3, input is made in the same manner as in the case of operating the performance keys on the keyboard 3. The coincidence timing signal from AND gate 12-16 is then applied to OR gate 12-18. On the other hand, the output of the buffer register 12-20 is directly sent to the AND gate 12-24.
AND gate 12 via inverter 12-25
-13 and 12-14, and the output of the type code storage section of the RAM 11 is applied directly to the AND gate 12-14 and to the AND gates 12-13 and 12-24 via the inverter 12-26. Therefore, AND gates 12-13 are opened when the outputs of buffer registers 12-20 and RAM 11 are both "0" signals, and set FFs 12-27. On the other hand, the AND gate 12-14 is opened when the output of the buffer register 12-20 is "0", the output of the RAM 11 is "1", and the FF12-27 is reset (the output is "1"), and the FF12-20 is opened when the output is "1". 2
Set 8. And FF12-27,12-
28 is reset by the output signal detected by AND gates 12-24. This FF12-27
The set outputs of FF12-28 and FF12-28 are both sent to address counter 12-6 via OR gate 12-29.
It is supplied to the FF 12-10 as a set signal via the OR gate 12-12. Furthermore, FF12-2
The output of 7 is AND gate 12-30, 12-31
, the output of FF12-28 is AND gate 12-
32. That is, AND gate 12-3
0 is an FF that detects that a “0” signal is continuously written in the type code storage section of the RAM 11.
In the set output state of 12-27, the timing of the key-off signal of the timing operation key 18 is detected. The AND gate 12-31 is a key-on signal of the timing operation key 18.
It is output in synchronization with the end signal of one word time from -17. Also, and gate 12-32
is "0" in the type code storage section of RAM11,
It is output in synchronization with the termination signal output from the AND gate 12-17 in the set state of the FF 12-28 which detects a continuous state of "1". Each output of these AND gates 12-30, 12-31, and 12-32 is applied as a gate signal to an AND circuit 12-34 via an OR gate 12-33, and from the AND circuit 12-34, a time signal is output at the output timing. The 4-bit time code data of the binary counter 14-4 of the creation control unit 14 is output, and the time code data is passed through the OR circuit 12-4.
It is input to RAM11. That is, the AND circuit 12
The time data output from -34 is the time data from the previous operation of the timing operation key 18 to the current operation of the timing operation key 18 at the output timing of the AND gate 12-32.
Furthermore, at the output timing of the AND gate 12-30, the time period during which the timing operation key 18 is held down, that is, the time when one timing operation key 18
This is time data from the on point to the off point.
On the other hand, the output of the AND gate 12-30 provides a clear/start command to the time creation control unit 14 via a clear circuit 13-16 and a delay circuit 12-22. Therefore, the output timing of the AND gate 12-31 is the time data from the key-off point until the next timing operation key 18 is pressed. In addition, the outputs of the AND gates 12-31 and 12-32 are connected to the OR gate 12-35 and the delay circuit 12-36.
is supplied to the OR gates 12-37 and 12-38 via the OR gate 12-12.
Set FF12-10 to output a read command. The output of the AND gate 12-30 is further supplied to the OR gate 12-37, and the output is passed through a delay circuit 12-39 to the OR gate 12-37.
38. That is, AND gate 12-3
At the output timing of AND gate 12-32, the address counter 12-6 is incremented by "2" steps, and at the output timing of AND gate 12-30, the address counter 12-6 is incremented by only one step. It is applied to OR gates 12-18. In this way, when the E key is operated, pitch code data stored in advance in the RAM 11 is read out, a corresponding timing signal is input to the shift register 13-13, and sent to the musical tone control section 1 via the AND gate 13-23. The duration of each pitch is determined by the rhythm operation of the timing operation keys 18 by oneself. That is, the timing signals of each pitch input to the shift register 13-13 are sequentially outputted from the AND gate 13-23 for the duration of the tone determined by the operation of the timing operation key 18 and sent to the tone control section 1. Also, the time data of this note length is RAM1
The code is input to the code data storage section of the storage area in which "0" is written in the type code storage section 1. The key input control section of the musical tone control section 1 includes a scale counter 13-1 in the performance control section 2 shown in FIG.
Octave counter 13-2, decoder 13-
3, 13-4, and gate 13-5, 13-
6, 13-7, 13-8, or gate 13-9,
Since there is a circuit that inputs the key timing signal of the performance key corresponding to the shift register 13-13, etc., the signal output from the AND gate 13-23 in Fig. 8 follows the path shown by the broken line from its output. The signal is directly inputted to the shift register 13-13 through the OR gate 13-9 in FIG. 8 of the key input control section 4 of the musical tone control section 1. Next, for automatic performance by S key operation, FF15
-3 is output, FF12-10 is set to issue a read command, address counter 12-6 is reset, and AND gates 12-16, 12-17, 1 are output via OR gate 12-15.
A gate signal is applied to 3-23. FF15-
The output of 3 is AND gate 12-40, 12-41
Also supplied. AND gate 12-40 is opened by the output of inverter 12-25, sets FF 12-43 with its output signal, and applies the set signal to matching circuit 12-42. Matching circuit 12-
42 contains the time code data stored in the buffer registers 12-19 and the time creation control unit 14.
The time code data represented by 4 bits is supplied to the binary counter 14-4 of
Coincidence with each time code data is detected only when there is a "0" signal in the buffer registers 12-20. The match signal is then supplied to the OR gate 13-16a of the clear circuit 13-16 and resets the FF 12-43. Also S
At the time of key operation, the address counter 12-6 is reset, but it is immediately incremented by "+1" via the delay circuit 12-44, the OR gate 12-18, and the OR gate 12-5, and the buffer register 12-6 is incremented by "+1" immediately.
A read signal is also applied to -19 and 12-20. Therefore, when the S key is operated, the memory contents of the address "0" of the RAM 11 are transferred to the buffer register 12-.
19, 12-20. Also, the output of the AND gate 12-41 is the volume control value generation circuit 1.
7 is given as a read command to the volume control value memory 17-1. Therefore, in the case of automatic performance, RAM
The pitch code data of the storage area in which "1" is written in the type code storage section 11 is the matching circuit 1.
A match is detected at 2-23. Then, the matching timing signal is input to the shift register 13-13, and the pitch is generated using the time interval of the time data in the storage area where "0" is written in the type code storage section as the sound length. shift register 1
Apply the timing signal in 3-13 to AND gate 1
3-23 to the key input control section 4 of the musical tone control section 1. The output of the AND gate 12-41 is given to the volume control value memory 17-1 of the volume control value generation circuit 17 as a read command. The volume control value generation circuit 17 supplies the volume control values a to d output from the key distribution circuit 16 to the musical tone generating section 5 of the musical tone control section 1 via the OR gate 17-2, and controls the volume in synchronization with the key-on signal. The value is stored in the value memory 17-1. The volume control values a to d are stored in different binary code formats each represented by 4 bits, for example. The volume control value memory 17-1 is composed of, for example, a RAM. The volume control values a to d written in the volume control value memory 17-1 are sequentially read out in synchronization with the read command output from the AND gate 12-41 during automatic performance, and are read out via the OR gate 17-2. The signal is supplied to the musical tone generator 5. These volume control values a to d are, for example, a, b, c,
These are different volume control values that control the absolute volume appropriately lower in the order of d. Now, the operation of pitch input to the RAM 11 will be explained using the state shown in FIG. First, the FF of the instruction control unit 15 is activated by operating the K key.
15-1 to generate a pitch input mode signal and to reset the address counter 12-6 to the "0" address state. Further, a write command is applied to the RAM 11. Then, while looking at the score, use keyboard 3 to operate the performance keys that correspond to the pitches of B ₂ , C ₃ , C ₅ , G ₄ , and D ₁ (chords) in order, and then press I.
key, and then sequentially operate the performance keys corresponding to pitches E ₅ and A ₃ . When the B ₂ key is pressed, the key timing signal corresponding to that key is output from the OR gate 13-9, and the OR gate 13-9 outputs the key timing signal corresponding to that key.
10, AND gate 13-11, OR gate 13
-12, the timing signal is input to the shift register 13-13 and cyclically held. Then, when you release this B ₂ key, and gate 13-1
Since the key-off signal is obtained from 9 and FF13-20d is set, counter 13-20f is set.
counts the clock signal ₁ output from AND gate 13-20g. Counter 13-2
0f supplies an output signal to the AND gate 13-20c after 100 ms has elapsed. At this point FF1
Since FF 3-20b is already in the set state, FF 13-16b is set by the output signal from AND gate 13-20c via OR gate 13-16a. When a clear signal is obtained from the clear circuit 13-16, a key timing signal for the _B2 key is output from the AND gate 13-21, and the AND gate 13-14 is closed, so that this timing signal is transferred to the shift register 13.
Cleared from -13. AND GATE 13-2
The key timing signal of the _B2 key output from the AND circuit 12-1 and the AND gate 12-2
applied to the key timing signal and synchronized with that key timing signal.
The pitch code data and "1" signal of the B ₂ key are stored in the code data storage section and type code storage section of the storage area of the "0" address of the RAM 11, respectively.
It is written as shown in figure a. When this write is completed, the address counter 12-6 is incremented by "+1" by the output of the AND gate 12-3, advances to the next address "1", writes "0" to the type code storage section of that address, and waits. I come to do it. In this case, since only one key is pressed, it waits at the "1" address, and then the address counter 12-6 further increases "+1" with the 1 word time end signal output from the AND gate 13-16e. It is incremented and eventually waits at address "2". Next, when the C ₃ key is pressed, the pitch code data and the "1" signal corresponding to the C ₃ key are stored in the code data storage section and type code storage section of the storage area at address "2" of the RAM 11, respectively, in the same way as above. It will be written as shown in Figure 9b, and will wait at address "4". Furthermore, when a pitch is input as a chord by simultaneously pressing the three performance keys C ₅ , G ₄ , and D ₁ (in this embodiment, a chord is also referred to as one pitch for the purpose of explanation), the shift register 13- A key timing signal corresponding to each key is input to 13 and held in circulation. Then, from the time when all three keys C ₅ , G ₄ , and D ₁ are released, the counter 13-20f measures 100 m.
When the output signal is obtained from the AND gate 13-20c after the elapse of time s, a clear signal is subsequently output from the clear circuit 13-16.
Therefore, three key timing signals corresponding to the C ₅ , G ₄ , and D ₁ keys input to the shift register 13-13 are output from the AND gate 13-21, and these key timing signals are also input to the shift register 13-13. Cleared from 13 onwards. Pitch code data corresponding to each key timing signal output from the AND gate 13-21 is sent via the AND circuit 12-1 and the OR gate 12-4 in synchronization with each key timing signal.
The code is stored in the code data storage section of the storage area at addresses "4", "5", and "6" of the RAM 11. Of course, a "1" signal is written into the type code storage section each time each pitch data is stored. That is, when each data is written to the storage area of address "4" by the key timing signal of the _C5 key of the shift register 13-13, the AND gate 12-3 is written.
The address counter 12-6 increments by one in response to the "+1" increment signal from , and waits at the next address "5". In the key timing signal of the _G4 key, each data is written corresponding to the storage area of address "5", and it waits at the next address "6". Furthermore,
In the key timing signal of the _D1 key, each data is written corresponding to the storage area at address "6", and at the next address "7", "0" is written to the type code storage section of the storage area and waits. After that, the key timing signal disappears, so the address counter 12-6 does not increment, and the AND gate 13-1
In response to the one word time end signal outputted from 6e, it advances by "+1" and eventually waits at address "8". Next, press the I key and the one shot circuit 12-
Address counter 12-6 is incremented by +1 via OR gate 12-7 and OR gate 12-5 in response to the one shot signal output from 8. That is,
I will be waiting at address "9", and I will wait at address "9".
Two consecutive "0" states are stored in the type code storage section of the RAM 11 as shown in FIG. Thereafter, when the E ₅ key and the A ₃ key are pressed, the data will be stored as shown in FIG. 9e and FIG. 9f, respectively, by the above-described storage operation. As a result, as shown in FIG. 9(f), only pitch code data is sequentially stored in the storage area of each address of the RAM 11 in a state where it is divided into pitches (in the case of chords, a plurality of chords are grouped). Although it will be explained in detail later, note length time data will be stored later in the storage area where "0" is written in the type code storage section, and the time data of the note length will be stored in the storage area where "0" is written in the type code storage section. A so-called pause time during which no sound is output is stored in the code data storage section of the storage area "0". Next, the tone length input operation when the E key is operated to instruct the tone length (time) input side will be explained using the state diagram shown in FIG. Only the pitch code data is stored in the RAM 11 as shown in FIG.
4 is set, the address counter 12-6 of the RAM 11 is placed in a reset state,
A read command is issued from FF12-10.
Also, and gates 12-13, 12-14, 1
2-16 and 12-17 are also placed in an openable state. In this initial state, the timing operation keys 18 shown in FIG. 6 are operated in accordance with the rhythm without inputting pitch code data. In FIG. 10, the timing operation key is represented by the □T key. In this case, the performer can arbitrarily operate the 16 timing operation keys according to his or her own senses to instruct performance information for volume control and tone selection. When the b key in FIG. 6 is pressed as the first timing operation key 18, the key distribution circuit 16 outputs a key-on signal, volume control value b, and memory selection command, and the volume control value b is output from the OR circuit 1.
The memory selection command is supplied to the selected musical tone memory 7 to the musical tone generating section 5 via 7-2. Incidentally, the volume control value b is also written into the volume control value memory 17-1. Therefore, by pressing the b key, the absolute volume is controlled by the volume control value b and the pre-stored musical tone is stored in the storage area of the selected musical tone memory 7 until the next timing operation key is pressed. The sound will be emitted from the speaker 10. Since the key-on signal from the b key is supplied to the clear circuit 13-16, the shift register 13-13 is first cleared. Furthermore, the AND gate 13-16e of the clear circuit 13-16
The clear end signal output from AND gate 1
2-17, as a "+1" increment signal to the address counter 12-6 via the OR gate 12-18,
It is also applied as a read signal to buffer registers 12-19 and 12-20. Furthermore, binary counters 14-1, 14-4 of the time creation control unit 14
is cleared and counting starts from the initial state. Then, the pitch code data B ₂ and the instruction control signal "1" in the storage area of "0 address" of the RAM 11 are transferred to the buffer registers 12-19 and 1, respectively.
At the same time, the storage area of the RAM 11 at the address "1" becomes an output state.
The pitch code data _B2 and instruction control signal "1" written in the buffer registers 12-19 and 12-20 are supplied to a coincidence circuit 12-23. That is, in the matching circuit 12-23, the buffer register 1
The pitch code data B ₂ in 2-19 is compared with the pitch code by the scale counter 13-1 and the octave counter 13-2, and the matching timing signal is sent to the OR gate 13-10 and the AND gate 13-11. , and are input to the shift register 13-13 via OR gates 13-12 in order. The timing signal corresponding to the pitch _B2 input to the shift register 13-13 is cyclically held and sent to the key input control section 4 of the musical tone control section 1 via the AND gate 13-23 (Fig. 10). (see a). As mentioned above, the key input control section 4 is composed of a shift register similar to the shift register 13-13 of the performance control section 2, a scale, an octave counter, etc.
Pitch code data _B2 is decoded in accordance with the timing signal sent from 3-13, and based on the pitch frequency of _B2 , the tone of the musical tone in the storage area of the selected musical tone memory 7 is transmitted to the speaker 10 using the volume control value b. The pronunciation begins from On the other hand, since the coincidence timing signal output from the coincidence circuit 12-23 is also applied to the OR gate 12-18, the address counter 12-6 is incremented by "+1" and the buffer registers 12-19, 1
A read signal is supplied to 2-20. For this reason,
The memory contents of address "1", that is, zero, are written into the buffer registers 12-19 and 12-20, and the memory contents of address "2" of the RAM 11 become output. Therefore, AND gate 12-1
4 is opened and FF12-28 is set, and the set signal is supplied to the AND gate 12-32, and also gives a "-1" reverse signal to the address counter 12-6 via the OR gate 12-29.
Supply a reset signal to 2-10 and issue a write command.
Give it to RAM11. At this point, the RAM 11 waits in the write state of address "1". Next, if the d key in FIG. 6 is pressed in time with the rhythm as the second timing operation key 18, a key-on signal is output from the key distribution circuit 16 as described above, and a clear signal is output from the clear circuits 13-16. The timing signal of pitch _B2 in the shift register 13-13 is cleared by the signal, and is no longer sent to the musical tone control section 1. On the other hand, since the one word time end signal from the clear circuit 13-16 is supplied to the AND gate 12-32 via the AND gate 12-17, this AND gate 12-32 is opened and the output signal is output from the OR gate 12-32. AND circuit 12-34 through 33
is applied as a gate control signal. Then, at the timing of generation of this gate control signal, the time data in the binary counter 14-4 of the time creation control section 14 is transferred to the AND circuit 12-34 and the OR circuit 12.
-4, it is written to the storage area of address "1" of RAM11. In other words, as shown in Figure 10b, the time interval (T ₁ to _{T 2} ) from the first □T key (b key) operation to the current □T key (d key) operation is equal to the pitch.
It is written as _B2 tone length data.
In addition, since the output signal of the AND gate 12-17 is applied as a clear/start command to the time creation control unit 14 via the delay circuit 12-22, the binary counters 14-1 and 14-4 are operated at the address "1" of the RAM 11. After the time data is written to ``, it is cleared and counting starts again from the initial state. Furthermore, the output of the AND gate 12-32 is passed through the OR gate 12-35 and the delay circuit 12-36.
Applied as a set signal to FF12-10 and RAM
Give lead command to 11 and or gate 12
-38, as a result, a "+2" increment signal is applied to the address counter 12-6, so the buffer registers 12-19 and 12-20 are eventually
The contents at the address "2" of the RAM 11 are written, and the contents at the address "3" are output from the RAM 11. The pitch code data C ₈ written in the buffer register 12-19 and the "1" signal written in the buffer register 12-20 are supplied to the matching circuit 12-23, so that the pitch code data C8 written in the buffer register 12-19 and the "1" signal written in the buffer register 12-20 are supplied to the matching circuit 12-23.
-1, a match with pitch code data is detected by the octave counter 13-2. The coincidence timing signal is then input to the shift register 13-13 and output from the AND gate 13-23 to be sent to the musical tone control section 1. Musical tone control section 1
Since the storage area of the selected musical tone memory 7 and the volume control value d are supplied by operating the d key, the pitch _C3 is sounded from the speaker 10 with musical tone control and volume control based on this (Fig. 10). b). Assuming that the a key in FIG. 6 is operated as the third timing operation key 18, the same operation as described above causes the address "3" of the RAM 11 to be changed from the second d key operation to the third time as shown in FIG. 10 c. The time data (T ₂ to _{T 3} ) up to when the a key is operated is written. And buffer register 12-19
First, the memory contents of address "4" are written into the buffer register 12-20, and the matching circuit 12-20 is written.
The timing signal of pitch C ₅ that matches at 23 is input to the shift register 13-13, and then the memory contents of address "5" are written to the buffer registers 12-19 and 12-20, and the matching circuit 12 -23 to pitch _G4 are inputted to the shift register 13-13, and similarly, a timing signal of pitch _D1 is inputted. Therefore,
In this case, three timing signals are input to the shift register 13-13 and sent to the tone control section 1. Based on these three timing signals, the key input control section 4 of the musical tone control section 1 controls the musical tone as a chord in the musical tone generating section 5, and generates the musical tone from the speaker 10 by specifying the musical tone in the selected musical tone memory by operating the a key and by using the volume control value a. (10th
(see figure c). Then, when the matching circuit 12-23 outputs the three matching timing signals,
The memory contents of address "7" are written to buffer registers 12-19 and 12-20, and RAM1
1 puts the storage contents at address "8" into the output state. Therefore, in this case, the AND gate 12
-13 is opened and FF12-27 is set. The set signal provides a "-1" reverse signal to the address counter 12-6 via the OR gate 12-29, and also resets the FF 12-10 to become a write command. Also, and gate 12-30,1
2-31 is also supplied. For this reason, first, when the a key off signal is output from the key distribution circuit 16, the AND gate 12-30 is opened, and the time data during the ON operation of the a key is sent from the AND circuit 12-34 to the binary counter of the time control section 14. 14-4
The data is written to the storage area at address "7" of the RAM 11. That is, as shown in FIG. 10d, the on-operation time (T ₃ to T ₃ ') of the a key is written. The output of the AND gate 12-30 is applied as a clear/start command to the time control unit 14 via the clear circuit 13-16 and the delay circuit 12-22, and counting starts again from the initial state. Also, the output of the AND gate 12-30 is the OR gate 12-37, the delay circuit 12-39, the OR gate 1
2-38, the address counter 12-6 is incremented by "+1" via the OR gate 12-18,
Specify address "8" of RAM11. Next, when the c key is pressed as the fourth timing operation key 18, the same operation as described above is performed.
The time interval (T ₃ ′ to T ₄ ) The time data is written as shown in FIG. 10e. and,
The memory contents of the address "9" of the RAM 11 are written to the buffer registers 12-19 and 12-20, and the timing signal of pitch _E5 from the matching circuit 12-23 is input to the shift register 13-13.
The musical tone control unit 1 produces a musical tone and volume specified by the c key. Below, similarly, the fifth timing operation key 1
8, as shown in FIG. 10 f, the time data of the time interval T ₄ to _{T 5} from when the c key is turned on to when the timing operation key 18 is turned on for the fifth time is written to the memory area at address "10" of the RAM 11. It can be done. In this way, when specifying the E key, while playing the pre-stored pitch from the speaker 10,
It operates so as to sequentially store the time intervals of tone lengths between pitches written in the RAM 11 in a binary coded state. Further, volume control values b, d, a, c, . . . are sequentially stored in the volume control value memory 17-1 each time the timing operation key 18 is operated. Next, as shown in FIG. 10(f), the operation of reading data from the RAM 11 in which pitch and duration data are stored in automatic performance will be described. Press the S key to set FF15-3, reset address counter 12-6, and then set FF12-10.
is set and a read command is given to RAM11.
Furthermore, it is supplied to the AND gates 12-40 and 12-41 as a gate control signal, and the delay circuit 1
2-44, supplies a "+1" increment signal to the address counter 12-6 and a read signal to the buffer registers 12-19 and 12-20 via the OR gate 12-18. Therefore, at this point, the pitch code data of _B2 and the instruction control signal "1" are written in the buffer registers 12-19 and 12-20, respectively, and the output of the RAM 11 is the content of the storage area at address "1". is output.
Incidentally, by operating the S key, the time creation control section 14 performs a clear/start operation (not shown). Therefore, in the same way as when inputting the tone length described above, the matching circuit 12-23 inputs the data stored in the buffer register 12-19.
_B2 pitch code data and scale counter 13-
1. The octave counter 13-2 detects coincidence with the pitch code data, and inputs the coincidence timing signal to the shift register 13-13.
This coincidence timing signal is the OR gate 12-18
Since the address counter 12-6 is incremented by "+1", the memory contents stored at the address "1" of the RAM 11 are written to the buffer registers 12-19 and 12-20. It can be done. That is, this time buffer register 12-20
Since the instruction control signal “0” is written in
FF12-43 via AND gate 12-40
is set, and the set signal is sent to the matching circuit 12-4.
2 as a comparison command. This matching circuit 12
-42, a match between the time code data (time interval _T1 to _T2 ) in the buffer register 12-19 and the time count value of the binary counter 14-4 of the time creation control section 14 is detected. When the coincidence detection signal is obtained, it resets the FF 12-43 and applies it to the clear circuit 13-16, thereby clearing the shift register 13-13. Furthermore, the clear completion signal from the AND gate 12-17 is supplied to the AND gate 12-22a and the OR gate 12-18, which shifts the address and stores the address "2" of the RAM 11 in the buffer registers 12-19 and 12-20. The contents will be written. Based on the output of the AND gate 12-17, the time creation control section 1
The binary counters 14-1 and 14-4 of No. 4 perform clear/start operations. Therefore, the timing signal corresponding to the pitch of _B2 input to the shift register 13-13 is cyclically held for the time period T1 to T2 in the storage area at address " ₁ " of the RAM ₁₁ , and is also sent to the AND gate 13. -23 to the musical tone control section 1. In this way, the pitch code data stored in the RAM 11 shown in FIG. It is controlled so that it is sent to 1. Note that if you press the E key during automatic performance, FF15-3 of the instruction control section 15 will be reset.
By operating the S key again, automatic performance can be started from the beginning. The timing operation keys 18 are arranged as shown in FIG. 6, and a plurality of press keys are provided for volume control, but a single press key may be used instead. FIG. 11 shows the configuration of a press key as one timing key, in which a pair of electrodes 101, 102 and 103, 104 are provided on the front and back surfaces of a substrate 100, respectively, and are integrally attached to a press bar 105. The flat plates 106 and 107 are covered with conductive rubber 108 and 1, respectively.
09 is retained. The state is normally as shown in the figure, and by pressing the electrode 103
and 104 are separated (break), and electrodes 101 and 10
2 is made conductive. A volume control value can be obtained even with this one pressed key. That is, since the time from break to make differs depending on the speed at which the key is pressed, the time during this time is associated with the count value of the clock pulse. FIG. 12 shows an example of this. When a press key is pressed, the binary counter 111 is first reset by the key-off (break) circuit 110, and then the FF 112 is set. This set output signal is supplied to AND gate 113 and also to AND gate 114. Therefore, the clock pulse from AND gate 113
₀ is output, and the binary counter 111 counts the number. At the time of make, the AND gate 114 is opened by the output signal of the key-on (make) circuit 115 and the
Reset FF112. Therefore, the count value during the set output period of the FF 112, that is, from break to make, is obtained, and the count value is sent to the volume control value creation control section 17 from the AND circuit 117 to which the output of the AND gate 114 is applied as a gate signal. The output of the key-on circuit 115 is clear circuit 1 in FIG.
3-16, and the output of the key release detection circuit 118 when the key after making is released is applied as a key-off signal to the AND gate 12-30 in FIG. After all, different volume control values can be obtained from the binary counter 111 depending on the pressing speed of the pressed key. In the embodiment described above, the command signal of the timing operation key 18 for specifying each storage area of the selected musical tone memory 7 was not stored, but it is of course possible to specify this automatically during automatic performance. The information may be stored as a binary code. In addition, two types of pitch code data and tone length (time) code data are available.
One code data is stored in the RAM 11, and the volume control value is stored in another volume control value memory 17-1, but it goes without saying that all of this may be stored in one RAM, and the musical tone designation information Of course. Furthermore, the volume control values a to d are supplied to the musical tone generator 5, and are used to perform various volume controls such as varying the amplitude value of the volume envelope specified in the selected musical tone memory 7, or varying the absolute volume. It includes the means. In addition, the performance memory 11 is
The storage device is not limited to RAM, but may be other storage devices such as magnetic tape or magnetic card. In addition, it goes without saying that the storage method for the performance memory 11 and the circuit configuration of each part are not limited to the embodiments, and can be modified in various ways without departing from the gist of the present invention. As described in detail above, the present invention first inputs and stores a pitch, and then reads out the pitch while adding performance information such as a desired length, timbre, volume, etc., and generates a sound.
By recording such performance information, you can express your own thoughts as they are, making it possible to create an effective electronic musical instrument with unprecedented variety. Therefore, it can be widely used even by people who cannot read musical scores very well or who cannot play musical instruments.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of the configuration of an electronic musical instrument according to the present invention, FIGS. 2 and 3 are diagrams explaining the performance memory of FIG. 1, and FIG. 4 is a detailed diagram of the time creation control section of FIG. 1. , FIG. 5 is an explanatory diagram of FIG. 4, FIG. 6 is a layout diagram of the timing operation keys of FIG. 1, FIG. 7 is a detailed diagram of the key distribution circuit of FIG. 1, and FIG. 8 is an explanatory diagram of FIG. Detailed view of the performance control section, FIG. 9 is a state explanatory diagram for pitch input in FIG. 8, FIG. 10 is a state explanatory diagram for time input in FIG. 8, and FIG. Other embodiments of the timing key in the figure and FIG.
FIG. 3 is a diagram illustrating a volume control value creation circuit when the timing operation keys shown in the figure are used. 1... Musical tone control section, 2... Performance control section, 3...
Keyboard, 4...Key input control section, 5...Musical tone generation section, 6...Musical tone memory, 7...Selected musical tone memory,
10...Speaker, 11...Performance memory, 12...
...Memory input/output control unit, 13...Timing input/output control unit, 14...Time creation control unit, 15...Instruction control unit, 16...Key distribution circuit, 17...Volume control value generation circuit, 18... timing operation key,
K...Pitch input mode key, I...Inhibit key, S...Automatic performance start key, E...End key, C...Clear key.

Claims (1)

[Scope of Claims] 1. A plurality of performance keys corresponding to each scale, at least one timing key, a performance information storage means that can be written and read, and by successive selective operations of the plurality of performance keys. a first input control means for storing a series of pitch information in the performance information storage means in advance; and after inputting and storing the series of pitch information in the performance information storage means by the first input control means;
By operating the timing key, the pitch information is read out from the performance information storage means to instruct to generate musical tones of the corresponding scale, and each tone length information corresponding to the series of pitch information is read out from the performance information storage means. An electronic musical instrument comprising: second input control means for inputting performance information obtained by measuring timing key operation time to the performance information storage means. 2. The second input control means includes: an output means for outputting a reference clock; and a calculation means for calculating the operation time of the timing key based on the reference clock output from the output means, 2. The electronic musical instrument according to claim 1, wherein the note length information is obtained from an output of a calculation means. 3. A plurality of performance keys corresponding to each scale, a plurality of timing keys each specifying a different volume or timbre, a performance information storage means capable of writing and reading, and a continuous selective operation of the plurality of performance keys. a first input control means for storing a series of pitch information in the performance information storage means in advance; and after inputting and storing the series of pitch information in the performance information storage means by the first input control means;
By selectively manipulating the plurality of timing keys, the pitch information is read out from the performance information storage means and an instruction is given to generate musical tones of the corresponding scale with the relevant volume or timbre, and the series of tones is an electronic device comprising: second input control means for obtaining respective note length information corresponding to high information by measuring the operation time of the timing key and inputting the obtained note length information to the performance information storage means; musical instrument. 4. The second input control means sends control information indicating the volume or timbre specified by the selective operation of the plurality of timing keys to the performance information storage means in correspondence with the series of pitch information. 4. The electronic musical instrument according to claim 3, further comprising means for storing information. 5. The second input control means includes: an output means for outputting a reference clock; and a calculation means for calculating the operation time of the timing key based on the reference clock output from the output means, 5. The electronic musical instrument according to claim 3, wherein the note length information is obtained from the output of a calculation means. 6 A plurality of performance keys corresponding to each scale are arranged in a matrix consisting of a plurality of columns and a plurality of rows, and one of the columns or the rows specifies a different volume, and the other one specifies a different volume. A plurality of timing keys that specify different tones; and volume control information indicating the corresponding volume based on the column and row to which the operated timing key belongs in accordance with the selective operation of the plurality of timing keys;
control information generating means for generating timbre control information indicating a corresponding timbre; performance information storage means capable of writing and reading; and a series of pitch information generated by successive selective operations of the plurality of performance keys. a first input control means for storing the series of pitch information in the performance information storage means in advance; and after inputting and storing the series of pitch information in the performance information storage means by the first input control means;
By selectively operating the plurality of timing keys, the pitch information is read from the performance information storage means, and a musical tone of a corresponding scale is determined by the volume control information generated by the control information generation means. It instructs the timing key to generate sound volume and a tone determined by the tone control information generated by the control information generating means, and to set each tone length information corresponding to the series of pitch information to the timing key. An electronic musical instrument comprising: second input control means for inputting performance information obtained by measuring operation time to the performance information storage means. 7. The second input control means selectively operates the plurality of timing keys to cause the performance information storage means to input the volume control information and the volume control information generated from the control information generation means using the timing keys. 7. The electronic musical instrument according to claim 6, further comprising means for storing at least one of the timbre control information in correspondence with the series of pitch information. 8. The second input control means includes: an output means for outputting a reference clock; and a calculation means for calculating the operation time of the timing key based on the reference clock output from the output means, 8. The electronic musical instrument according to claim 6, wherein the note length information is obtained from an output of a calculation means. 9 A plurality of performance keys corresponding to each scale, at least one timing key consisting of a press key switch that makes after a break, and measuring the time from the break to the make due to the press operation of the timing key, and measuring the pressing speed. a pressing speed detecting means for obtaining pressing speed information shown in FIG. a first input control means for inputting and storing the series of pitch information in the performance information storage means by the first input control means;
Instructing to read the pitch information from the performance information storage means by operating the timing key and generate a musical tone of the corresponding scale at a volume based on the pressing speed information generated from the pressing speed detecting means. and second input control means for obtaining respective note length information corresponding to the series of pitch information by measuring the time of operation of the timing key and inputting the obtained note length information to the performance information storage means. An electronic musical instrument characterized by 10 The second input control means uses the pressing speed information generated from the pressing speed detecting means by the pressing operation of the timing key as control information for controlling the volume, and controls the performance in correspondence with the series of pitch information. 10. The electronic musical instrument according to claim 9, further comprising means for storing information in the information storage means. 11. The second input control means includes: an output means for outputting a reference clock; and a calculation means for calculating the operation time of the timing key based on the reference clock output from the output means, 11. The electronic musical instrument according to claim 9 or 10, wherein the note length information is obtained from an output of a calculation means.