JPH0193286A - Video signal converter - Google Patents

Abstract

PURPOSE:To convert a video signal having jitter component such as a VTR into an NTSC signal not including jitter component used for broadcast by applying A/D conversion once to a nonstandard video signal, applying various digital processings and outputting the result as the standard video signal through D/A conversion. CONSTITUTION:An inputted nonstandard video signal 1 is converted into a digital signal by an A/D converter 2 and separated into a luminance Y signal and a chrominance C signal by a Y/C separation circuit 3, the Y signal is inputted directly to a time axis correction circuit 5, and the C signal is demodulated into s R-Y signal and a B-Y signal by a color demodulation circuit 4 and the result is inputted. The time axis correction circuit 5 consists of a time axis correction memory 5A and memory controllers 5B, 8 and the memory 5A applies independent write/readout asynchronously. That is, the 910fM clock having a frequency of 4fsc inputted to the memory controller 5B is used for the write and the 4fsc clock synchronously with a color burst is used for readout. The Y signal, R-Y signal and B-Y signal via the time axis correction circuit 5 are formed into an NTSC signal form by an NTSC encoder 6 and a standard video signal 8 is outputted by the D/A converter 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus for converting an NTSC signal containing a jitter component, such as the output of a VTR, into an NTSC signal containing no jitter component used for broadcasting.

[Conventional technology]

Color television receivers using digital signal processing technology are increasingly being used as digital AV equipment, including VTRs and other media. In this case, the video signal may differ from the NTSC signal (hereinafter referred to as standard video signal) used for broadcasting. In VTRs, the color subcarrier is not synchronized with the horizontal synchronization signal, which causes various problems. Furthermore, in cases where the signal itself contains jitter, such as with a VTR, digital processing is performed using a clock phase-locked to the horizontal synchronization signal as the system clock, so the jitter contained in the input signal appears on the screen. . For example, in high-definition digital television receivers that improve the characteristics of conventional color television receivers, the signal processing clock is phase-locked to the horizontal synchronization signal when converting the number of scanning lines from inclace scanning to non-interlace scanning. Since a clock is used, jitter occurs on the screen, degrading the image quality.

[Problem that the invention seeks to solve]

As described above, if a high-definition digital television receiver converts an input non-standard video signal into a standard video signal, it can be adapted to any input, making it extremely versatile.

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a conversion device that converts a non-standard video signal such as that of a VTR into a standard video signal.

[Means for solving problems]

The device of the present invention A/D converts a non-standard input video signal, and after Y/C separation, converts the Y signal and the color difference (R-Y, m-y) signal obtained by color demodulating the C signal into a time signal. Input the Y signal two color difference signals that have been time axis corrected into the axis correction circuit and convert them into NTS
Input to C encoder to convert into NTSC signal format, D/
This is a device that outputs a standard video signal after A conversion.

The time axis correction circuit in the device writes the input Y signal 9 color difference signals to the time axis correction memory using a clock that is phase-locked to the horizontal synchronization signal that is synchronously separated from the input video signal, and locks the phase to the color subcarrier. It is designed to read and output using the clock.

[Effect]

As will be described in detail in the embodiment, the write clock of the time base correction memory of the time base correction circuit is a 9 10 fn clock (fH: frequency of the horizontal synchronization signal) phase-locked to the horizontal synchronization signal. Using this clock, the Y signal and color difference signal are written to the time axis correction memory at 4 fsc (fsc:
If the signal is read out using the clock of 4 fsc (color subcarrier frequency), sample points (dots) of the video signal can be obtained in synchronization with the 4 fsc clock.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit block diagram, in which the upper part shows a part that performs a series of signal processing, and the lower part shows a clock generation part.

First, the clock generation part will be explained.

Two clock systems are generated: a clock whose phase is locked to the horizontal synchronization signal, and a clock whose phase is locked to the color burst. A non-standard video signal 1, which is an input to this device, is input to a sync separation circuit 9, where a horizontal sync signal is separated and input to a PLL circuit 10. The PLL circuit 10 generates pulses that are phase-locked to the horizontal synchronizing signal, and the clock generation circuit 13 generates clock pulses of a predetermined frequency. 91Of+clock of this series is 4f3
The clock has a frequency of c, but in order to indicate that it is synchronized with the horizontal synchronizing signal, the display corresponds to the number of dots in one scanning line.

The input non-standard video signal 1 is also input to the APC circuit 11
, a color subcarrier synchronized with the color burst is generated, which is converted into a pulse by the PLL circuit 12, and is output to the clock generation circuit 1.
3, a 4fsc black signal synchronized with the color burst is generated. Further, the color subcarrier generated by the APC circuit 11 is converted into a digital signal by the A/D converter 14, and used for multiplication in the color demodulation circuit 4, which will be described later.

Next, the portion in the upper part of FIG. 1 that performs signal processing will be explained. The input non-standard video signal 1 is converted into a digital signal by the A/D converter 2, and the Y/C separation circuit 3 converts the brightness (
The Y) signal is separated into one color (C) signal, and the Y signal is directly input to the time axis correction circuit 5, and the C signal is input to the color demodulation circuit 4.
RY signal.

It is input after demodulating into a B-Y signal. RY signal.

The B-Y signals are time-division multiplexed. A/D converter 2
．． 14. The clock in Y/C separation circuit 3 is 910
fH clock. Here, the color demodulation circuit 4 receives the digital color subcarrier which is the output 14a of the A/D converter 14, and the C
This is a demodulation circuit that multiplies signals.

The time axis correction circuit 5 includes a time axis correction memory 5A and a memory controller 5B, and writing and reading of the time axis correction memory 5A are performed independently and asynchronously. That is, writing is performed using a 910 fM clock input to the memory controller 5B, and reading is performed using a 4 fsc clock. The Y signal and color difference (R-Y, B-Y) signals with shifters are aligned in phase with this writing, and 4f5. By reading with the clock, Y
, R-Y.

Jitter components included in each signal B-Y are absorbed.

The Y signal, R-Y signal, and B-Y signal that have passed through the time axis correction circuit 5 in this way are input to the NTSC encoder 6, and the NTSC
The D/A converter 7 outputs it as a standard video signal 8 which is an analog signal.

〔Effect of the invention〕

As explained above, in the present invention, a non-standard video signal is once A/D converted, various digital processing is performed, and then D/A converted again and outputted as a standard video signal. For the non-standard video signal, after Y/C separation, the C signal is demodulated into an RY signal and a BY signal, and the time axis is corrected together with the Y signal in a time axis correction circuit. The clock written to the correction memory is 91 synchronized with the horizontal synchronization signal.
This is a 0fN clock, and reading is performed using a 4fsc clock synchronized with the color burst. All dots on the horizontal scan line are therefore synchronized to the color subcarrier. VTR
This circuit absorbs the jitter even in video signals with a lot of jitter. Furthermore, the output signal that passes through this device is different from the original human input signal, and the video signal and synchronization signal are completely synchronized, so it can be used before a receiver that performs scan line conversion, such as a high-definition digital television receiver. By intervening this device, there will be no problem with the scanning line conversion, and the circuit configuration of the scanning line conversion section will be simplified.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of an embodiment of the present invention. 2.14--A/D converter, 3-Y/C separation circuit, 4--color demodulation circuit, 5-
Time axis correction circuit, 6...-NTSC encoder, 7-D
/ A converter, 9 - synchronous separation circuit, 11-A P
C circuit, 10.12-・PL, L circuit, 13-
Clock generation circuit.

Claims (1)

[Claims] After A/D conversion of a non-standard input video signal and Y/C separation,
The color difference (R-Y,
B-Y) signal is input to the time axis correction circuit, and the time axis corrected Y signal and color difference signal are input to the NTSC encoder to form an NTSC signal, and after D/A conversion, output as a standard video signal. The time axis correction circuit writes the input Y signal and the color difference signal to the time axis correction memory using a clock phase-locked to a horizontal synchronization signal that is synchronously separated from the input video signal, and writes the input Y signal and color difference signal into the time axis correction memory. 1. A video signal converting device for converting a non-standard video signal into a standard video signal, the device reading and outputting using a clock phase-locked to a standard video signal.