JPH0192134U - - Google Patents
Info
- Publication number
- JPH0192134U JPH0192134U JP18644687U JP18644687U JPH0192134U JP H0192134 U JPH0192134 U JP H0192134U JP 18644687 U JP18644687 U JP 18644687U JP 18644687 U JP18644687 U JP 18644687U JP H0192134 U JPH0192134 U JP H0192134U
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- semiconductor
- semiconductor device
- bump
- semiconductor chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の半導体装置の一部破断斜視図
、第２図は従来の半導体チツプの組立状態を示す
一部破断斜視図、第３図は従来の他の半導体チツ
プの組立状態を示す一部破断斜視図である。
２１……第１の半導体チツプ、２２……第２の
半導体チツプ、２３……接着剤層、２４……バン
プ、２５……ボンデイングパツド、２６，２７…
…リード、２８……金属ワイヤ、２９……パツケ
ージ。
Fig. 1 is a partially cutaway perspective view of the semiconductor device of the present invention, Fig. 2 is a partially cutaway perspective view showing the assembled state of a conventional semiconductor chip, and Fig. 3 shows the assembled state of another conventional semiconductor chip. It is a partially cutaway perspective view. 21... First semiconductor chip, 22... Second semiconductor chip, 23... Adhesive layer, 24... Bump, 25... Bonding pad, 26, 27...
...Lead, 28...Metal wire, 29...Package.
Claims (1)
状態で複数の半導体チツプをマウントするように
したことを特徴とする半導体装置。 (2) 前記裏面を接する一方の半導体チツプをバ
ンプ構造となし、該バンプによるフエイスボンデ
イングを行い、他方の半導体チツプにボンデイン
グパツドを設け、ワイヤによるボンデイングを行
うようにしたことを特徴とする実用新案登録請求
の範囲第１項記載の半導体装置。[Claims for Utility Model Registration] (1) A semiconductor device characterized in that a plurality of semiconductor chips are mounted in the same package with their back surfaces adhered to each other. (2) A practical use characterized in that one of the semiconductor chips in contact with the back surface has a bump structure, and face bonding is performed using the bump, and the other semiconductor chip is provided with a bonding pad, and bonding is performed using a wire. A semiconductor device according to claim 1 of patent registration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18644687U JPH0192134U (en) | 1987-12-09 | 1987-12-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18644687U JPH0192134U (en) | 1987-12-09 | 1987-12-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0192134U true JPH0192134U (en) | 1989-06-16 |
Family
ID=31477674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18644687U Pending JPH0192134U (en) | 1987-12-09 | 1987-12-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0192134U (en) |
-
1987
- 1987-12-09 JP JP18644687U patent/JPH0192134U/ja active Pending