JPH0191467A - Thin film transistor substrate - Google Patents

Abstract

PURPOSE:To improve manufacturing yield, by forming a part or the whole part of a source line, a source electrode and a drain electrode, of two or more kinds of conducting layers, and making up the upper side conducting layer of the two or more conducting layers, in a pattern form smaller than the lower side conducting layer. CONSTITUTION:A part of the whole part of a source line 6'', source electrodes 6, 6', drain electrodes 7, 7' are formed of two or more conducting layers. The upper side conducting layer of the two or more conducting layers has a pattern form smaller than the conducting layer of the lower side. In a two-layer structure of the source electrodes 6, 6' and drain electrodes 7, 7' of a thin film transistor(TFT), the pattern size of the first layer electrodes 6', 7' is larger than the electrodes of the second layer. Therefore, even after a plurality of manufacturing processes of photolithography, the channel size or the like of the TFT is not affected by the deviation of patterns, and defects like disconnection of patterns scarcely occur on account of two-layer structure. Therefore completing a manufacturing process of high yield.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a thin film transistor substrate.

[Prior Art] Recently, flat displays have been actively developed to realize office automation equipment terminals, portable televisions, and the like. In order to achieve this, a so-called active matrix method is becoming popular, in which a thin film active element is arranged near the electrodes in a liquid crystal display element in which a plurality of liquid crystal display pixel electrodes are arranged, thereby driving the liquid crystal close to static drive. has been developed. Various proposals have been made regarding the structure, materials, etc. of thin film active elements used for such purposes, and their advantages and disadvantages are being discussed. Among these, research on thin film transistors that have the potential for video display is actively being conducted. FIG. 2 shows a cross-sectional view of a conventionally well-known thin film transistor (hereinafter referred to as TPT) having an inverted stagger structure. 21 is a transparent insulating substrate made of glass or the like, 22 is ITO, and 23 is Sn.
A gate line that also serves as a display pixel electrode and a transistor gate electrode formed of a transparent conductive thin film such as O□;
24 is a gate insulating film, 25 is a semiconductor layer, 26 is a source electrode, and 27 is a drain electrode.

Conventionally, when creating a transistor with such a structure, the gate electrode, the source electrode 26, and the drain electrode 27 are
Since each of these is formed by a single photolithography process, wire breaks were observed due to adhesion of foreign matter and dust during the manufacturing process, contact during substrate transportation, etc. When such a wire break on the substrate side is viewed as a liquid crystal display element, a signal does not propagate beyond the wire break, causing a line defect. Conventionally, as a countermeasure to this problem, as shown in Figure 3, wiring is constructed from multiple conductive layers, and each layer is patterned using multiple photolithography processes using the same pattern. It is considered that it will be dealt with. The part indicated by the first layer source electrode 26 and the first layer drain electrode 27 in Figure 3 is 2
The first layer of layer wiring is shown.

This shows a state in which the first layer electrode and the second layer electrode are formed in a pattern of the same size.

[Problems to be Solved by the Invention] A TPT in which the source and drain electrodes as described above are constituted by a plurality of conductive materials and is formed by a plurality of photolithography steps has a structural problem. When creating a pattern with the narrowest line width, it is almost impossible to completely overlap the patterns when using the same pattern again to pattern the narrowest part, so it is necessary to repeat multiple photolithography processes. Pattern deviation occurs. This not only changes the essential physical quantity such as the channel size of the thin film transistor, but also requires the mask to be designed with pattern misalignment in mind, resulting in a decrease in aperture ratio and an increase in interelectrode capacitance. This results in a deterioration in display quality. Furthermore, if such a design is not used, it may cause defects such as short circuit between the source electrode and the train electrode.

In this case, even if line defects due to wire breakage can be prevented, new defects will occur, and the manufacturing yield will not be improved, compared to the conventional simple matrix type display element. This does not lead to solving the problem of high manufacturing costs. An object of the present invention is to solve the above-mentioned problems of the prior art and to complete a high-yield manufacturing process.

[Means for Solving the Problems] The present invention has been made to solve the above-mentioned problems, and includes arranging pixel electrodes in rows and columns on an insulating substrate, and thin film transistors near the intersections of the electrodes. In the thin film transistor substrate, a part or all of the source line, the source electrode, and the drain electrode are formed from two or more types of conductive layers, and the upper conductive layer of the two or more types of conductive layers is lower than the two or more types of conductive layers. The present invention provides a thin film transistor substrate characterized by having a pattern shape smaller than that of a conductive layer on the side thereof.

Hereinafter, the present invention will be explained in detail with reference to the drawings. Figure 1 is a basic configuration diagram of the present invention, and (b) in Figure 1 (
1 is a cross-sectional view of plane AA'' of the plan view shown in a). 1 is a transparent insulating substrate, 2 is a gate electrode, 3 is an interlayer insulating film and gate insulating film (hereinafter simply referred to as gate insulating film), and 4 is a semiconductor layer. , 5 is a contact formation layer provided for the purpose of converting the nonlinear characteristics at the junction to linear characteristics and improving electrical characteristics such as suppressing current when off. 6° is the first layer source electrode, 6
is the second layer source electrode (hereinafter referred to as the first layer source electrode 6°)
and the 2Nth source electrode may be collectively referred to as source electrode 6+6'. ), the source electrode 6+6° is connected to a source line 6'' connecting the source electrodes of a plurality of TPTs arranged in a row.

7° is the first layer drain electrode, and 7 is the second layer train electrode (hereinafter, the first layer drain electrode 7° and the second layer drain electrode 7 may be collectively referred to as drain electrode 7+7°). ).

A pixel electrode 8 is connected to the drain electrode 7+7° and is used to apply a voltage from the drain electrode 7+7° to the liquid crystal layer. 9 is an end face of the source electrode 6+6°, and 10 is an end face of the drain electrode 7+7°.

Further, C is the distance between the first layer source electrode 6'' and the first layer drain electrode 7°, and represents the channel size that determines the characteristics of the transistor.

The insulating substrate 1 can be made of glass, synthetic resin, etc., and the gate electrode 2 can be made of metal such as Al or Cr. The interlayer insulating film/gate insulating film 3 is SiN.

5iON, Sin, TaO5, etc. can be used and can be selected depending on the required TPT characteristics. The semiconductor layer 4 is made of polycrystalline silicon, amorphous silicon (a-3i
) etc., but the contact forming layer 5 is generally used in the form of ``a-3i''.

The structure of the present invention shown in FIG. 1 has an inverted stagger structure,
A first-layer source electrode 6' and a first-layer drain electrode 7' are formed on the semiconductor layer and the gate insulating film 3, and the pattern shape is smaller than that of the electrode 6° above the first-layer source electrode 6°. The second layer source electrode 6 is connected to the first layer train electrode 7.
A second layer source electrode 7 having a smaller pattern shape than the electrode 7° above is formed.

By adopting such a structure, even if a pattern shift occurs in the multiple photolithography steps for forming the multilayer structure described above, the pattern of the source electrode 6 in the second layer will be different from that in the first layer. source electrode 6'
If the pattern of the drain electrode 7 in the second layer does not protrude from the pattern of the train electrode 7 in the first layer, the deviation will not affect the channel size L.

In addition, at least one of the two or more types of conductive layers is made of metal or a metal compound, so that when a signal input from the outside is propagated to the TPT arranged in each pixel, the resistance component inherent to the wiring part is This is desirable from the viewpoint of preventing signal delay and signal waveform blunting. It is desirable that the metal or metal compound used at this time has as low a resistivity as possible.

The material of the first layer source electrode 6' and the first layer drain electrode can be a high melting point metal such as Cr, Mo, Ti, W, etc. or a high melting point metal silicide, etc. These metals are a semiconductor layer made of a silicon-based compound. It is desirable to add a function to prevent deterioration of the electrode structure due to interdiffusion between the wiring metal and the second layer wiring metal. Preferably, it is formed from silicide. The material of the second layer of metal is mainly a low-resistance metal, and is made of a material that allows signals input from an external circuit to be input to the thin film transistor formed for each pixel without delay. It is desirable to take For this purpose, low resistance Cu,
Ag.

Although Au, A1, etc. can be used, it is preferable to use Al in consideration of process consistency.

Also, the difference in dimension between the 1st layer and 2H patterns is 0.4~
A thickness of about 4 μm is desirable, and a range of 1.5 to 2 μm is particularly desirable.

Although the source and drain electrodes are described as having a two-layer structure, they can also be put into practical use with a structure of two or more layers. In this case, the pattern of the lower electrode layer The dimensions of the pattern of the upper electrode layer formed are always the same or small.

Therefore, if the dimensional accuracy of multiple photolithography processes is kept within the range that affects the channel size L, products with uniform characteristics can be manufactured, and the patterning reproducibility of the mechanical equipment in the photolithography process can be improved. In this case, dimensional accuracy can be reduced compared to manufacturing the conventional multilayer structure shown in FIG.

In addition, the contact formation layer 5 and the IN-th source electrode 6°,
The drain electrode 7° of the first layer can be formed with the same pattern in one patterning process, and it is possible to eliminate pattern misalignment, but if it is formed separately in two patterning processes, the contact formation layer The dimensions of the pattern No. 5 may be made somewhat larger than the dimensions of the picture electrode pattern.

Although not shown in FIG. 1, in the case of a TPT having the structure shown in FIG. By providing a light shielding layer to prevent
Although methods for preventing such an increase in off-state current are known, the structure of the present invention is very effective in this case as well, and will be explained below.

5 and 6 show cross-sectional views in which a light shielding layer M11 is formed on the semiconductor layer 4. FIG. 5 shows the conventional structure, and FIG. 6 shows the structure of the present invention. 12 is an insulating layer.

The light-shielding layer 11 is formed on the semiconductor layer 4 to prevent light from hitting the semiconductor layer 4, but the material of the light-shielding layer needs to be controlled to a certain potential to prevent the characteristics of the thin film transistor from drifting. There is. For this reason, since they are generally conductive metals, the end surfaces 9 and 10 of the source electrode 616' and the drain electrode 7+7' facing the light shielding layer 11 are short-circuited between the picture electrodes and the light shielding layer 11. In order to prevent this, it is necessary to provide the insulating layer 12.

Such an insulating layer 12 is a conventional source electrode 6+6° as shown in FIG. 12 has become thinner (because there is a large difference in level),
The source electrode 6+6° and the drain electrode 7+7° are the light shielding layer 1
1 has the disadvantage that there is a high risk of short circuit. However, as shown in FIG. 6, in the structure of the present invention, the end surfaces 9 and 10 are stair-like (that is, the second layer is set back from the first layer in the length direction of the channel size L). ), the problems mentioned above are less likely to occur.

Also, as mentioned above, as to whether or not the total film thickness will become thicker due to multi-layering, the total wiring resistance should be set to the design value, so the film thickness can be set to the required value at that time. Therefore, even if multilayer wiring is used, the film thickness will not increase proportionally.

It is also effective for the source line 6'' to adopt the two-layer structure of the present invention described above for the same reason.

Although the above description is about the inverted staggered structure TPT, the method of the present invention is not limited to the inverted staggered structure. For example, in the case of a TPT having a coplanar structure as shown in FIG. 4, the source electrode 6+6° and the drain electrode 7+7' are made into a two-layer structure, and the end face 9.0 shown in FIG.
When the second layer electrode and the first layer electrode have a stepped structure as in IO, the insulation state between the gate electrode 2 and the gate electrode 2 formed through the gate electrode 24 is as shown in FIG. It is clear that this method is effective for ensuring reliability for the reasons shown in , preventing electrical short circuits between the gate electrode 2 and the source electrode 6,66° or the train electrode 7+7°, and preventing the occurrence of defects. It is.

The structure of each TPT of the present invention is as described above, but as a flat display, display pixel electrodes such as liquid crystal are arranged in matrix on an insulating substrate, and the TPT is arranged near the intersection of these electrodes. This results in liquid crystal driving that is close to static driving (so-called active matrix method).

[Function] In the two-layer structure of the source electrode and drain electrode of the TFT of the present invention, the pattern size of the first layer electrode is larger than that of the second layer electrode, so even after multiple photolithography manufacturing steps, TPT due to pattern deviation
It does not affect the channel size, etc., and defects such as pattern breakage are less likely to occur due to the two-layer structure. In addition, because of the above structure, the end faces of the IN and second layers are on steps, so even if such end faces are covered with an insulating layer, the insulating layer does not become thinner because there is no sudden step difference, which may cause short circuits. less likely to occur.

[Example] Glass substrate 10 having 10,000 transistors having the structure shown in FIG. 1 with a light shielding layer 11 added as shown in FIG. 6
A transistor with a conventional structure was fabricated, and electrical characteristics and defect occurrence conditions were compared with those of a transistor with a conventional structure. 1,000 Cr was deposited on the glass substrate and patterned to form a pattern that served as a gate electrode and a gate line. Next, using a plasma CVD method, a 5iON film as a gate insulating film, an a-Si layer as a semiconductor layer, and a contact M for improving junction characteristics are formed.
Three i-layers were successively deposited. The thickness of each layer at this time is 2,500, 1,500, and 1,000, respectively. After that, the n''a-3i layer and the a-Si layer were patterned into island shapes to form a semiconductor layer. 1
000 people, and then the second layer of source electrode and the second layer of drain electrode were deposited using AI to a film thickness of 30 mm.
00 people were used for vapor deposition. Subsequently, the second electrode and the first layer electrode were successively patterned.

As in the structure of the present invention, the pattern of the IN-th electrode is larger than the pattern of the second layer electrode. Although the TPT was completed through the above process, in order to confirm the significance of the structure obtained by the method of the present invention, the upper side of the source electrode, semiconductor layer, and drain electrode of the TPT was formed by plasma CVD method as shown in FIG. A 5iON film of 4,000 layers was formed as an insulating film, and a light-shielding layer made of material AI was further formed on top thereof by vapor deposition.

On the other hand, for comparison with the structure of the present invention, the TPT described above
The patterns of the first layer source electrode and the second layer source electrode have the same dimensions, and the first layer drain electrode and 2N
This is a structure in which the dimensions of the drain electrode patterns are the same, and all other conditions such as material and film thickness are the same.
Ten glass substrates with 10,000 PTs (ie, conventional type) were made. Then, the state of occurrence of the defects was compared.

First, when comparing defects, for the 10 glass substrates of the present invention, not a single short circuit between the source electrode, drain electrode, and light shielding layer was observed among the 10,000 TPTs. In the 10 glass substrates prepared by the conventional method, 2 to 3 short-circuit points were observed among the 10,000 TPTs on each substrate. At the same time, we also compared transistor characteristics, and found almost no difference in basic static characteristics.Furthermore, in the substrate according to the present invention, there was a tendency for the in-plane distribution of differences in individual transistor characteristics to become smaller. It was confirmed that the method of the present invention can prevent the occurrence of defects without affecting the transistor characteristics.

[Effects of the Invention] As described above, according to the structure of the present invention, it is possible to remove structural defects that would otherwise occur in conventional methods without changing transistor characteristics. . In the method of the present invention, the number of photolithography steps in the manufacturing process increases, but if a line defect occurs due to a disconnection or a short circuit between the light shielding layer and the source electrode or source line, the substrate Therefore, it is considered that the present invention makes a large contribution to reducing the manufacturing cost of thin film transistor substrates.

By adopting the TPT structure according to the present invention, it is possible to solve the problem that the manufacturing cost of active matrix type liquid crystal display elements is higher than that of conventionally used simple matrix type liquid crystal display elements. This will greatly contribute to the practical application of the technology.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 1(a) is its plan view, and FIG. 1(b) is its AA
' is a cross-sectional view of the plane. FIG. 2 is a cross-sectional view of a conventional TPT having an inverted staggered structure, FIG. 3 is a cross-sectional view of the TPT shown in FIG. 2 with a two-layer structure, and FIG. A cross-sectional view of a Cobrana type TFT having
FIG. 5 is a cross-sectional view of a conventional TPT having a two-layer electrode with an insulating layer formed on the semiconductor layer, and FIG. 6 is a cross-sectional view of a TPT having the structure of the present invention with an insulating layer formed on the semiconductor layer. A1: Insulating substrate 2: Gate electrode 3: Interlayer insulating film and gate insulating film 4: Semiconductor layer 5: Contact formation layer 6', 26°: First layer source electrode 6.26: Second layer source electrode 6 ”: Source line 7°, 27°: 1st layer drain electrode 7.27: 2nd layer drain electrode 8: Pixel electrode 9.10: End surface 11: Light shielding layer 12: Insulating layer L: Channel size A 1 8-A' cross section N 2 Figure M4L tag purchase 5 Figure ¥ 6 10

Claims (1)

[Claims] 1. In a thin film transistor substrate in which a plurality of pixel electrodes are arranged on an insulating substrate and a thin film transistor is arranged near the pixel electrodes, part or all of the source line, the source electrode, and the drain electrode are provided. A thin film transistor substrate is formed of two or more types of conductive layers, and an upper conductive layer of the two or more types of conductive layers has a smaller pattern shape than a lower conductive layer. 2. Among the two or more types of conductive layers constituting the source and drain electrodes of each thin film transistor near the plurality of electrodes, the pattern of the upper conductive layer is on the lower side in the length direction of the channel. 2. The thin film transistor substrate according to claim 1, wherein the thin film transistor substrate has a shape that is recessed from the conductive layer.