JPH0191463A - High breakdown voltage semiconductor element and its manufacture - Google Patents

Abstract

PURPOSE:To increase breakdown voltage, and enable process reduction, by forming a recessed part from the top surface of an semiconductor element to a P-N junction by etching, and making up a constitution wherein the surface of the P-N junction is exposed in the recessed part. CONSTITUTION:A constitution is made up wherein, by etching, a recessed part 10 is formed from the surface of a semiconductor element to a P-N junction, and the surface of the P-N junction is exposed in the recessed part 10. Since the recessed part 10 is formed by etching, the surface of the P-N junction to obtain forward direction breakdown voltage is smooth, and contamination also is little, so that high breakdown voltage is obtained. Since the recessed part 10 can be formed by an etching process to make ohmic contact between a gate region 4 and a gate electrode 8, a forming process of a beveled structure for high breakdown voltage is saved. Therefore the number of manufacturing processes is decreased, and high breakdown voltage is obtained.

Description

[Detailed Description of the Invention] [Summary] In high-voltage transistors, the breakdown voltage is often determined by local breakdown due to the electric field at the pn junction surface. For this purpose, the pn junction surface has a bevel structure to provide a withstand voltage. However, using a bevel structure increases the number of manufacturing steps, and it is technically difficult to form the bevel structure with high precision, resulting in poor yield. Moreover, there was a problem of high cost.

For this reason, a recess is formed by etching from the surface of the semiconductor element to the pn junction, and the pn junction is constructed as a planar diode in which the surface of the junction appears only within the recess, thereby weakening the electric field at the junction surface and creating a high withstand voltage. (7).As a result, the bevel structure formation process is unnecessary,
In addition to reducing the number of steps and improving yield, the mass production effect also resulted in a reduction in h-strain.

[Industrial application field]

The present invention relates to a semiconductor device, and particularly to a breakdown voltage structure of a semiconductor device that requires a high breakdown voltage.

[Traditional technique]

In SiRisk and transistors that require high breakdown voltage, the breakdown voltage is often determined by local breakdown at the surface of the pn junction rather than breakdown inside the junction. When an overvoltage is applied to the pn junction, the electric field on the exposed pn junction surface becomes stronger, and when it exceeds a certain limit, local breakdown occurs, the electric field is concentrated, and the junction is destroyed. For this reason, pn
In order to weaken the electric field at the junction surface, the exposed pn junction is beveled, that is, the pn junction surface is beveled.

FIGS. 5A and 5B are cross-sectional views of PNP run risks 40 and 50, respectively, which have been beveled.

In the pnp transistor 40 shown in FIG.
groove 43. 43 is drilled, and the pn junction surface consisting of the emitter region 41 and the base region 42 is processed to have a positive bevel of 44.degree. 45. Note that the positive bevel is a structure in which a bevel is formed so that the area increases from the low concentration region side to the high concentration region side of carriers. Next, in the run risk 50 shown in FIG. Contrary to the positive bevel, the negative bevel has a structure in which the bevel is formed so that the area increases from the high carrier concentration region side to the low carrier concentration region side.

FIG. 6 is a diagram showing the relationship between the bevel angle and the maximum electric field on the pn junction surface when the pn junction surface is beveled. As shown in the figure, the electric field on the pn junction surface is maximum when the negative bevel is approximately 45°, so the negative bevel is approximately 45°.
In order to reduce the electric field strength on the pn junction surface with a bevel, the bevel angle must be set to 1° to 6°.

The bevel structure shown in FIGS. 5(a) and 5(b) is formed for each element after each element is cut from the wafer.

Below, the steps required to form the bevel structure will be briefly described.

(2) First, a surface protection step is performed in which a highly viscous resist film such as LTO (low temperature oxide film) or negative resist is applied to the element surface.

(2) Next, a sandblasting process is performed in which extremely fine sand is mixed with high-pressure gas and blown onto the element at a predetermined angle to form a beveled surface on the pn junction surface.

(2) Next, a step of cleaning the element contaminated by the sandblasting step is performed.

(2) Furthermore, chemical etching is performed to remove the damaged layer on the surface of the bevel formed by the sandblasting process (surface treatment process).

[Problem that the invention seeks to solve]

As mentioned above, conventionally, the pn junction surface was processed into a bevel shape in order to increase the withstand voltage. However, in the process of processing into a bevel shape, the sandblasting process,
The surface treatment process is a technically difficult process, and there is a problem that the yield is low.The sandblasting process for processing into a bevel structure and the surface treatment process are performed for each element after cutting each element from the wafer. The problem was that productivity was low.

SUMMARY OF THE INVENTION In view of the above conventional problems, it is an object of the present invention to provide a low-cost, high-voltage semiconductor device that can be manufactured with a small number of steps, has a high yield, and is highly effective in mass production, and a method for manufacturing the same.

[Means for solving problems]

In order to achieve the above object, the present invention provides a high breakdown voltage semiconductor element having a pn junction capable of obtaining forward breakdown voltage, and in which one of the semiconductor layers constituting the pn junction is made of Ga) 7B.
A recess is formed by etching from the surface of the high voltage semiconductor element to the pn junction, and the p-n junction is formed only within the recess.
It is characterized by a configuration in which the surface of the n-junction appears. Further, a gate 5, which is a semiconductor layer of a conductivity type opposite to that of the semiconductor substrate, is formed by diffusion in a semiconductor substrate of a conductivity type, and the gate layer and the semiconductor substrate constitute a pn junction that can obtain a forward breakdown voltage. In the method of manufacturing a high-voltage semiconductor device, the etching step includes a diffusion step of etching the gate layer, and an etching step of forming a recessed portion for connecting an electrode to the gate layer by etching. The method is characterized in that a recess is formed over the pn junction, and etching is performed so that the surface of the pn junction appears only within the recess.

[For production]

Since the recesses are formed by etching, the surface of the pn junction, which provides forward breakdown voltage, is smooth and has little contamination. Therefore, when a reverse bias is applied, the depletion layer spreads easily on the surface of the pn junction, the electric field on the surface of the pn junction can be weakened, and a high breakdown voltage can be obtained.

In addition, the fourth part is the ohmic contact between the gate region and the gate electrode.
Since it can be formed by an etching process for making contact, the number of manufacturing steps is reduced compared to the conventional method by omitting the bevel structure forming step, which was conventionally performed to achieve high breakdown voltage.

Therefore, the technically difficult process of forming a bevel structure is eliminated, the small grooves are increased, and productivity is improved. Also,
The ethoching process can be performed on all the elements on the wafer, so after cutting each element from the wafer as in the conventional method, a process to increase the voltage resistance such as a bevel structure formation process is performed for each element. is no longer needed, and a gas production effect can be obtained.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 (al to (C1) are a plan view, a front view, and a side view of a normally-on type electrostatic induction sink (hereinafter referred to as Sl risk) which is an embodiment of the present invention.

In the same figure (al to (C)), 2 has a thickness dl of 350
71 m of n″″ base 1, 3 is p with thickness d2 of 15 μm
+7 node region, 4 is a p+ agate region with a thickness d3 of 15 μm, 5 is an n- region with a thickness d4 of 13 μm, 6 is an n+ region, on the p+ region 3 is an anode electrode 7,
A gate electrode 8 is formed on the age-- region 4, and a cathode electrode 9 is formed on the n+ cathode region 6.

Further, an opening 10 for forming the gate electrode 8 on the p+ gate region 4 is provided in the 1:) portion outside the device, and the distance from the p+ gate region 4 to the outer end of the opening 10 is d5 is 750 μm. Note that the values of d1 to d5 can be freely set without being limited to the above example, and the thickness of the n-substrate 2 is exaggerated in the drawing.

As is well known, the normally-on type Sr silisc creates a forward bias voltage between the anode electrode 7 and the cathode electrode 9 by applying a reverse bias voltage (hereinafter referred to as VGk) between the gate electrode 8 and the cathode electrode 9. voltage (hereinafter referred to as VAK)
This is to prevent conduction between the anode electrode 7 and the cathode electrode 9 when the anode electrode 7 and the cathode electrode 9 are added. When attempting to increase the withstand voltage of the Sl silicon risk, the problem is how high the maximum blocking voltage can be when a forward voltage VAK is applied between the gate electrode 8 and the cathode electrode 9. At this time, p+
The pn junction composed of the gate region 4 and the n-substrate 2 is reverse biased, and the withstand voltage of the pn junction when reverse biased determines the maximum blocking voltage (hereinafter referred to as forward withstand voltage).

In the Sl silicon risk, in order to connect the p+ gate region 4 and the gate I- electrode 8 such as A1 at the end face,
The surface of the pn junction consisting of the p+ gate region 4 and the n"" substrate 2 is exposed. The reverse breakdown voltage of the pn junction is determined by the breakdown voltage based on the electric field concentration at the point of minimum curvature of the p+ agate region, the breakdown voltage at the junction surface, or until the so-called punch-through occurs when the depletion layer spreading in the n'' substrate reaches the anode region. It is determined by the minimum withstand voltage among the withstand voltages. Due to various factors such as the surface shape, the presence of ions, and contamination, the depletion layer at the junction surface area expands when biased in the reverse direction.
Breakdown is more likely than inside the joint. Therefore,
As mentioned above, in the past, the surface of the pn junction was processed into a bevel shape to weaken the electric field on the junction surface. In the Sl silicon risk according to the present invention, an opening IO is provided near the outer periphery by etching as shown in FIG. Since the pn junction surface is formed by etching, the degree of )η staining is small and smooth. Furthermore, since there is a highly doped n" cathode region at the outer edge, it becomes a pin junction of the p" nn layer and has a high breakdown voltage.

In this embodiment, the n+ cathode region 6 in the opening 10
P+ gate regions 4 to n are drilled to a depth of 13 μm from
The lateral distance to + region 6 was 750 μm. n-
The thickness of the substrate 2 is 350 μm%.The thickness of the p" anode region 3 is 15 μm, and the thickness of the P+ gate region 4 is 15 μm. Therefore, the linear distance from the p" gate region 4 to the P+ anode region 3 is 320 μm. , P+ gate region 4 to n
The distance in the lateral direction from one cathode region j or 6 is made larger than the straight line distance from the P+ gate region 4 to the P+ region 3. For this reason, nine layers of p+ gate region 4 and nine layers of n- substrate 2 are used.
Punch-through (expansion of the depletion layer in the n- substrate 2 to the P+ anode region 3 due to the reverse bias) when a reverse bias voltage is applied to the pn junction with the n-layer as the pn
Breakdown occurs within the joint before it occurs at the surface of the joint.

Next, FIGS. 2(a) to 2(C) show other embodiments in which the present invention is applied to Sl cyrisk. In FIG. 2(a) to (C), the same regions as in FIG. is covered with a passivation film 11 such as an oxide film, a nitride film, or a polyimide film, and even in this case, it is possible to increase the breakdown voltage of the pn junction surface when a forward voltage is applied to the P+ anode region 3 and the N+ cathode region 6. Further, FIG. 2(b) shows an example in which the present invention is applied to a Sl silicon risk having an anode short structure in which an n+ region 12 is provided between the P+ anode regions 3.Furthermore, FIG. The P+ gate region 13 at the end is diffused deeper than the inner P+ gate region 14 to form a guard ring, weakening the electric field concentration inside the junction and increasing the withstand voltage inside the n- substrate 2. In this way, the present invention is also applicable to the case where a guard ring is formed.

In addition, in FIG. 2 (al to (C)), the diameter d of the opening 10
is the straight line distance from P+ gate region 4 to P+ anode region 3! If it is larger than 1Sltl, bunch-through inside the pn junction occurs at a lower forward voltage than breakdown at the junction surface, so the forward breakdown voltage does not change even if the n+ region 6 is not provided at the outer end. Although not shown, the present invention can also be applied to Sl silices that have various combinations of pansivation coatings, anode short structures, and guard rings shown in FIGS. 2(a) to 2(C) above.

Next, FIG. 3 is a block diagram of a buried gate type GTO (gate turn-off thyristor) which is an embodiment of the present invention.

In the figure, 22 is an n-substrate which is an n-type semiconductor layer;
3 is a P+ anode region which is a P type semiconductor layer, 24 is a P gate base region which is a P type semiconductor layer, 25 is a P+ gate region which is a P type semiconductor layer with low resistance and high impurity concentration, 26
is an n+ cathode region which is an n-type semiconductor layer, and an anode electrode 27, a gate electrode 28, and a cathode electrode 29 are formed on the P+ anode region 23, the P+ gate region 25, and the n+ cathode region 26, respectively.

Furthermore, an opening 30 is provided at the end by connecting the n+ cathode region 26 and the P gate F/base region 24 by etching, and the opening 30 is provided with an opening 30 from the P+ gate region 2.1 and the P gate base region 28. The surface of the pn junction is exposed. Furthermore, the impurity concentration of the n-substrate 22 is low;
Since the impurity concentration of the n+ cathode region 26 is high, the P+ gate 1 region 25, the P gate base region 1524, and the n+
The cathode region 26 becomes a pin junction, and a high breakdown voltage can be obtained. In this way, the present invention can also be applied to a buried gate type GTo.

In addition, the Slisrisk, G
TO is a P-type gate Sl silice, GTO, but of course the present invention is an n-type gate Sl thyrisk, GTO.
It can also be applied to TO.

Next, a method for manufacturing the above-mentioned high voltage semiconductor device will be explained.

Figure 4(a) - (gl is the figure 1 fat - (C
) is a diagram illustrating the steps of the method for manufacturing Sl cyrisk shown in FIG.

First, the impurity atom concentration of phosphorus (P) is lXl0L+cm
n-silicon substrate 4 with a thickness of about 300 to 400 μm
0 is prepared, and a silicon dioxide (SiO2) film (not shown) is formed on one principal surface 43 of the n-silicon substrate 40 by thermal oxidation. Then, the silicon dioxide film is etched by photolithography to form a mask for forming a gate region.

Next, the temperature is 1150°C from the top and bottom surfaces of the n-silicon substrate 40.
At a temperature of
1. Provide a P+ region 42 that will become a gate, and form a junction with the n- silicon substrate 40 (FIG. 4(a)).

Next, on one main surface 43 of the n-silicon substrate 40 including the P+ region 42, an n-type film having a thickness of approximately 15 μm is grown by epitaxial growth.
A region 44 is formed (FIG. 4(b)).

Further, phosphorus (P) or the like is diffused onto the surface of the n- region 44 using POCl 3 or the like as a source to form an n+ region 45 having a thickness of approximately 3 μm and serving as a cathode (FIG. 4(C)).

Subsequently, HF:HNO3:CH3Cool-1=
Using an etching agent having a composition ratio of 15:100:5, the area from the n+ region 45 to the n- region 44 at the outer edge is selectively etched to form an opening 46 that exposes the surface of the P+ region 42 (a fourth Figure (d)). In addition, the opening 4
6 is desirably larger than the thickness β of the n-silicon substrate 40. Further, poron (B) is again diffused into the hatched area of the P+ region 42 whose surface is exposed in the opening 46 in order to lower the gate resistance and establish ohmic contact (FIG. 4(e)).

Next, an anode electrode 47, a gate electrode 48, a cathode electrode 4 made of β, etc. are formed on the P+ region 41, the P+ region 42, and the n+ region 45 by vapor deposition or sputtering, respectively.
9 (Fig. 4(f)).

Finally, the opening 46 is covered with a burnishing film 50 made of silicon dioxide, nitride, polyimide, etc., leaving the bonding bathode regions of the gate electrode 48 and cathode electrode 49 (FIG. 3(g)).

In addition, in the above-mentioned embodiment of the manufacturing method of the present invention, an example was explained in which one Sl silis is manufactured, but it is of course possible to manufacture many Sl silis on one wafer at the same time by the manufacturing method of the present invention. It is. Therefore, a large number of Sl silicon risks can be manufactured on one wafer up to the final process, resulting in a mass production effect. Furthermore, the conditions such as temperature, impurity density, and diffusion time in the diffusion process and the dimensions of the element in each process are not limited to those in the above embodiments.

As described above, in the method for manufacturing a high voltage semiconductor device of the present invention, the etching agent used to form the opening for making ohmic contact is used to remove the etching agent, which consists of the gate region and the base region.
An opening is formed so that the n-junction has a planar diode structure. For this reason, the planar diode structure provides a withstand voltage on the pn junction surface, so it is not possible to use the conventional pn junction.
There is no need to process the joining surface into a bevel shape. Furthermore, since the openings are formed by chemical etching, there is little contamination of the pn junction surface, resulting in a smooth finish and a high yield.

Although the above embodiments have described the Sl silicon risk and buried gate type GTO, the present invention is also applicable to other buried gate structures such as 5IT (static induction transistor) in addition to the Sl silicon risk and buried gate type GTO. It can also be applied to voltage-resistant semiconductor devices. Further, in this embodiment, only a high voltage semiconductor device having a P-type gate has been described, but the present invention can also be applied to a buried gate type high voltage semiconductor device having an n-type gate.

〔Effect of the invention〕

As explained above, according to the present invention, the forward breakdown voltage is obtained by the planar diode structure formed by the etching process that makes ohmic contact with the gate electrode, so the bevel structure is technically difficult and difficult to increase the yield. This eliminates the need for a structure forming process, improving productivity.

Furthermore, according to the manufacturing method of the present invention, when manufacturing a plurality of high voltage semiconductor devices on one wafer, each device is cut individually as in the conventional method, and then the pn junction surface of each device is formed into a bevel structure. This eliminates the need for processing steps and allows multiple high-voltage semiconductor devices to be manufactured on a wafer up to the final process, resulting in a mass production effect and lower costs.

[Brief explanation of the drawing]

FIGS. 1(a), (bl, fc) are a plan view, a front view, a side view, and a front view, respectively, of an SI risk according to an embodiment of the present invention.
Figures 2(a) to (C1 are diagrams showing the configuration of the Sl silicon risk according to another embodiment of the present invention, and Figure 3 is a diagram showing the configuration of a buried gate type GT according to an embodiment of the present invention.
4[0] to (g) are diagrams explaining the manufacturing process of an Sl thyristor according to an embodiment of the present invention. FIG. 5(a) and fbl are bevels of positive bevel and negative bevel, respectively. FIG. 6 is a cross-sectional view of a pnp transistor having a bevel structure, which shows the magnitude of the maximum electric field at the surface of a pn junction when a bevel structure is used. 2 . . . n-″ group 1, 3... p+ anode region, 4... p+ gate region, 5... n- region, 6... n+ cathode region, 10... opening. Patent Applicant Toyota Industries Corporation Same as above Semiconductor Research Promotion Foundation 60"h Sortnik Zero lbu 15S 14P"h-n@k < C) 4 colors of Zhao's other suojiku@shown T figure 2 Diagram (G) (b) (C) (d) Seven hemorrhoids Kazumi's brother's evening IC 4th (e) (f) nsI dimension Irisu Noriwa store 2 ni Continuation of figure 4 page ■ Int, Cl,' Identification code Internal reference number // H01L 29/80
V 8122-5F @ Inventor Nishizawa
Jun - Tsukikai, Sendai City, Miyagi Prefecture 0 Inventor Tamamushi Hisashige Tsukikai, Sendai City, Miyagi Prefecture

Claims (1)

[Scope of Claims] 1) In a high voltage semiconductor element having a pn junction capable of obtaining a forward breakdown voltage, and in which one of the semiconductor layers constituting the pn junction is a gate layer, the pn 1. A high voltage semiconductor device, characterized in that a recess is formed by etching over the bonding, and the surface of the pn junction appears only within the recess. 2) The high voltage semiconductor device according to claim 1, wherein the width of the recess is approximately equal to or greater than the maximum width of a depletion layer that occurs when the pn junction is biased in a reverse direction. 3) A gate layer, which is a semiconductor layer of a conductivity type opposite to that of the semiconductor substrate, is formed in a semiconductor substrate of one conductivity type by impurity diffusion, and the gate layer and the semiconductor substrate form a pn junction that can obtain a forward breakdown voltage. and an etching step of forming a recess for connecting an electrode to the gate layer by etching. A method for manufacturing a high-voltage semiconductor device, characterized in that a recess is formed from the top surface of the pn junction to the pn junction, and etching is performed so that the surface of the pn junction appears only within the recess. 4) The method of manufacturing a high voltage semiconductor device according to claim 3, wherein the width of the recess is approximately equal to or greater than the maximum width of a depletion layer that occurs when the pn junction is biased in the opposite direction.