JPH0184452U - - Google Patents
Info
- Publication number
- JPH0184452U JPH0184452U JP18156787U JP18156787U JPH0184452U JP H0184452 U JPH0184452 U JP H0184452U JP 18156787 U JP18156787 U JP 18156787U JP 18156787 U JP18156787 U JP 18156787U JP H0184452 U JPH0184452 U JP H0184452U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- electrode
- insulating film
- window
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18156787U JPH0184452U (US07922777-20110412-C00004.png) | 1987-11-27 | 1987-11-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18156787U JPH0184452U (US07922777-20110412-C00004.png) | 1987-11-27 | 1987-11-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0184452U true JPH0184452U (US07922777-20110412-C00004.png) | 1989-06-05 |
Family
ID=31473048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18156787U Pending JPH0184452U (US07922777-20110412-C00004.png) | 1987-11-27 | 1987-11-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0184452U (US07922777-20110412-C00004.png) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57164564A (en) * | 1981-04-03 | 1982-10-09 | Nec Corp | Planar semiconductor device |
-
1987
- 1987-11-27 JP JP18156787U patent/JPH0184452U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57164564A (en) * | 1981-04-03 | 1982-10-09 | Nec Corp | Planar semiconductor device |
