JPH0184149U - - Google Patents
Info
- Publication number
- JPH0184149U JPH0184149U JP1988152960U JP15296088U JPH0184149U JP H0184149 U JPH0184149 U JP H0184149U JP 1988152960 U JP1988152960 U JP 1988152960U JP 15296088 U JP15296088 U JP 15296088U JP H0184149 U JPH0184149 U JP H0184149U
- Authority
- JP
- Japan
- Prior art keywords
- history
- history memory
- error occurs
- hardware error
- freeze
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003745 diagnosis Methods 0.000 claims 1
- 238000012423 maintenance Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Description
図は本考案による実施例のデータ処理装置の要
部ブロツク図である。
図中、１はヒストリ制御回路、２は割込みトラ
ツプ回路、３はヒストリ凍結制御レジスタ、１０
はヒストリ凍結指示信号線である。
The figure is a block diagram of main parts of a data processing device according to an embodiment of the present invention. In the figure, 1 is a history control circuit, 2 is an interrupt trap circuit, 3 is a history freeze control register, and 10 is a history control circuit.
is the history freeze instruction signal line.
Claims (1)
期して順次記録してゆくとともに、ハードウエア
・エラーが生じたとき該記録動作を凍結せしめら
れるヒストリ・メモリを有するデータ処理装置に
おいて、ヒストリ凍結制御レジスタと、該ヒスト
リ凍結制御レジスタの内容にしたがつて所定条件
発生時にヒストリ凍結指示信号を発生するゲート
回路とをそなえ、上記ハードウエア・エラー発生
時とともに該ハードウエア・エラー以外の所定条
件が発生したときにも上記ヒストリ・メモリの凍
結を可能にし、さらに上記所定条件の１つとして
保守診断命令発生を含むよう構成したことを特徴
とするヒストリ・メモリ制御回路。 In a data processing device having a history memory that sequentially records information at a predetermined location within the processing device in synchronization with a clock and freezes the recording operation when a hardware error occurs, a history freeze control register is used. and a gate circuit that generates a history freeze instruction signal when a predetermined condition occurs according to the contents of the history freeze control register, and when the hardware error occurs and a predetermined condition other than the hardware error occurs. A history memory control circuit, characterized in that the history memory can be frozen even when the history memory is frozen, and the history memory control circuit is further configured to include generation of a maintenance diagnosis command as one of the predetermined conditions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988152960U JPH0184149U (en) | 1988-11-24 | 1988-11-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988152960U JPH0184149U (en) | 1988-11-24 | 1988-11-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0184149U true JPH0184149U (en) | 1989-06-05 |
Family
ID=31428364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988152960U Pending JPH0184149U (en) | 1988-11-24 | 1988-11-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0184149U (en) |
-
1988
- 1988-11-24 JP JP1988152960U patent/JPH0184149U/ja active Pending
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