JPH0180951U - - Google Patents

Info

Publication number
JPH0180951U
JPH0180951U JP1987177441U JP17744187U JPH0180951U JP H0180951 U JPH0180951 U JP H0180951U JP 1987177441 U JP1987177441 U JP 1987177441U JP 17744187 U JP17744187 U JP 17744187U JP H0180951 U JPH0180951 U JP H0180951U
Authority
JP
Japan
Prior art keywords
island
stitch
semiconductor device
plastic package
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987177441U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987177441U priority Critical patent/JPH0180951U/ja
Publication of JPH0180951U publication Critical patent/JPH0180951U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第1図は本考案の一実施例の縦断面図、第2図
は本考案の他の実施例の縦断面図、第3図は従来
例の縦断面図である。 1,21,31……リードフレーム、2……第
1ステツチ部、3,24……絶縁物、4……第2
ステツチ部、5,25,33……半導体チツプ、
6,7,26,34……電極、8,9,28,3
5……ステツチ、10,11,27,36……A
u線、22,32……ステツチ部、23,37…
…アイランド部、12,29,37……半導体装
置プラスチツクパツケージ。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 半導体素子を取り付けるアイランドと、該
    アイランド上の半導体素子電極に金属細線による
    接続をするステツチ部とを有し、該ステツチ部は
    絶縁物を介して2層構造をなしていることを特徴
    とする半導体装置プラスチツク・パツケージ用リ
    ードフレーム。 (2) 前記ステツチ部と前記アイランド部とが絶
    縁物を介して固定された2層構造をなしているこ
    とを特徴とする実用新案登録請求の範囲第1項記
    載の半導体装置プラスチツク・パツケージのリー
    ドフレーム。
JP1987177441U 1987-11-20 1987-11-20 Pending JPH0180951U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987177441U JPH0180951U (ja) 1987-11-20 1987-11-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987177441U JPH0180951U (ja) 1987-11-20 1987-11-20

Publications (1)

Publication Number Publication Date
JPH0180951U true JPH0180951U (ja) 1989-05-30

Family

ID=31469105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987177441U Pending JPH0180951U (ja) 1987-11-20 1987-11-20

Country Status (1)

Country Link
JP (1) JPH0180951U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04123464A (ja) * 1990-09-13 1992-04-23 Mitsubishi Electric Corp 半導体集積回路装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04123464A (ja) * 1990-09-13 1992-04-23 Mitsubishi Electric Corp 半導体集積回路装置

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