JPH01770A - Compound semiconductor integrated circuit - Google Patents
Compound semiconductor integrated circuitInfo
- Publication number
- JPH01770A JPH01770A JP62-64015A JP6401587A JPH01770A JP H01770 A JPH01770 A JP H01770A JP 6401587 A JP6401587 A JP 6401587A JP H01770 A JPH01770 A JP H01770A
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- substrate
- integrated circuit
- gaas
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 150000001875 compounds Chemical class 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 14
- 239000013078 crystal Substances 0.000 description 5
- RCJVRSBWZCNNQT-UHFFFAOYSA-N dichloridooxygen Chemical compound ClOCl RCJVRSBWZCNNQT-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical group [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は化合物半導体を基板として用いた集積回路に関
する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an integrated circuit using a compound semiconductor as a substrate.
（従来の技術）
現在、集積回路は主にシリコン（Ｓｉ）を基板として作
られているが、例えばＧａＡｓはＳｉよりも電子移動度
が大きく、また、半絶縁性基板を作ることが可能である
ため、ＧａＡｓを集積回路基板として用いれば、Ｓｉを
基板として用いるよりも高速動作を実現できる。ＧａＡ
ｓを基板として用いたＧａＡｓ集積回路の基本素子とし
ては、ＧａＡｓショットキ障壁接合ゲート型電界効果ト
ランジスタ（以後ＧａＡｓ ＭＥＳＦＥＴと記す）が多
く用いられている。また、基本回路構成としては、ＤＣ
ＦＬ（Ｄｉｒｅｃｔ Ｃｏｕｐｌｅｄ ＦＥＴ Ｌｏｇ
ｉｃ）、ＢＥＬ（Ｂｕｆｆｕｒｅｄ ＦＥＴ Ｌｏｇｉ
ｃ） 、５ＣＦＬ（Ｓｏｕｒｃｅ ＣｏｕｐｌｅｄＦＥ
Ｔ Ｌｏｇｉｃ）などがあるが１．このうちＤＣＦＬお
よび５ＣＦＬでは、しきい値電圧の異なったＦＥＴを同
一基板上に形成する必要がある。(Prior art) Currently, integrated circuits are mainly made using silicon (Si) as a substrate, but GaAs, for example, has higher electron mobility than Si, and it is also possible to make semi-insulating substrates. Therefore, if GaAs is used as an integrated circuit substrate, higher speed operation can be achieved than if Si is used as a substrate. GaA
GaAs Schottky barrier junction gate field effect transistors (hereinafter referred to as GaAs MESFETs) are often used as basic elements of GaAs integrated circuits using S as a substrate. In addition, the basic circuit configuration is DC
FL (Direct Coupled FET Log
ic), BEL (Buffered FET Logi)
c) , 5CFL (Source CoupledFE
T Logic) etc. 1. Among these, DCFL and 5CFL require FETs with different threshold voltages to be formed on the same substrate.
（発明が解決しようとする問題点）
従来、しきい値電圧の異なるＦＥＴを同一基板上に形成
するためにはキャリア密度あるいは厚さの異なるＧａＡ
ｓ結晶層を動作領域とするＦＥＴを同一基板上に形成し
ていた。しかし、このような方法ではｎ型ＧａＡｓ結晶
層を形成するための工程が複数回必要であり、工程が煩
雑であるという欠点があった。(Problems to be Solved by the Invention) Conventionally, in order to form FETs with different threshold voltages on the same substrate, GaAs with different carrier densities or thicknesses have been used.
FETs whose operating region is the s-crystal layer were formed on the same substrate. However, such a method requires a plurality of steps to form the n-type GaAs crystal layer, and has the disadvantage that the steps are complicated.
本発明の目的は、製造工程を簡略化したしきい値電圧の
異なるＦＥＴを含むＧａＡｓ集積回路を提供するもので
ある。An object of the present invention is to provide a GaAs integrated circuit including FETs with different threshold voltages, which simplifies the manufacturing process.
（問題点を解決するための手段）
本発明の集積回路は化合物半導体基板の面方位（１００
）面上に形成された同一種類の動作層を有するショット
キ障壁、接合ゲート型電界効果トランジスタのゲート電
極を制御すべきしきい値電圧の大きさに応じて各々異な
る方位に配置し、該トランジスタを有する化合物半導体
基板の裏面に応力を有する絶縁膜あるいは金属膜が設け
られていることを特徴とする。化合物半導体集積回路で
構成される。(Means for Solving the Problems) The integrated circuit of the present invention has a surface orientation (100
), the gate electrodes of junction gate field effect transistors having the same type of active layer formed on the surface are arranged in different directions depending on the magnitude of the threshold voltage to be controlled, and the transistors are It is characterized in that an insulating film or a metal film having stress is provided on the back surface of the compound semiconductor substrate. Consists of compound semiconductor integrated circuits.
（作用）
本発明は基板の裏面に応力を有する金属膜を被着して基
板を曲げた場合、ＧａＡｓ ＭＥＳＦＥＴのしきい値電
圧ＶＴが基板の曲率またはそり量に比例して変化し、そ
の変化の方向がＭＥＳＦＥＴの方位によって異なるとい
う発見に基づいたものである。第２図に短冊状に切断し
たＧａＡｓ基板上に形成された異なる方位を有するＦＥ
ＴのｖＴと基板のそり量の関係を示したもので、第３図
はこの２種類のＦＥＴの方位と結晶エッチの関係を示し
ている。図中３１は面方位（１００）ノ基板面、３２は
［０１月方位）ＦＥＴ、３３は［０１１］方位のＦＥＴ
である。第２図よりそりを加えた場合［０１１］と［０
１月の方位によってＶＴの変化が逆方向に移行し、異な
るＶＴを有することがわかる。(Function) The present invention provides that when a metal film having stress is applied to the back surface of the substrate and the substrate is bent, the threshold voltage VT of the GaAs MESFET changes in proportion to the curvature or amount of warpage of the substrate. This is based on the discovery that the direction of the MESFET differs depending on the orientation of the MESFET. Figure 2 shows FEs with different orientations formed on a GaAs substrate cut into strips.
It shows the relationship between vT of T and the amount of warpage of the substrate, and FIG. 3 shows the relationship between the orientation and crystal etch of these two types of FETs. In the figure, 31 is the (100) substrate surface, 32 is the [01 orientation) FET, and 33 is the [011] orientation FET.
It is. From Figure 2, when warpage is added, [011] and [0
It can be seen that the change in VT shifts in the opposite direction depending on the orientation in January, and has different VT.
ＧａＡｓのようにせん亜鉛鉱構造では結晶に歪みが加え
られると分極が誘起され、その分極により電荷が発生す
ることが知られている。そして、その電荷は結晶方位に
よって異なるため、本実験のように方位依存性が現われ
たものと考えられる。It is known that in a zincite structure such as GaAs, polarization is induced when strain is applied to the crystal, and electric charges are generated due to the polarization. Since the charge differs depending on the crystal orientation, it is thought that orientation dependence appeared as in this experiment.
（実施例）
次に、本発明の一実施例について図面を参照して説明す
る。(Example) Next, an example of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.
先ず、第１図（ａ）に示すようにＧａＡｓの半絶縁性基
板５の表面にＳｉイオンを５０ＫｅＶ、２．５刈０１２
ｃｍ−２の条件でイオン注入し、さらにＡｓ圧雰囲気中
で８００’Ｃｌ２Ｏ分間のアニールを行い、ＧａＡｓ動
作層３を形成する。First, as shown in FIG. 1(a), Si ions were applied to the surface of a GaAs semi-insulating substrate 5 at 50 KeV and 2.5 volts.
Ion implantation is performed under the condition of cm-2, and further annealing is performed for 800'Cl2O minutes in an As pressure atmosphere to form a GaAs active layer 3.
次に、第１図（ｂ）に示すように、動作層３を覆うよう
に半絶縁性基板５上に、タングステンシリサイド（ＷＳ
ｉ）をスパッタ法を用いて０．５ｐｍの膜厚に堆積した
後、通常のホトリソグラフィ法と四フッ化炭素を用いた
ドライエツチング法とによってＷＳｉの膜を所定の形に
パターニングし、ショットキゲート１を形成する。Next, as shown in FIG. 1(b), tungsten silicide (WS) is placed on the semi-insulating substrate 5 so as to cover the active layer 3.
After depositing i) to a film thickness of 0.5 pm using a sputtering method, the WSi film was patterned into a predetermined shape by ordinary photolithography and dry etching using carbon tetrafluoride, and a Schottky gate was formed. Form 1.
続いて第１図（ｃ）に示すように、ショットキゲート１
をマスクにして、Ｓｉイオンを１５０ＫｅＶ。Next, as shown in FIG. 1(c), Schottky gate 1
Using a mask, Si ions were heated at 150 KeV.
５Ｘ１０１３ｃｍ−３の条件でイオン注入し、更にＡｓ
圧雰囲気中で７５０°Ｃｌ２Ｏ分のアニールを行いｎ中
層４ａ、４ｂを形成する。Ion implantation was performed under the conditions of 5X1013cm-3, and As
Annealing for 750° Cl2O is performed in a pressure atmosphere to form n intermediate layers 4a and 4b.
続いて、第１図（ｄ）に示すように、ＡｕＧｅ−Ｎｉの
金属層からなるソース電極２ａ及びドレイン電極２ｂを
形成する。Subsequently, as shown in FIG. 1(d), a source electrode 2a and a drain electrode 2b made of a metal layer of AuGe-Ni are formed.
最後にこのＧａＡｓ基板の裏面に２ Ｘ １０１０ｄｙ
ｎ／ｃｍ”の膜応力を有するＷ膜６をスパッタ法で４ｐ
ｍ全面堆積し、［０１１］ＦＥＴよりエンハンスメント
型ＦＥＴ、［０１１］、ＦＥＴよりデプレッション型Ｆ
ＥＴを製作した。Finally, 2 x 1010dy on the back side of this GaAs substrate.
A 4p W film 6 having a film stress of "n/cm" is formed by sputtering.
Deposited on the entire surface, enhancement type FET than [011] FET, depletion type F than [011] FET
I made ET.
以上の実施例では［０１１］方位と［０１１］方位の２
つの直交した方向にＦＥＴを作成したが、任意の方向で
作成することができる。この場合、第２図に示した基板
のそり量としきい値電圧の関係も変化するので、所望の
異なるしきい値電圧のＦＥＴが容易に作成できる。In the above embodiment, the two directions are [011] and [011].
Although FETs were fabricated in two orthogonal directions, they can be fabricated in any direction. In this case, since the relationship between the amount of substrate warpage and the threshold voltage shown in FIG. 2 also changes, FETs with different desired threshold voltages can be easily created.
（発明の効果）
以上説明したように、本発明によれば、しきい値電圧の
異なるＦＥＴを含む集積回路を、１種類の動作層を有す
るＦＥＴで形成することができるため、製作工程を大幅
に簡素化できる効果がある。(Effects of the Invention) As explained above, according to the present invention, an integrated circuit including FETs with different threshold voltages can be formed using FETs having one type of active layer, so the manufacturing process can be significantly reduced. This has the effect of simplifying the process.
第１図（ａ）〜（ｄ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図、第２は本発
明の一実施例を説明するための１しきい値電圧の変化と
基板のそり量の関係を示した図、第３図は本発明の基礎
となる実験結果を説明するための模式％式％
図中、
１・・・ショットキゲート、２ａ・・・ソース電極、２
ｂ・・・ドレイン電極、３・・・動作層、４ａ、４ｂ・
・・ｎ型層、５・・・半絶縁性基板、６・・・Ｗ膜、３
１・・・面方位（１００）の基板面、３２・・・［０１
１］方位のＦＥＴ、３３・・・［０１１］方位のＦＥＴ
である。Figures 1 (a) to (d) are cross-sectional views of a semiconductor chip shown in order of steps to explain an embodiment of the present invention, and Figure 2 is a threshold value for explaining an embodiment of the present invention. FIG. 3 is a diagram showing the relationship between voltage changes and the amount of warpage of the substrate, and is a schematic % formula for explaining the experimental results that form the basis of the present invention. In the figure, 1... Schottky gate, 2a... Source electrode, 2
b...Drain electrode, 3...Active layer, 4a, 4b.
... n-type layer, 5 ... semi-insulating substrate, 6 ... W film, 3
1...Substrate surface with plane orientation (100), 32...[01
1] FET in the direction, 33...FET in the [011] direction
It is.
Claims (1)
た同一種類動作層を有するショットキ障壁接合ゲート型
電界効果トランジスタのゲート電極を、制御すべきしき
い値電圧の大きさに応じて各々異なる方位に配置し、該
トランジスタを有する化合物半導体基板の裏面に応力を
有する絶縁膜あるいは金属膜が設けられていることを特
徴とする化合物半導体集積回路。The gate electrodes of Schottky barrier junction gate field effect transistors having the same type of active layer formed on the (100) plane of a compound semiconductor substrate are arranged in different orientations depending on the magnitude of the threshold voltage to be controlled. 1. A compound semiconductor integrated circuit, characterized in that an insulating film or a metal film having stress is provided on the back surface of a compound semiconductor substrate having the transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62-64015A JPH01770A (en) | 1987-03-20 | Compound semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62-64015A JPH01770A (en) | 1987-03-20 | Compound semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS64770A JPS64770A (en) | 1989-01-05 |
| JPH01770A true JPH01770A (en) | 1989-01-05 |
Family
ID=
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