JPH0177052U - - Google Patents
Info
- Publication number
- JPH0177052U JPH0177052U JP1987173044U JP17304487U JPH0177052U JP H0177052 U JPH0177052 U JP H0177052U JP 1987173044 U JP1987173044 U JP 1987173044U JP 17304487 U JP17304487 U JP 17304487U JP H0177052 U JPH0177052 U JP H0177052U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- positive
- clock
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002194 synthesizing effect Effects 0.000 claims description 3
- 238000000605 extraction Methods 0.000 claims 2
- 239000000284 extract Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図は本考案の基本的構成を示す図、第２図
は本考案の実施例の構成を示す図、第３図は実施
例の動作波形図を示す図である。
第１図中、１０：正・反転データ発生回路、１
１：微分回路、１２：合成回路、１３：帯域通過
フイルタ。
FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is a diagram showing an operation waveform diagram of the embodiment. In Figure 1, 10: Positive/inverted data generation circuit, 1
1: Differentiating circuit, 12: Synthesizing circuit, 13: Band pass filter.
Claims (1)
ク抽出回路において、 ＮＲＺ信号から正相信号と反転位相の信号を発
生する正・反転データ発生回路１０と、 該正・反転データ発生回路１０の各信号出力を
微分する微分回路１１と、 前記微分回路１１の出力を加算し波形整形する
合成回路１２と、 該合成回路１２の出力を入力してクロツク信号
を出力する帯域通過フイルタ１３とで構成される
ことを特徴とするクロツク抽出回路。[Claims for Utility Model Registration] In a clock extraction circuit that extracts a clock signal from an NRZ signal, a positive/inverted data generation circuit 10 that generates a positive phase signal and an inverted phase signal from the NRZ signal, and the positive/inverted data generation circuit 10. A differentiating circuit 11 that differentiates each signal output of the circuit 10, a synthesizing circuit 12 that adds the outputs of the differentiating circuit 11 and shapes the waveform, and a bandpass filter 13 that inputs the output of the synthesizing circuit 12 and outputs a clock signal. A clock extraction circuit characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987173044U JPH0177052U (en) | 1987-11-12 | 1987-11-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987173044U JPH0177052U (en) | 1987-11-12 | 1987-11-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0177052U true JPH0177052U (en) | 1989-05-24 |
Family
ID=31464983
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987173044U Pending JPH0177052U (en) | 1987-11-12 | 1987-11-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0177052U (en) |
-
1987
- 1987-11-12 JP JP1987173044U patent/JPH0177052U/ja active Pending
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