JPH0176603U - - Google Patents
Info
- Publication number
- JPH0176603U JPH0176603U JP1987170928U JP17092887U JPH0176603U JP H0176603 U JPH0176603 U JP H0176603U JP 1987170928 U JP1987170928 U JP 1987170928U JP 17092887 U JP17092887 U JP 17092887U JP H0176603 U JPH0176603 U JP H0176603U
- Authority
- JP
- Japan
- Prior art keywords
- speed
- load
- internal
- error
- command
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Feedback Control In General (AREA)
Description
第１図はこの考案の一実施例を示す制御装置の
構成図、第２図はこの考案の動作を示す波形図、
第３図は従来の制御装置の構成図、第４図は従来
の制御装置の動作を示す波形図である。
図中１は速度ループ演算器、２は積分器、３は
内部速度ループ演算器、４はパワーアンプ、５は
負荷、６は切換スイツチ、７は速度指令、８は負
荷速度、９は速度エラー、１０は内部速度指令、
１１は内部速度エラー、１２はリミツタ、１３は
リミツタ出力である。なお、図中、同一あるいは
相当部分には同一符号を付して示してある。
Fig. 1 is a configuration diagram of a control device showing an embodiment of this invention, Fig. 2 is a waveform diagram showing the operation of this invention,
FIG. 3 is a configuration diagram of a conventional control device, and FIG. 4 is a waveform diagram showing the operation of the conventional control device. In the figure, 1 is a speed loop calculator, 2 is an integrator, 3 is an internal speed loop calculator, 4 is a power amplifier, 5 is a load, 6 is a changeover switch, 7 is a speed command, 8 is a load speed, and 9 is a speed error , 10 is the internal speed command,
11 is an internal speed error, 12 is a limiter, and 13 is a limiter output. In the drawings, the same or corresponding parts are designated by the same reference numerals.
Claims (1)
において、速度指令が入力され速度指令と負荷の
速度から速度ループエラーを演算する速度ループ
演算器と、速度ループエラーを積分して内部速度
指令を生成する積分器と、積分器の出力を制限す
るリミツタと、速度指令とリミツタ出力の和から
負荷速度を引いて内部速度エラーを演算する内部
速度ループ演算器と、内部速度エラーにより負荷
を駆動するパワーアンプと、速度指令を内部速度
ループ演算器に入力することを切換える切換スイ
ツチとから構成され、切換スイツチが入る時には
積分器の出力を制限することで負荷の速度変動を
小さくすることを特徴とした制御装置。 In a control device that controls the speed of a load using a speed command, there is a speed loop calculator that receives the speed command and calculates a speed loop error from the speed command and the load speed, and a speed loop calculator that integrates the speed loop error to generate an internal speed command. An integrator, a limiter that limits the output of the integrator, an internal speed loop calculator that calculates an internal speed error by subtracting the load speed from the sum of the speed command and limiter output, and a power amplifier that drives the load using the internal speed error. and a changeover switch that switches input of the speed command to the internal speed loop calculator, and when the changeover switch is turned on, the control is characterized by limiting the output of the integrator to reduce speed fluctuations of the load. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987170928U JPH0176603U (en) | 1987-11-09 | 1987-11-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987170928U JPH0176603U (en) | 1987-11-09 | 1987-11-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0176603U true JPH0176603U (en) | 1989-05-24 |
Family
ID=31462299
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987170928U Pending JPH0176603U (en) | 1987-11-09 | 1987-11-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0176603U (en) |
-
1987
- 1987-11-09 JP JP1987170928U patent/JPH0176603U/ja active Pending
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