JPH0156556B2 - - Google Patents
Info
- Publication number
- JPH0156556B2 JPH0156556B2 JP4172283A JP4172283A JPH0156556B2 JP H0156556 B2 JPH0156556 B2 JP H0156556B2 JP 4172283 A JP4172283 A JP 4172283A JP 4172283 A JP4172283 A JP 4172283A JP H0156556 B2 JPH0156556 B2 JP H0156556B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- substrate
- board
- film
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 57
- 239000010409 thin film Substances 0.000 claims description 29
- 239000003990 capacitor Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 238000005476 soldering Methods 0.000 claims description 6
- 239000010408 film Substances 0.000 description 61
- 229910000679 solder Inorganic materials 0.000 description 25
- 238000000034 method Methods 0.000 description 18
- 238000004519 manufacturing process Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 238000009966 trimming Methods 0.000 description 4
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 229910001120 nichrome Inorganic materials 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910004491 TaAlN Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 230000005587 bubbling Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Combinations Of Printed Boards (AREA)
- Networks Using Active Elements (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は集積回路装置、特に膜集積回路が形成
された主基板に膜集積回路が形成された副基板が
搭載されてなる構造を有する集積回路装置の改良
に関する。Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to an integrated circuit device, particularly an integrated circuit device having a structure in which a main substrate on which a film integrated circuit is formed and a sub-substrate on which a film integrated circuit is formed are mounted. Related to improvements in circuit devices.
(b) 技術の背景
混成集積回路は、二つ以上の異種の集積回路の
組合わせ、あるいは一つ以上の独立したデバイス
又は部品と一つ以上の集積回路からなる回路と定
義されて、具体的には膜集積回路と個別部品、膜
集積回路と半導体集積回路、膜集積回路と半導体
集積回路と個別部品、半導体集積回路と個別部品
の組合せがある。(b) Background of the Technology A hybrid integrated circuit is defined as a combination of two or more dissimilar integrated circuits, or a circuit consisting of one or more independent devices or components and one or more integrated circuits. There are combinations of film integrated circuits and individual parts, film integrated circuits and semiconductor integrated circuits, film integrated circuits and semiconductor integrated circuits and individual parts, and semiconductor integrated circuits and individual parts.
この様に多くの混成集積回路においては膜集積
回路が用いられており、半導体集積回路に比較し
て混成集積回路の特徴とされる、設計の自由度が
大きい、抵抗値や容量値を幅広くかつ精密に選択
することができる、素子及び回路相互間の分離が
容易で寄生容量を小さくできる、高電力や低電力
に有利である、迅速に供給することができかつ小
数量でも採算がとれる、などの利点は膜集積回路
に負うところが大きい。 In this way, many hybrid integrated circuits use film integrated circuits, and compared to semiconductor integrated circuits, hybrid integrated circuits are characterized by a greater degree of freedom in design, a wider range of resistance and capacitance values, and a wider range of resistance and capacitance values. It can be selected precisely, it is easy to separate elements and circuits and reduce parasitic capacitance, it is advantageous for high power or low power, it can be supplied quickly and it is profitable even in small quantities, etc. The advantages of this are largely due to membrane integrated circuits.
膜集積回路には周知の如く、薄膜集積回路と厚
膜集積回路とがあり、薄膜集積回路は抵抗値等回
路素子定数に高精度かつ高安定が要求される場合
に不可欠とされ、また厚膜集積回路は経済性と小
形化に優れて、システムの要求に応じて選択され
ている。 As is well known, there are two types of film integrated circuits: thin film integrated circuits and thick film integrated circuits. Integrated circuits are economical and compact, and are selected depending on system requirements.
(c) 従来技術と問題点
混成集積回路が応用される代表的な例としてア
クテイブフイルタがあげられる。(c) Prior art and problems Active filters are a typical example where hybrid integrated circuits are applied.
アクテイブフイルタは、その回路に用いられる
薄膜形成される抵抗体及びコンデンサの定数の許
容範囲が狭くかつ安定であることが要求されるた
めに薄膜集積回路が用いられて、従来その基板上
に半導体集積回路である演算増幅器を搭載してフ
イルタ回路を構成し、更に外部接続端子もこの基
板に接続されている。 Active filters use thin film integrated circuits because the resistors and capacitors used in the circuit are required to have narrow tolerances and stability in constants. An operational amplifier circuit is mounted to form a filter circuit, and external connection terminals are also connected to this board.
この構造においては、第1図に示す如く基板1
上に、薄膜集積回路の本来の目的である抵抗体及
びコンデンサの回路素子形成領域2(図中斜線で
示す)の他に、演算増幅器3及び外部接続端子4
(一部のみ図示する)の接続部分等の必ずしも薄
膜であることを必要としない回路の形成領域5を
広く設けることが必要であつて、場合によつては
基板面積の1/2以上がこれらの薄膜によつて形成
することを必要としない接続領域等の回路部分に
費やされる。 In this structure, as shown in FIG.
On the top, in addition to the circuit element forming area 2 (shown with diagonal lines in the figure) of resistors and capacitors, which are the original purpose of the thin film integrated circuit, there are also operational amplifiers 3 and external connection terminals 4.
It is necessary to provide a wide area 5 for forming circuits that do not necessarily need to be thin films, such as connecting parts (only a portion of which is shown), and in some cases, more than half of the board area is covered by these areas. This is used for circuit parts such as connection areas that do not need to be formed by thin films.
また、アクテイブフイルタにおいて高精密、高
安定が要求される前記の薄膜形成される抵抗体及
びコンデンサの多くは時定数を決定する素子であ
つて閉ループ回路を構成し、その時定数の許容範
囲は通常は±1〔%〕程度、厳格な場合には±0.1
〔%〕が要求される。 In addition, most of the thin-film resistors and capacitors mentioned above that require high precision and high stability in active filters are elements that determine the time constant and constitute a closed loop circuit, and the allowable range of the time constant is usually About ±1 [%], in strict cases ±0.1
[%] is required.
しかしながらコンデンサ素子の容量値は製造工
程において数〔%〕のばらつきを生ずることが避
け難く、薄膜集積回路の形成後に時定数の修正が
必要となることが多い。 However, it is unavoidable that the capacitance value of the capacitor element varies by several percent during the manufacturing process, and it is often necessary to correct the time constant after forming the thin film integrated circuit.
この修正を行なう実際的な方法は、まずコンデ
ンサの容量値を測定し、時定数すなわち容量値と
抵抗値との積が所定の値となる様に抵抗体をトリ
ミングする方法である。しかしながら容量値及び
抵抗値を精度良く測定するためには、閉ループ回
路の1個所を回路パターン形成の際には切断分離
し開ループとしておくことが必要であり、従来は
抵抗体のトリミング終了後にワイヤーボンデイン
グ或いははんだ付け等によつてこの切断分離した
回路を閉じるか、或いは外部接続端子を介して外
部で閉ループとしている。 A practical method for making this correction is to first measure the capacitance value of the capacitor and then trim the resistor so that the time constant, ie, the product of the capacitance value and the resistance value, becomes a predetermined value. However, in order to accurately measure capacitance and resistance values, it is necessary to cut and separate one part of the closed loop circuit to create an open loop when forming the circuit pattern. This cut and separate circuit is closed by bonding, soldering, etc., or it is made into a closed loop externally via an external connection terminal.
この様に抵抗値調整後の閉ループ形成のために
かなりの工数及び基板面積の増加を余儀なくされ
ている。 In this way, forming a closed loop after adjusting the resistance value requires a considerable increase in man-hours and substrate area.
以上説明した如く、従来1枚の薄膜集積回路に
よつて構成されるアクテイブフイルタ用集積回路
装置は、小型化及び集積規模の増大が困難であり
かつ高価であつて、その改善が強く要請されてい
る。 As explained above, the conventional active filter integrated circuit device composed of a single thin film integrated circuit is difficult to miniaturize and increase the scale of integration, and is expensive, and there is a strong demand for improvement. There is.
混成膜集積回路を複数の基板、すなわち1枚の
主基板とこれに搭載された単数又は複数の副基板
とに分割して形成する構造が既に知られている。
この構造は、例えば基本回路は同一であつて入出
力条件やピンレイアウトの異なる集積回路装置な
ど相互に類似する装置の供給が容易となること、
形状の小形化、集積規模の向上に有効であること
などの効果をもつ。高精度を要求される回路部分
のみを薄膜集積回路として副基板に形成して、厚
膜集積回路を形成した主基板上に搭載する本発明
に係る構造は、薄膜と厚膜とのそれぞれの利点を
生かす有効な手段であつて、機能と小形化及び経
済性とを両立させる効果を有する。 A structure in which a hybrid film integrated circuit is formed by dividing it into a plurality of substrates, that is, one main substrate and one or more sub-substrates mounted thereon, is already known.
This structure makes it easy to supply similar devices, such as integrated circuit devices with the same basic circuit but different input/output conditions and pin layouts.
It has effects such as being effective in reducing the size and increasing the scale of integration. The structure according to the present invention, in which only the circuit parts that require high precision are formed as thin film integrated circuits on a sub-substrate and mounted on the main substrate on which thick film integrated circuits are formed, has the advantages of thin film and thick film. It is an effective means of making the most of
従つて混成膜集積回路を主基板と副基板とに分
割形成する構造は、前記要請に対処し更に混成膜
集積回路を発展させるために最も有効な手段の一
つである。 Therefore, a structure in which a hybrid film integrated circuit is divided into a main substrate and a sub-substrate is one of the most effective means for meeting the above requirements and further developing hybrid film integrated circuits.
しかしながら、膜集積回路特に薄膜集積回路が
形成された副基板を厚膜集積回路が形成された主
基板に充分な信頼性をもつて接続することは決し
て容易ではなく、膜集積回路が基板の表裏両面に
形成され、また一般に膜集積回路に半導体集積回
路及び個別部品等も搭載されることがこの接続を
一層複雑にしている。 However, it is by no means easy to connect a sub-substrate on which a film integrated circuit, especially a thin film integrated circuit, is formed to a main substrate on which a thick film integrated circuit is formed with sufficient reliability. This connection is further complicated by the fact that it is formed on both sides, and that semiconductor integrated circuits and individual components are generally mounted on the membrane integrated circuit.
膜集積回路が形成された2枚の基板を平行に配
置して双方の回路を所要の位置において相互に接
続する方法として従来下記の方法が知られてい
る。 The following method is conventionally known as a method for arranging two substrates on which film integrated circuits are formed in parallel and connecting both circuits to each other at desired positions.
その一は通常は同一の大きさの複数の基板の周
辺の相対応する位置に接続パツドを設けて、この
間をリード線で接続する方法である。この方法に
おいてはパターン配置の自由度が失なわれ、かつ
接続工程においてかなりの工数を必要とする。 One method is to provide connection pads at corresponding positions around the periphery of a plurality of substrates, which are usually of the same size, and to connect these pads with lead wires. In this method, flexibility in pattern arrangement is lost and a considerable number of man-hours are required in the connection process.
基板の大きさが同じであることを必要とせず、
パターン配置の自由度が大きい方法としてははん
だバンプ法がある。この方法においては両基板面
内の任意の位置に相対応する接続パツドを設け
て、その間をはんだ球を融解することによつて接
続する。この方法は大きい利用価値を有するが、
基板の対向する面の間にフラツクス除去に必要な
空〓を再現性良く設けることが容易ではないこと
など、なお改良の余地を残している。 It does not require that the substrate sizes be the same,
A solder bump method is a method with a large degree of freedom in pattern arrangement. In this method, corresponding connection pads are provided at arbitrary positions on both substrates, and the connection is made between them by melting solder balls. Although this method has great utility value,
There is still room for improvement, including the fact that it is not easy to provide the space necessary for flux removal between opposing surfaces of the substrate with good reproducibility.
複数の基板を用いる混成集積回路装置に関し
て、その機能と集積規模を更に向上し、小形化、
経済性の向上を推進するためには、上記の他にも
改良すべき点があり、更に改善された構造が必要
とされている。 Regarding hybrid integrated circuit devices that use multiple substrates, we will further improve their functionality and integration scale, reduce their size,
In order to promote improvement in economic efficiency, there are other points to be improved in addition to the above, and a further improved structure is required.
(d) 発明の目的
本発明はアクテイブフイルタ回路を構成する膜
集積回路装置に関して、その回路を複数の基板に
分割形成する構造を進展せしめて、その機能と集
積規模の向上、小形化及び経済性の向上、を更に
推進することを目的とする。(d) Purpose of the Invention The present invention relates to a membrane integrated circuit device constituting an active filter circuit, and advances a structure in which the circuit is divided and formed on a plurality of substrates, thereby improving its function, integration scale, miniaturization, and economical efficiency. The aim is to further promote the improvement of
(e) 発明の構成
本発明の前記目的は、少なくとも複数個の膜形
成された抵抗およびコンデンサの回路素子と演算
増幅器を具備するアクテイブフイルタ回路を構成
する集積回路装置において、厚膜形成された回路
パターンを有する第1の基板と薄膜形成された回
路パターンを有する第2の基板を設け、前記第2
の基板は前記回路素子が相互に閉ループとならな
いように分離して前記回路パターンが形成される
と共に、該回路素子の素子値調整用のトリミング
が施されて製作され、前記第1の基板は前記回路
素子を閉ループに接続するための接続パツドを有
する前記回路パターンが形成されると共に、該第
1の基板の一辺には外部接続端子が接続してお
り、前記第1の基板と前記第2の基板とが両者の
前記接続パツドを金属球を介してはんだ接続さ
れ、また該第1の基板上の前記第2の基板が実装
される領域以外に前記演算増幅器が搭載されるこ
とにより、前記回路素子が前記第1の基板の前記
回路パターンにより閉ループにされて前記アクテ
イブフイルタ回路を構成することを特徴とした集
積回路装置により達成される。(e) Structure of the Invention The object of the present invention is to provide an integrated circuit device that constitutes an active filter circuit comprising at least a plurality of film-formed resistor and capacitor circuit elements and an operational amplifier. A first substrate having a pattern and a second substrate having a thin film-formed circuit pattern are provided;
The first substrate is manufactured by forming the circuit pattern by separating the circuit elements so as not to form a closed loop with each other, and trimming the circuit elements for adjusting element values, and the first substrate The circuit pattern having connection pads for connecting circuit elements in a closed loop is formed, and an external connection terminal is connected to one side of the first substrate, and the first substrate and the second substrate are connected to each other. The circuit board is connected to the circuit board by soldering the connection pads of both boards through metal balls, and by mounting the operational amplifier in a region other than the area where the second board is mounted on the first board. This is achieved by an integrated circuit device characterized in that the element is formed into a closed loop by the circuit pattern of the first substrate to form the active filter circuit.
(f) 発明の実施例
以下本発明の集積回路装置を実現する製造方法
を例示して本発明の特徴を説明し、次いで更に具
体的にアクテイブフイルタにかかる実施例を示
す。(f) Embodiments of the Invention The features of the present invention will be explained below by exemplifying the manufacturing method for realizing the integrated circuit device of the present invention, and then a more specific embodiment of an active filter will be shown.
(i) 厚膜集積回路の製造方法
基板としては例えば96%Al2O3セラミツク基
板を用い、AgPd系導体、RuO2系抵抗体等に
よつて所要の厚膜集積回路を形成し、はんだの
付着が許されない部分及び抵抗体をガラス質保
護膜で被覆する。(i) Method for manufacturing thick film integrated circuits For example, a 96% Al 2 O 3 ceramic substrate is used as the substrate, and the required thick film integrated circuit is formed with AgPd-based conductors, RuO 2 -based resistors, etc., and soldered. Cover areas where adhesion is not allowed and the resistor with a glass protective film.
厚膜集積回路を基板の表裏両面に形成する場
合にはそれぞれの面に前記方法を適用する。両
面の回路を所要の位置において電気的に接続す
ることが必要である場合には、予めその位置に
表裏貫通する孔を設けた基板を用いて、導体印
刷の際に基板の反対面から吸引することによつ
てペーストをこの孔内に流入させて孔の端面に
付着させ、焼成によつてスルーホールを形成す
る。 When forming thick film integrated circuits on both the front and back surfaces of a substrate, the above method is applied to each surface. If it is necessary to electrically connect circuits on both sides at a required position, use a board with a hole penetrating the front and back sides at that position in advance, and use suction from the opposite side of the board during conductor printing. By this, the paste is allowed to flow into the hole and adhere to the end face of the hole, and the through hole is formed by firing.
なお抵抗体は片面のみに集約することが望ま
しい。何故ならば第2面にペースト印刷をする
前に第1面の焼成を行なわねばならないため
に、第1面の抵抗体は2回焼成されて抵抗ペー
スト中のガラス成分の分離が進行して抵抗値の
低下を生じ、しかもシート抵抗値や抵抗パター
ンによつて低下量が変化しかつばらつき幅も大
きいためである。 Note that it is desirable that the resistors be concentrated on only one side. This is because the first side must be fired before the paste is printed on the second side, so the resistor on the first side is fired twice and the glass component in the resistor paste progresses to separate, forming a resistor. This is because the value decreases, and the amount of decrease changes depending on the sheet resistance value and resistance pattern, and the variation width is also large.
(ii) 薄膜集積回路の製造方法
薄膜集積回路を形成する基板としては例えば
99.5%Al2O3アルミナ基板もしくはグレーズド
基板を用いる。薄膜集積回路についてはこれを
基板の片面のみに形成する方が一般に有利であ
る。(ii) Manufacturing method for thin film integrated circuits Examples of substrates for forming thin film integrated circuits include
Use 99.5% Al 2 O 3 alumina substrate or glazed substrate. It is generally advantageous for thin film integrated circuits to be formed on only one side of a substrate.
基板上に、抵抗体は例えばTa2N又は
TaAlN等により、コンデンサは例えばTa2O5
を誘電体として、導体としては例えばTa膜上
にNiCrを介して形成するAu膜を用いて、薄膜
集積回路を形成する。次いで例えばCO2レーザ
によつて基板分割のための溝を形成する。 On the substrate, the resistor is made of e.g. Ta 2 N or
TaAlN, etc., the capacitor is e.g. Ta 2 O 5
A thin film integrated circuit is formed by using the dielectric material as a dielectric material and the conductor as an Au film formed on a Ta film via NiCr, for example. Next, grooves for dividing the substrate are formed using, for example, a CO 2 laser.
しかる後に有機絶縁性皮膜例えばレジスト皮
膜によつて薄膜集積回路を被覆する。ただし、
接続パツド及びその近傍と素子値調整のための
レーザトリミングを行なう部分はこの皮膜を形
成しない。この皮膜は素子の保護とはんだの付
着を阻止する効果を有する。素子値調整が必要
である場合にはこの状態で例えばYAGレーザ
を用いて実施する。 Thereafter, the thin film integrated circuit is coated with an organic insulating film, such as a resist film. however,
This film is not formed on the connection pad and its vicinity and the area where laser trimming is performed for element value adjustment. This film has the effect of protecting the element and preventing solder adhesion. If element value adjustment is required, it is carried out in this state using, for example, a YAG laser.
前記有機絶縁性皮膜は先に述べた如く薄膜集
積回路にはんだが付着することを阻止する効果
を有するが、この阻止効果に弱点がある。 As mentioned above, the organic insulating film has the effect of preventing solder from adhering to the thin film integrated circuit, but there is a weakness in this blocking effect.
すなわち第2図aに示す如く、基板11上に
Ta膜12、NiCr膜13及びAu膜14からな
る導体パターンが形成され、これを有機絶縁性
皮膜15で選択的に被覆して、有機絶縁性皮膜
15で被覆されない導体パターン上にはんだ1
6を付着させるとき、はんだ16が有機絶縁性
皮膜15とAu膜14との界面に侵入する。こ
のはんだの侵入速度は例えば温度230〔℃〕の溶
融はんだについて0.3〔mm/sec〕に達する場合
がある。 That is, as shown in FIG. 2a, on the substrate 11
A conductive pattern consisting of a Ta film 12, a NiCr film 13, and an Au film 14 is formed, which is selectively covered with an organic insulating film 15, and solder 1 is placed on the conductive pattern not covered with the organic insulating film 15.
6, the solder 16 invades the interface between the organic insulating film 15 and the Au film 14. For example, the solder penetration speed may reach 0.3 [mm/sec] for molten solder at a temperature of 230 [° C.].
この溶融はんだの侵入を防止するために、本
発明においては、第2図bに示す如く、導体パ
ターンにNiCr膜13及びAu膜14を欠く溝1
7を設け、有機絶縁性皮膜15をこの溝17内
で終端させている。この溝17においては電気
的接続はTa膜12のみで行なわれて導体抵抗
が上昇するが、集積回路の特性に悪影響が現わ
れない配置が可能である。 In order to prevent this molten solder from entering, in the present invention, as shown in FIG.
7 is provided, and the organic insulating film 15 is terminated within this groove 17. In this groove 17, electrical connection is made only through the Ta film 12, and the conductor resistance increases, but an arrangement is possible that does not adversely affect the characteristics of the integrated circuit.
(iii) 副基板の接続準備方法
副基板に薄膜集積回路が形成されている場合
には、この薄膜集積回路の接続パツドにはんだ
付けのためにペーストを印刷した後に、はんだ
めつきを施した金属球を置き、はんだリフロー
を行つてバンプを形成する。(iii) How to prepare the sub-board for connection If a thin-film integrated circuit is formed on the sub-board, paste is printed on the connection pads of this thin-film integrated circuit for soldering, and then solder is applied. Place a metal ball and perform solder reflow to form bumps.
本実施例においては、前記金属球に銀(Ag)
を用いている。これはAgは電気伝導度及び熱
伝導度が最も良く、かつ外部からの応力を吸収
する柔軟性を有することによる。 In this example, the metal ball is made of silver (Ag).
is used. This is because Ag has the best electrical conductivity and thermal conductivity, and has the flexibility to absorb external stress.
このバンプの形成に金属球を用いることによ
つて、後に説明する副基板を主基板に接続した
状態における両基板の間隔を容易に制御するこ
とが可能となる。両基板を接続するはんだ付け
後のフラツクスの流液バブリングによる洗浄を
完全に行なうためには、この間隔が0.3〔mm〕以
上あることが必要であり、本実施例においては
球の直径を0.28〔mm〕として、必要かつ充分な
間隔を実現している。 By using metal balls to form the bumps, it becomes possible to easily control the distance between the two substrates when the sub-substrate, which will be described later, is connected to the main substrate. In order to completely clean the flux by flowing liquid bubbling after soldering which connects both boards, it is necessary that this interval is 0.3 [mm] or more, and in this example, the diameter of the sphere is 0.28 [mm] or more. mm], achieving the necessary and sufficient spacing.
なおはんだめつきを施した金属球を接続パツ
ド上に載置する手段としは、所要の位置に直径
0.5〔mm〕の孔開けを行なつたステンレス板を副
基板に密着させてこの孔に金属球を落し込み、
その状態で加熱を行なつている。 The method for placing the soldered metal ball on the connection pad is to
Place a stainless steel plate with a 0.5 mm hole in close contact with the sub-board, drop a metal ball into the hole,
Heating is performed in this state.
また副基板に厚膜集積回路が形成されている
場合には、主基板との接続位置にはんだペース
トを印刷して、その上に前記と同様に金属球を
用いるバンプを形成する。 If a thick film integrated circuit is formed on the sub-board, solder paste is printed at the connection position with the main board, and bumps using metal balls are formed thereon in the same manner as described above.
(iv) 副基板の主基板への接続方法
主基板には通常は厚膜回路が形成されるが、
この厚膜集積回路の副基板との接続位置及び半
導体集積回路もしくは個別部品の接続位置に、
はんだペーストの印刷を行なう。はんだ膜の厚
さは例えば0.2〔mm〕程度とする。(iv) How to connect the sub-board to the main board A thick film circuit is usually formed on the main board, but
At the connection position of this thick film integrated circuit with the sub-board and the connection position of the semiconductor integrated circuit or individual components,
Print the solder paste. The thickness of the solder film is, for example, about 0.2 [mm].
この接続位置に相対して前記準備を終了した
副基板及びその他の部品を搭載し、リフロー炉
によつてはんだ融着を行なう。このはんだリフ
ロー法ははんだが融着した際に、その表面張力
によつて搭載部品が接続パツドの中心方向に位
置が自ら修正される効果を有する。 The prepared sub-board and other parts are mounted opposite to this connection position, and solder fusion is performed in a reflow oven. This solder reflow method has the effect that when the solder is fused, the position of the mounted component is corrected by itself toward the center of the connection pad due to its surface tension.
主基板の表裏両面に副基板もしくは部品を接
続する場合には、第1面の前記接続が終了した
後に第2面のはんだペースト印刷及びリフロー
処理を行なう。この第2面のリフロー処理に際
して、第1面に接続された副基板及び部品等は
主基板の下面に位置してこれを接続するはんだ
も融解するが、第3図に例えば接続パツドが
0.5〔mm〕×0.5〔mm〕の寸法である場合の分布例
を示す如く融解はんだの表面張力が大きく、接
続パツドの面積と数を選択することによつて下
面に位置する副基板及び部品等を落下させるこ
となく保持して、第2面のはんだ接続が可能で
ある。 When connecting sub-boards or components to both the front and back surfaces of the main board, solder paste printing and reflow processing are performed on the second side after the connection on the first side is completed. During this reflow process on the second surface, the sub-board and components connected to the first surface are located on the bottom surface of the main board, and the solder that connects them is also melted.
As shown in the distribution example when the size is 0.5 [mm] x 0.5 [mm], the surface tension of the molten solder is large, and by selecting the area and number of connection pads, the sub-board and components located on the bottom surface can be The second side can be soldered while holding it without dropping it.
(v) 外部接続端子の接続等
以上説明した如くはんだ付け実装を終了した
主基板を例えばCO2レーザを用いて各モジユー
ルに分割する。(v) Connection of external connection terminals, etc. The main board that has been soldered and mounted as described above is divided into modules using, for example, a CO 2 laser.
外部接続端子の接続位置には先の副基板等の
搭載のためのはんだ膜形成の際にはんだ膜を形
成しておき、加熱空気吹付等の局部加熱法によ
つて外部接続端子のはんだ付けを行なう。次い
で所要の外装を施する。 A solder film is formed at the connection position of the external connection terminal when forming the solder film for mounting the sub-board etc., and the external connection terminal is soldered using a local heating method such as hot air blowing. Let's do it. Next, the required exterior is applied.
(vi) 主・副基板間の回路の分担
第4図はアクテイブフイルタ回路の1例を示
し、21は演算増幅器、C1乃至C4及びR1乃至
R6は何れも高精度、高安定を要求される薄膜
形成のコンデンサ素子及び抵抗素子である。(vi) Allocation of circuits between main and sub-boards Figure 4 shows an example of an active filter circuit, 21 is an operational amplifier, C 1 to C 4 and R 1 to
R6 is a thin film capacitor element and a resistor element that require high precision and high stability.
本発明によつてこのアクテイブフイルタを混
成集積回路装置として製造するに当つては、薄
膜集積回路によつて第4図に一点鎖線をもつて
示す範囲内の薄膜形成される抵抗およびコンデ
ンサの回路素子を相互に分離し開ループ状態で
副基板上に形成し、その他の回路部分を厚膜回
路によつて主基板上に形成する。主・副基板間
で上述の如く回路を分担して、主・副基板間の
回路接続を先に説明した製造方法によつて実施
するならば、副基板においては抵抗やコンデン
サの回路素子は開ループ状態になつているため
トリミング工程での抵抗値調整を高精度で実現
でき、かつ主・副基板間を接続する工程によつ
てアクテイブフイルタ回路の閉ループ化が同時
に実現されるとなど、高精度・高信頼度のアク
テイブフイルタ回路用集積回路装置を量産性良
く製造可能で安価な製品提供ができる。 In manufacturing this active filter as a hybrid integrated circuit device according to the present invention, circuit elements such as resistors and capacitors formed as thin films within the range indicated by the dashed line in FIG. are separated from each other and formed in an open loop state on a sub-substrate, and other circuit parts are formed on the main substrate using thick film circuits. If the circuits are shared between the main and sub boards as described above and the circuit connections between the main and sub boards are made using the manufacturing method described above, circuit elements such as resistors and capacitors will be open on the sub board. Because it is in a loop state, the resistance value can be adjusted with high precision in the trimming process, and the process of connecting the main and sub boards simultaneously creates a closed loop of the active filter circuit.・Highly reliable integrated circuit devices for active filter circuits can be mass-produced and can be provided at low cost.
更に、例えば第4図に破線をもつて示す如
く、抵抗素子R5に並列に接続される抵抗素子
R′5及び抵抗素子R6に並列に接続される抵抗素
子R′6を主基板上に厚膜抵抗素子として、薄膜
抵抗素子R5及びR6の例えば10倍程度以上の抵
抗値を与えて設けるならば、副基板及び演算増
幅器21をはんだ付けした後に演算増幅器21
の利得調整を厚膜抵抗素子R′5及びR′6のトリミ
ングによつて容易に実施することが可能であ
る。 Furthermore, a resistive element connected in parallel to the resistive element R5 , as shown by the broken line in FIG. 4, for example.
The resistance element R' 6 connected in parallel to R' 5 and the resistance element R 6 is formed as a thick film resistance element on the main substrate, and has a resistance value of, for example, about 10 times or more than that of the thin film resistance elements R 5 and R 6 . If provided, after soldering the sub-board and operational amplifier 21,
It is possible to easily adjust the gain by trimming the thick film resistive elements R'5 and R'6 .
前記厚膜抵抗素子R′5及びR′6は薄膜抵抗素子
R5及びR6に直列に挿入されてもよく、R5とR′5
及びR6とR′6相互間の抵抗値の配分を選択する
ことによつて、特性に支障を及すことはない。 The thick film resistive elements R'5 and R'6 are thin film resistive elements.
May be inserted in series with R 5 and R 6 , R 5 and R′ 5
And, by selecting the distribution of resistance values between R 6 and R′ 6 , the characteristics are not affected.
(vii) 主基板の1面のみに厚膜回路を形成した実施
例
第5図aは主基板の1面のみに厚膜回路が形
成された10次の低域アクテイブフイルタを示す
平面図、第5図bはそのX−Y断面を示す断面
図である。(vii) An example in which a thick film circuit is formed on only one side of the main substrate. FIG. 5b is a cross-sectional view showing the X-Y cross section.
主基板31はAgPd系厚膜導体を印刷し、そ
の上にはんだ付着防止のガラス層が印刷されて
いる。副基板32及び33にはTa系薄膜によ
る集積回路が形成されて、先に説明した如く3
4でAg球を介して主基板31の厚膜回路には
んだ付け接続されている。また演算増幅器35
はプラスチツクによるデユアル・インライン・
パツケージタイプである。なお36は厚膜回路
形成領域、37は外部接続端子である。 The main substrate 31 is printed with an AgPd-based thick film conductor, and a glass layer to prevent solder adhesion is printed thereon. Integrated circuits made of Ta-based thin films are formed on the sub-substrates 32 and 33, and as described above, 3
4, it is soldered and connected to the thick film circuit of the main board 31 via the Ag bulb. Also, the operational amplifier 35
Dual in-line made of plastic
It is a package type. Note that 36 is a thick film circuit forming area, and 37 is an external connection terminal.
本実施例においては、副基板の抵抗素子につ
いて先に述べた如く抵抗値調整を行なうことに
よつて、アクテイブフイルタの動作状態におけ
る抵抗値調整を行なうことなく、遮断周波数
0.5〔%〕以内に止めている。 In this embodiment, by adjusting the resistance value of the resistance element on the sub-board as described above, the cut-off frequency can be adjusted without adjusting the resistance value in the operating state of the active filter.
It is kept within 0.5 [%].
本実施例においては、装置の小形化について
は従来に比較して約7/8であるが、製造原価は
約2/3に低減される。 In this embodiment, the size of the device is reduced to about 7/8 compared to the conventional device, but the manufacturing cost is reduced to about 2/3.
(viii) 主基板の2面に厚膜集積回路を形成した実施
例
第6図a及びbは主基板の2面に厚膜集積回
路が形成された6次の低域アクテイブフイルタ
を示す平面図である。(viii) Embodiment in which thick film integrated circuits are formed on two sides of the main substrate Figures 6a and b are plan views showing a 6th-order low-pass active filter in which thick film integrated circuits are formed on two sides of the main board. It is.
主基板41はスルーホールによつて選択的に
接続された厚膜集積回路が2面に形成され、そ
の1面に演算増幅器45、他面に薄膜集積回路
が形成された基板42が先に説明した製造方法
によつて搭載されている。ただし、46及び4
6′は厚膜集積回路形成領域、47は外部接続
端子である。 The main substrate 41 has thick film integrated circuits selectively connected by through holes formed on two sides, and the substrate 42 has an operational amplifier 45 formed on one side and a thin film integrated circuit formed on the other side, which will be explained first. It is installed using a manufacturing method that However, 46 and 4
6' is a thick film integrated circuit forming area, and 47 is an external connection terminal.
本実施例においては、従来例に比較して約1/
2に小形化され、かつ製造原価も約3/4に低減さ
れている。 In this example, it is approximately 1/1 compared to the conventional example.
2, and the manufacturing cost has been reduced by about 3/4.
(g) 発明の効果
以上説明した如く本発明による、集積回路装置
の集積回路によつて形成される閉ループ回路を副
基板上に計画的に開ループ回路として形成し、主
基板上にはこの開ループ回路を閉成する回路部分
を形成して、高い信頼度を備えてかつ作業が容易
である金属球を介するはんだ付け接続によつて閉
ループが完成される構造の集積回路装置によつ
て、その小形化、集積規模の増大或いは薄膜集積
回路と厚膜集積回路との効果的な使いわけ等の基
板分割の効果を高い信頼性と経済性とをもつて容
易に実現することができる。(g) Effects of the Invention As explained above, according to the present invention, the closed loop circuit formed by the integrated circuit of the integrated circuit device is intentionally formed as an open loop circuit on the sub-board, and this open-loop circuit is formed on the main board. By means of an integrated circuit device, the closed loop is completed by a soldered connection through a metal ball, which forms the circuit part that closes the loop circuit and is highly reliable and easy to work with. The effects of substrate division, such as downsizing, increasing the scale of integration, or effectively using thin-film integrated circuits and thick-film integrated circuits, can be easily achieved with high reliability and economy.
また、必要に応じて、一部の抵抗素子を副基板
と主基板とに形成された各抵抗素子の並列又は直
列接続によつて実現することによつて、その抵抗
値調整が容易に行なわれて、前記効果が更に拡大
される。 In addition, if necessary, the resistance value can be easily adjusted by realizing some of the resistance elements by connecting each resistance element formed on the sub-board and the main board in parallel or in series. As a result, the above effect is further magnified.
第1図はアクテイブフイルタ混成薄膜集積回路
の従来例を示す平面図、第2図aは薄膜集積回路
の接続パツド近傍の従来例を示す断面図、第2図
bは本発明の実施例の同一部分を示す断面図、第
3図は接続パツドにおける融解はんだの表面張力
の効果を示す図、第4図はアクテイブフイルタの
例を示す回路図、第5図aは本発明の1実施例の
平面図、第5図bはその断面図、第6図a及びb
は他の実施例の2平面を示す平面図である。
図において、11は基板、12はTa膜、13
はNiCr膜、14はAu膜、15は絶縁性皮膜、1
6ははんだ、17は溝、21は演算増幅器、31
及び41は主基板、32,33及び42は副基
板、34はAg球を介するはんだ付け接続、35
及び45は演算増幅器、36,46及び46′は
厚膜集積回路形成領域、37及び47は外部接続
端子を示す。
FIG. 1 is a plan view showing a conventional example of an active filter hybrid thin film integrated circuit, FIG. 2 a is a sectional view showing a conventional example near the connection pad of the thin film integrated circuit, and FIG. 3 is a diagram showing the effect of the surface tension of molten solder on the connection pad, FIG. 4 is a circuit diagram showing an example of an active filter, and FIG. 5a is a plan view of one embodiment of the present invention. Figure 5b is a sectional view, Figures 6a and b
FIG. 3 is a plan view showing two planes of another embodiment. In the figure, 11 is a substrate, 12 is a Ta film, and 13 is a Ta film.
is NiCr film, 14 is Au film, 15 is insulating film, 1
6 is solder, 17 is a groove, 21 is an operational amplifier, 31
and 41 are main boards, 32, 33 and 42 are sub boards, 34 are soldered connections via Ag balls, 35
and 45 are operational amplifiers, 36, 46 and 46' are thick film integrated circuit forming regions, and 37 and 47 are external connection terminals.
Claims (1)
コンデンサの回路素子と演算増幅器を具備するア
クテイブフイルタ回路を構成する集積回路装置に
おいて、 厚膜形成された回路パターンを有する第1の基
板と薄膜形成された回路パターンを有する第2の
基板を設け、 前記第2の基板は前記回路素子が相互に閉ルー
プとならないように分離して前記回路パターンが
形成されると共に、該回路素子の素子値調整用の
トリミングが施されて製作され、 前記第1の基板は前記回路素子を閉ループに接
続するための接続パツドを有する前記回路パター
ンが形成されると共に、該第1の基板の一辺には
外部接続端子が接続しており、 前記第1の基板と前記第2の基板とが両者の前
記接続パツドを金属球を介してはんだ接続され、
また該第1の基板上の前記第2の基板が実装され
る領域以外に前記演算増幅器が搭載されることに
より、前記回路素子が前記第1の基板の前記回路
パターンにより閉ループにされて前記アクテイブ
フイルタ回路を構成することを特徴とした集積回
路装置。[Claims] 1. In an integrated circuit device constituting an active filter circuit comprising at least a plurality of film-formed resistor and capacitor circuit elements and an operational amplifier, a first circuit pattern having a thick film-formed circuit pattern is provided. A second substrate having a circuit pattern formed as a thin film on the substrate is provided, and the second substrate has the circuit pattern formed by separating the circuit elements so as not to form a closed loop with each other, and the circuit elements of the circuit element. The first substrate is manufactured by being trimmed for adjusting element values, and the first substrate is formed with the circuit pattern having connection pads for connecting the circuit elements in a closed loop, and the circuit pattern is formed on one side of the first substrate. is connected to an external connection terminal, and the first board and the second board are connected to each other by soldering the connection pads of both through a metal ball,
Furthermore, by mounting the operational amplifier in a region other than the area where the second board is mounted on the first board, the circuit elements are made into a closed loop by the circuit pattern of the first board and the active circuit elements are closed. An integrated circuit device comprising a filter circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4172283A JPS59167089A (en) | 1983-03-14 | 1983-03-14 | Integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4172283A JPS59167089A (en) | 1983-03-14 | 1983-03-14 | Integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59167089A JPS59167089A (en) | 1984-09-20 |
JPH0156556B2 true JPH0156556B2 (en) | 1989-11-30 |
Family
ID=12616305
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4172283A Granted JPS59167089A (en) | 1983-03-14 | 1983-03-14 | Integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59167089A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7989917B2 (en) * | 2002-01-31 | 2011-08-02 | Nxp B.V. | Integrated circuit device including a resistor having a narrow-tolerance resistance value coupled to an active component |
-
1983
- 1983-03-14 JP JP4172283A patent/JPS59167089A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS59167089A (en) | 1984-09-20 |
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