JPH0153814B2 - - Google Patents

Info

Publication number
JPH0153814B2
JPH0153814B2 JP57069225A JP6922582A JPH0153814B2 JP H0153814 B2 JPH0153814 B2 JP H0153814B2 JP 57069225 A JP57069225 A JP 57069225A JP 6922582 A JP6922582 A JP 6922582A JP H0153814 B2 JPH0153814 B2 JP H0153814B2
Authority
JP
Japan
Prior art keywords
voltage
bit
input voltage
differential
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57069225A
Other languages
Japanese (ja)
Other versions
JPS58186222A (en
Inventor
Tooru Kumasaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
Original Assignee
NEC Home Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd filed Critical NEC Home Electronics Ltd
Priority to JP6922582A priority Critical patent/JPS58186222A/en
Publication of JPS58186222A publication Critical patent/JPS58186222A/en
Publication of JPH0153814B2 publication Critical patent/JPH0153814B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/42—Sequential comparisons in series-connected stages with no change in value of analogue signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Description

【発明の詳細な説明】 本発明は、アナログ信号を２進化コードによつ
て示されるデイジタル信号へ変換する方式の改良
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in the method of converting an analog signal into a digital signal represented by a binary code.

従来のかゝるアナログ・デイジタル変換方式
は、デイジタル変換の分解能に応じた基準電圧を
設定し、これと与えられたアナログ信号の入力電
圧とを逐次比較するものとなつており、回路構成
が複雑化すると共に、回路構成の複雑化に応じて
入力電圧をデイジタル信号へ変換する所要時間が
大となる等の欠点を生じていた。 In the conventional analog-to-digital conversion method, a reference voltage is set according to the resolution of the digital conversion, and this is successively compared with the input voltage of the applied analog signal, making the circuit configuration complicated. At the same time, as the circuit configuration becomes more complex, the time required to convert the input voltage into a digital signal increases.

本発明は、従来のかかる欠点を根本的に排除す
る目的を有し、最大電圧E0を順々に２分した電
圧E1、E2……、Eoを１番目、２番目、……、ｎ
番目の基準電圧とし、入力電圧Ea1を１番目の最
上位ビツトからｎ番目の最下位ビツトに至るまで
のｎビツトのデイジタル値に変換する第１〜第ｎ
の処理を有するアナログ・デイジタル変換方式に
おいて、第１の処理においては、入力電圧Ea1と
１番目の基準電圧との第１の差電圧Ea1−E1が正
の場合には最上位ビツトである１番目のビツトを
「１」となし、第１の差電圧Ea1−E1が負の場合に
は１番目のビツトを「０」となし、第２の処理に
おいては、第１の差電圧が正の場合には第１の差
電圧を新たな入力電圧Ea2となし、第１の差電圧
が負の場合には入力電圧Ea1を新たな入力電圧Ea2
となし、入力電圧Ea2と２番目の基準電圧との第
２の差電圧Ea2−E2が正の場合には２番目のビツ
トを「１」となし、第２の差電圧Ea2−E2が負の
場合には２番目のビツトを「０」となし、第ｍ
（ｍ＝３、…、ｎ）の処理においては、第（ｍ−
１）の差電圧が正の場合には第（ｍ−１）の差電
圧を新たな入力電圧Eanとなし、第（ｍ−１）の
差電圧が負の場合には入力電圧Ea(n-1)を新たな入
力電圧Eanとなし、入力電圧Eanとｍ番目の基準
電圧との第ｍの差電圧Ean−Enが正の場合にはｍ
番目のビツトを「１」となし、第ｍの差電圧Ean
−Enが負の場合にはｍ番目のビツトを「０」と
なすようにした極めて効果的なアナログ・デイジ
タル変換方式を提供するものである。 The present invention has the purpose of fundamentally eliminating such drawbacks of the conventional art, and sequentially divides the maximum voltage E 0 into two halves to divide the voltages E 1 , E 2 . . . , E o into the first, second, . . . ,n
The input voltage E a1 is converted into an n-bit digital value from the first most significant bit to the nth least significant bit.
In the analog-to-digital conversion method having the following processing, in the first processing, if the first difference voltage E a1 −E 1 between the input voltage E a1 and the first reference voltage is positive, the most significant bit is A certain first bit is set to "1", and when the first difference voltage E a1 -E1 is negative, the first bit is set to "0", and in the second process, the first difference is set to "0". If the voltage is positive, the first differential voltage is set as the new input voltage E a2 ; if the first differential voltage is negative, the input voltage E a1 is set as the new input voltage E a2
If the second differential voltage E a2 −E 2 between the input voltage E a2 and the second reference voltage is positive, the second bit is set to “1” and the second differential voltage E a2 − If E 2 is negative, the second bit is set to 0, and the
In the (m=3,...,n) process, the (m-th
1) When the differential voltage is positive, the (m-1)th differential voltage is set as the new input voltage E an , and when the (m-1)th differential voltage is negative, the input voltage E a( n-1) as the new input voltage E an , and if the m-th difference voltage E an −E n between the input voltage E an and the m-th reference voltage is positive, m
The mth bit is set to "1", and the mth differential voltage E an
This provides an extremely effective analog-to-digital conversion method in which the m-th bit is set to "0" when -E n is negative.

以下、実施例を示す図によつて本発明の詳細を
説明するが、便宜上、まず本発明の原理から説明
する。 Hereinafter, details of the present invention will be explained with reference to figures showing examples, but for convenience, the principle of the present invention will be explained first.

第１図は、本発明の原理を示す図であり、最大
入力電圧E0を２分した基準電圧E1、同電圧E1を
２分した基準電圧E2、および、同電圧E2を２分
した基準電圧E3等の、２進化状に分割された複
数の基準電圧E1〜E3を設け、まず、同図Ａのと
おり、アナログ信号の入力電圧Eaと、最大の基
準電圧E1とを比較し、この結果、入力電圧Eaが
大であれば、２進化コードの最上位ビツトを送出
する反面、入力電圧Eaが小であれば、最上位ビ
ツトを送出しないものとしている。 FIG. 1 is a diagram showing the principle of the present invention, in which a reference voltage E 1 is obtained by dividing the maximum input voltage E 0 into two, a reference voltage E 2 is obtained by dividing the same voltage E 1 into two, and a reference voltage E 2 is obtained by dividing the maximum input voltage E 0 into two. First , as shown in FIG . As a result, if the input voltage Ea is large, the most significant bit of the binary code is sent out, whereas if the input voltage Ea is small, the most significant bit is not sent out.

たゞし、この場合は、Ea＞E1のため、最上位
ビツトが送出される。 However, in this case, since Ea>E 1 , the most significant bit is transmitted.

ついで、同図Ｂのとおり、Ea＞E1の場合は、
同図Ａにおける比較結果の差電圧Ea−E1と、基
準電圧E2とを比較し、差電圧Ea−E1が大であれ
ば、２進化コードの最上位ビツトにつぐ次位ビツ
トを送出する反面、差電圧Ea−E1が小であれば、
次位ビツトを送出しないものとしている。 Then, as shown in Figure B, if Ea>E 1 ,
Compare the difference voltage Ea-E 1 resulting from the comparison in A in the same figure with the reference voltage E 2 , and if the difference voltage Ea-E 1 is large, send out the next bit following the most significant bit of the binary code. On the other hand, if the differential voltage Ea−E 1 is small,
It is assumed that the next bit is not transmitted.

たゞし、この場合は、（Ea−E1）＜E2のため、
次位ビツトが送出されない。 However, in this case, since (Ea−E 1 )<E 2 ,
The next bit is not sent.

更に、（Ea−E1）＜E2の場合は、差電圧Ea−E1
を基準電圧E3と比較し、差電圧Ea−E1が大であ
れば、２進化コードの最下位ビツトを送出する反
面、差電圧Ea−E1が小であれば、最下位ビツト
を送出しないものとしている。 Furthermore, if (Ea−E 1 )<E 2 , the differential voltage Ea−E 1
is compared with the reference voltage E3 , and if the differential voltage Ea- E1 is large, the least significant bit of the binary code is sent out, whereas if the differential voltage Ea- E1 is small, the least significant bit is sent out. It is assumed that it will not be done.

たゞし、この場合は、（Ea−E1）＜E3のため、
最下位ビツトが送出される。 However, in this case, since (Ea−E 1 )<E 3 ,
The least significant bit is sent out.

したがつて、第１図の場合は、最下位ビツトが
論理値“１”、次位ビツトが“０”、最下位ビツト
が“１”となり、２進化コードの“101”が得ら
れるものとなり、これによつて入力電圧がデイジ
タル信号へ変換される。 Therefore, in the case of Figure 1, the least significant bit is a logical value of "1", the next bit is "0", and the least significant bit is "1", resulting in a binary code of "101". , thereby converting the input voltage into a digital signal.

なお、デイジタル信号のビツト数を増加させ、
デイジタル信号の分解能を向上させるには、差電
圧Ea−E1と基準電圧E3との差電圧（Ea−E1）−
E3を、基準電圧E3を２分した基準電圧と比較し、
上述と同様に操作すればよく、２進化状の基準電
圧を多く設ければ設ける程、分解能が向上する。 In addition, by increasing the number of bits of the digital signal,
To improve the resolution of digital signals, the difference voltage (Ea − E 1 ) − between the differential voltage Ea − E 1 and the reference voltage E 3
Compare E 3 with a reference voltage obtained by dividing the reference voltage E 3 into two,
The operation may be performed in the same manner as described above, and the more binary reference voltages are provided, the better the resolution will be.

第２図は、以上の原理に基づく具体的な回路構
成例を示すブロツク図であり、入力電圧Eaを入
力INから比較器CP1および減算作用を行なう差動
増幅器DA1の一方の入力へ与えると共に、入力電
圧Eaおよび差動増幅器DA1の出力を、アナログ
スイツチ等のスイツチSW1を介し、比較器CP2お
よび差動増幅器DA2の一方の入力へ与えており、
更に、スイツチSW1の出力および差動増幅器DA2
の出力を、スイツチSW2を介し、比較器CP3の一
方の入力へ与えている。 FIG. 2 is a block diagram showing a specific example of the circuit configuration based on the above principle, in which the input voltage Ea is applied from the input IN to the comparator CP 1 and one input of the differential amplifier DA 1 that performs the subtraction operation. At the same time, the input voltage Ea and the output of the differential amplifier DA 1 are applied to one input of the comparator CP 2 and the differential amplifier DA 2 via a switch SW 1 such as an analog switch.
Furthermore, the output of switch SW 1 and the differential amplifier DA 2
The output of is applied to one input of comparator CP 3 via switch SW 2 .

また、スイツチSW1は、比較器CP1の出力へ入
力の接続されたインバータIN1の出力により制御
され、スイツチSW2は、比較器CP2の出力へ入力
の接続されたインバータIN2の出力により制御さ
れるものとなつており、比較器CP1と差動増幅器
DA1との他方の入力には、基準電圧E1が与えら
れ、比較器CP2と差動増幅器DA2との他方の入力
には、基準電圧E2が与えられていると共に、比
較器CP3の他方の入力には、基準電圧E3が与えら
れている。 Further, switch SW 1 is controlled by the output of inverter IN 1 whose input is connected to the output of comparator CP 1 , and switch SW 2 is controlled by the output of inverter IN 2 whose input is connected to the output of comparator CP 2 . The comparator CP 1 and the differential amplifier
A reference voltage E 1 is given to the other input of the comparator CP 2 and the differential amplifier DA 2 , and a reference voltage E 2 is given to the other input of the comparator CP 2 and the differential amplifier DA 2 . A reference voltage E 3 is applied to the other input of 3 .

このため、入力INへ第１図Ａの入力電圧Eaが
与えられたものとすれば、比較器CP1の出力が
“１”となり、出力OUT1から最上位ビツトB2と
して送出されると共に、インバータIN1の出力は
“０”となり、スイツチSW1が図示の状態を保つ
ため、差動増幅器DA1における減算によつて得ら
れた差電圧Ea−E1が同増幅器DA1の出力に生じ、
これがスイツチSW1を介して比較器CP2と差動増
幅器DA2へ与えられ、比較器CP2の出力が“０”
となり、出力OUT2の次位ビツトB2も“０”とな
る。 Therefore, if the input voltage Ea shown in FIG. 1A is applied to the input IN, the output of the comparator CP 1 becomes "1" and is sent out from the output OUT 1 as the most significant bit B 2 . Since the output of inverter IN 1 becomes "0" and switch SW 1 maintains the state shown in the figure, the difference voltage Ea - E 1 obtained by subtraction in differential amplifier DA 1 is generated at the output of differential amplifier DA 1 . ,
This is given to comparator CP 2 and differential amplifier DA 2 via switch SW 1 , and the output of comparator CP 2 becomes “0”.
Therefore, the next bit B2 of the output OUT2 also becomes "0".

また、出力OUT2の“０”によりインバータ
IN2の出力は“１”となり、これによつてスイツ
チSW2が制御され、スイツチSW1を介する差電圧
Ea−E1を比較器CP3へ与えるため、比較器CP3の
出力が“１”となり、出力OUT3から最下位ビツ
トとして送出される。 In addition, the inverter is activated by “0” of the output OUT 2 .
The output of IN 2 becomes “1”, which controls the switch SW 2 and increases the differential voltage across the switch SW 1 .
Since Ea- E1 is applied to the comparator CP3 , the output of the comparator CP3 becomes "1" and is sent out from the output OUT3 as the least significant bit.

したがつて、この場合も、上述と同様に出力
OUT1〜OUT3から“101”の２進化コードが得
られる。 Therefore, in this case as well, the output is
A binary code of "101" is obtained from OUT 1 to OUT 3 .

なお、入力電圧Eaの値に応じてスイツチSW1，
SW2が制御されるため、出力OUT1〜OUT3から
は、入力電圧Eaの値に応じた状況の２進化コー
ドが送出される。 In addition, depending on the value of the input voltage Ea, the switch SW 1 ,
Since SW 2 is controlled, the outputs OUT 1 to OUT 3 output a binary code in a state corresponding to the value of the input voltage Ea.

たゞし、スイツチSW1，SW2として、制御入力
の“０”により動作するものを用いれば、インバ
ータIN1，IN2を省略してもよく、差動増幅器
DA1，DA2の代りに減算器等を用いても同様であ
り、所要のビツト数に応じて構成段数を定めれば
よい等、種々の変形が自在である。 However, if switches SW 1 and SW 2 are operated by control input "0", inverters IN 1 and IN 2 may be omitted, and the differential amplifier
The same effect can be achieved by using a subtracter or the like in place of DA 1 and DA 2 , and various modifications can be made, such as by determining the number of constituent stages depending on the required number of bits.

以上の説明により明らかなとおり、本発明によ
れば、構成が簡単であると共に、簡単な構成のた
め、デイジタル信号への変換速度が高く、かつ、
安価に製造できるものとなり、各種用途のアナロ
グ・デイジタル変換に用いて顕著な効果が得られ
る。 As is clear from the above description, according to the present invention, the configuration is simple, and because of the simple configuration, the conversion speed to digital signals is high, and
It can be manufactured at low cost, and can be used to achieve remarkable effects in analog-to-digital conversion for various purposes.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の原理を示す図、第２図は本発
明の実施例を示すブロツク図である。 CP1〜CP3……比較器、DA1，DA2……差動増
幅器、SW1，SW2……スイツチ、E1〜E3……基
準電圧、Ea……入力電圧、B3……最上位ビツト、
B2……次位ビツト、B1……最下位ビツト。 FIG. 1 is a diagram showing the principle of the invention, and FIG. 2 is a block diagram showing an embodiment of the invention. CP 1 to CP 3 ... Comparator, DA 1 , DA 2 ... Differential amplifier, SW 1 , SW 2 ... Switch, E 1 to E 3 ... Reference voltage, Ea ... Input voltage, B 3 ... most significant bit,
B2 ...Next bit, B1 ...Lowest bit.

Claims (1)

【特許請求の範囲】 １ 最大電圧E0を順々に２分した電圧E1、E2…
…、Eoを１番目、２番目、……、ｎ番目の基準
電圧とし、入力電圧Ea1を１番目の最上位ビツト
からｎ番目の最下位ビツトに至るまでのｎビツト
のデイジタル値に変換する第１〜第ｎの処理を有
するアナログ・デイジタル変換方式において、 第１の処理においては、入力電圧Ea1と１番目
の基準電圧との第１の差電圧Ea1−E1が正の場合
には最上位ビツトである１番目のビツトを「１」
となし、第１の差電圧Ea1−E1が負の場合には１
番目のビツトを「０」となし、 第２の処理においては、第１の差電圧が正の場
合には第１の差電圧を新たな入力電圧Ea2となし、
第１の差電圧が負の場合には入力電圧Ea1を新た
な入力電圧Ea2となし、入力電圧Ea2と２番目の基
準電圧との第２の差電圧Ea2−E2が正の場合には
２番目のビツトを「１」となし、第２の差電圧
Ea2−E2が負の場合には２番目のビツトを「０」
となし、 第ｍ（ｍ＝３、…、ｎ）の処理においては、第
（ｍ−１）の差電圧が正の場合には第（ｍ−１）
の差電圧を新たな入力電圧Eanとなし、第（ｍ−
１）の差電圧が負の場合には入力電圧Ea(n-1)を新
たな入力電圧Eanとなし、入力電圧Eanとｍ番目
の基準電圧との第ｍの差電圧Ean−Enが正の場合
にはｍ番目のビツトを「１」となし、第ｍの差電
圧Ean−Enが負の場合にはｍ番目のビツトを
「０」となす ことを特徴とするアナログ・デイジタル変換方
式。[Claims] 1. Voltages E 1 , E 2 , which are obtained by sequentially dividing the maximum voltage E 0 into two halves...
..., E o are the 1st, 2nd, ..., nth reference voltages, and the input voltage E a1 is converted into an n-bit digital value from the 1st most significant bit to the nth least significant bit. In the analog-to-digital conversion method having the first to nth processes, in the first process, when the first difference voltage E a1 −E 1 between the input voltage E a1 and the first reference voltage is positive; The first bit, which is the most significant bit, is set to “1”.
and 1 if the first differential voltage E a1 −E 1 is negative.
In the second process, if the first differential voltage is positive, the first differential voltage is set as a new input voltage E a2 ,
If the first differential voltage is negative, the input voltage E a1 is set as the new input voltage E a2 , and the second differential voltage E a2 −E 2 between the input voltage E a2 and the second reference voltage is positive. In this case, the second bit is set to “1” and the second differential voltage is
If E a2 −E 2 is negative, set the second bit to “0”.
In the m-th (m=3,...,n) process, if the (m-1)-th differential voltage is positive, the (m-1)-th
The difference voltage between is set as the new input voltage E an , and the (m-th
If the differential voltage in 1) is negative, the input voltage E a(n-1) is set as the new input voltage E an , and the m-th differential voltage E an − between the input voltage E an and the m-th reference voltage is set as the new input voltage E an −. The m-th bit is set to "1" when E n is positive, and the m-th bit is set to "0" when the m-th differential voltage E an -E n is negative. Analog/digital conversion method.
JP6922582A 1982-04-23 1982-04-23 Analog-digital converting system Granted JPS58186222A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6922582A JPS58186222A (en) 1982-04-23 1982-04-23 Analog-digital converting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6922582A JPS58186222A (en) 1982-04-23 1982-04-23 Analog-digital converting system

Publications (2)

Publication Number Publication Date
JPS58186222A JPS58186222A (en) 1983-10-31
JPH0153814B2 true JPH0153814B2 (en) 1989-11-15

Family

ID=13396566

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6922582A Granted JPS58186222A (en) 1982-04-23 1982-04-23 Analog-digital converting system

Country Status (1)

Country Link
JP (1) JPS58186222A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54154253A (en) * 1978-05-24 1979-12-05 Philips Nv Binary analoggtoodigital converter
JPS5723322A (en) * 1980-07-16 1982-02-06 Advantest Corp High speed analog-to-digital converter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54154253A (en) * 1978-05-24 1979-12-05 Philips Nv Binary analoggtoodigital converter
JPS5723322A (en) * 1980-07-16 1982-02-06 Advantest Corp High speed analog-to-digital converter

Also Published As

Publication number Publication date
JPS58186222A (en) 1983-10-31

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