JPH0151210B2 - - Google Patents
Info
- Publication number
- JPH0151210B2 JPH0151210B2 JP58131403A JP13140383A JPH0151210B2 JP H0151210 B2 JPH0151210 B2 JP H0151210B2 JP 58131403 A JP58131403 A JP 58131403A JP 13140383 A JP13140383 A JP 13140383A JP H0151210 B2 JPH0151210 B2 JP H0151210B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- resistance
- emitter
- differential amplifier
- amplifier circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 1
Landscapes
- Amplifiers (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は集積回路に属し、特にIC化された差
動増幅回路の製造条件に起因する利得のバラツキ
を抑える回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to integrated circuits, and particularly relates to a circuit for suppressing gain variations caused by manufacturing conditions of an IC-based differential amplifier circuit.
従来より差動増幅回路の利得はAv＝gmPL−
RL／reで表わされ、エミツタ抵抗reとコレクタ抵抗
RLにより決まる。またICの抵抗は従来より層抵
抗（正方形抵抗の抵抗値）を規準にしておりプロ
セスにより１種類から数種類の層抵抗を使い分け
て所要の抵抗値を実現している。 Conventionally, the gain of a differential amplifier circuit is A v = gmP L −
It is expressed as R L / re and is determined by the emitter resistance r e and the collector resistance R L. Furthermore, IC resistance has traditionally been based on layer resistance (the resistance value of a square resistor), and one to several types of layer resistance are used depending on the process to achieve the required resistance value.
さてIC内に高利得の差動増幅回路を構成しよ
うとすると当然RLとreの比を大きく取る事にな
る。ICの製造プロセス上数種類の層抵抗がある
場合にはRLとreの層抵抗が異なる事となる。しか
しRLとreの層抵抗が異なると各々の製造偏差によ
る素子値のバラツキは独立となり最悪製造偏差の
２乗で利得が影響を受ける。またこの影響を避け
る為無理をして一種の層抵抗を用いると製造偏差
の影響は無くなるのであるが、抵抗の形状（タ
テ、ヨコ比）が著しく異なる場合にはやはり抵抗
値が影響を受け利得が所要値からずれる事にな
る。 Now, if you try to configure a high-gain differential amplifier circuit within an IC, you will naturally have to increase the ratio of R L and r e . If there are several types of layer resistance due to the IC manufacturing process, the layer resistances of R L and r e will be different. However, if the layer resistances of R L and r e differ, variations in element values due to manufacturing deviations become independent, and in the worst case, the gain is affected by the square of the manufacturing deviation. Also, if you go out of your way to use a type of layered resistor to avoid this effect, the influence of manufacturing deviation will disappear, but if the shape of the resistor (vertical and horizontal ratio) is significantly different, the resistance value will still be affected and the gain will be affected. will deviate from the required value.
本発明は前述の様な欠点を緩和する為に抵抗比
が必要な差動増幅回路において鋭エミツタ抵抗を
Ｙ結線から△結線へＹ→△変換し変換前の抵抗値
に対して数倍の値にし、同種の抵抗にてコレクタ
抵抗及びエミツタ抵抗を実現するとともに所定の
抵抗比が取れる様にし製造条件により層抵抗値が
変化しても利得変動が生じない様にした差動増幅
回路を提供するものである。 In order to alleviate the above-mentioned drawbacks, the present invention converts the sharp emitter resistance from Y to △ connection in a differential amplifier circuit that requires a resistance ratio to a value several times the resistance value before conversion. To provide a differential amplifier circuit in which a collector resistance and an emitter resistance are realized using the same type of resistance, a predetermined resistance ratio can be obtained, and gain fluctuation does not occur even if the layer resistance value changes due to manufacturing conditions. It is something.
本発明の構成は、集積化されコレクタ抵抗とエ
ミツタ抵抗を有する差動増幅回路において該差動
増幅回路を製造するプロセス上で製造される層抵
抗が２種類以上ある場合、各エミツタ抵抗のトラ
ンジスタ側の端をもう一本の抵抗で接続し、等価
的にＹ−△変換を施し、各エミツタ抵抗の値を高
くしコレクタ抵抗と同じ層抵抗にてエミツタ抵抗
を形成する事を特徴としている。 The configuration of the present invention is such that when there are two or more types of layered resistors manufactured in the process of manufacturing the differential amplifier circuit in an integrated differential amplifier circuit having a collector resistor and an emitter resistor, the transistor side of each emitter resistor is It is characterized in that the end of the resistor is connected to another resistor, equivalently subjected to Y-Δ conversion, the value of each emitter resistor is increased, and the emitter resistor is formed with the same layer resistance as the collector resistor.
すなわち、１対のトランジスタのコレクタとエ
ミツタにそれぞれ集積化された抵抗が接続されて
なる差動増幅回路において、この１対のトランジ
スタのエミツタにそれぞれ一端が接続されたエミ
ツタ抵抗と、エミツタ間に接続された抵抗と、エ
ミツタ抵抗のそれぞれの他端が結線されて接続さ
れた電流源を有し、コレクタに接続された抵抗
と、エミツタに接続された抵抗とが同種の層抵抗
によつて構成されるものである。 In other words, in a differential amplifier circuit in which integrated resistors are connected to the collectors and emitters of a pair of transistors, an emitter resistor whose one end is connected to the emitters of the pair of transistors, and an emitter connected between the emitters. The resistor connected to the collector and the resistor connected to the emitter are configured by the same type of layer resistance. It is something that
次に本発明の実施例について図面に参照して説
明する。第３図は本発明の実施例を表わし、トラ
ンジスタ３と３′、コレクタ抵抗（RC）１と１′、
エミツタ抵抗（RE）１０′，１０″、トランジス
タ３，３′のエミツタ間に接続される抵抗１０、
そして定電流源４より成る。第１図は差動増幅回
路の基本形であり、そのトランジスタのエミツタ
抵抗を△結線したものが第３図となる。第２図は
第１図に対しＹ→△変換とする為にRE２及び
２′の交点より定電流源の間に新たに仮想抵抗RE
９を追加した従来例である。但しRE９を追加す
ることによりＹ→△変換が可能となるがRE9×
1(A)分だけ定電流源側の電圧余裕が減少する事に
注意を要する。第３図のREは下式に算出できる。 Next, embodiments of the present invention will be described with reference to the drawings. FIG. 3 shows an embodiment of the invention, in which transistors 3 and 3', collector resistors (RC) 1 and 1',
Emitter resistor (RE) 10', 10'', resistor 10 connected between the emitters of transistors 3, 3',
It consists of a constant current source 4. FIG. 1 shows the basic form of a differential amplifier circuit, and FIG. 3 shows the one in which the emitter resistors of the transistors are connected in Δ. Figure 2 shows a new virtual resistance RE between the constant current source and the intersection of RE2 and 2' in order to perform Y→△ conversion compared to Figure 1.
This is a conventional example in which 9 is added. However, by adding RE9, Y→△ conversion becomes possible, but RE9×
Please note that the voltage margin on the constant current source side decreases by 1 (A) . RE in Figure 3 can be calculated using the formula below.
RE10＝（２×RE2×RE2
＋RE2×RE9）／RE9
RE10′＝（２×RE2×RE2
＋RE2×RE9）／RE2
RE10″＝（２×RE2×RE2
＋RE2×RE9）／RE2′
仮想抵抗RE９は定電流源側の電圧余裕による
適当な値が設定されるが、RE2＝RE9と仮定する
とRE10＝RE10′＝RE10″＝３×RE2となり初期の
RE２に対し３倍の値となる。よつてRCとREの
抵抗比が大きい高利得回路においてもその抵抗比
が１／３となり同じ層抵抗でRC、REを製造でき
利得所要値を得ることができる。 RE10=(2×RE2×RE2 +RE2×RE9)/RE9 RE10′=(2×RE2×RE2 +RE2×RE9)/RE2 RE10″=(2×RE2×RE2 +RE2×RE9)/RE2′ The virtual resistance RE9 is constant. An appropriate value is set depending on the voltage margin on the current source side, but assuming RE2 = RE9, RE10 = RE10' = RE10'' = 3 x RE2, and the initial
The value is three times that of RE2. Therefore, even in a high-gain circuit where the resistance ratio between RC and RE is large, the resistance ratio becomes 1/3, making it possible to manufacture RC and RE with the same layer resistance and obtain the required gain value.
本発明は以上説明した様にエミツタ抵抗REを
Ｙ→△変換し、初めの値より数倍大きい値にする
事により、抵抗用の層抵抗が何種類もあるプロセ
スにおいても同種の層抵抗を使用して、エミツタ
抵抗およびコレクタ抵抗を形成できる。そのため
製造偏差の影響を受けない高利得差動増幅回路を
得る事ができる。という効果がある。 As explained above, the present invention converts the emitter resistance RE from Y to △ and makes it several times larger than the initial value, so that the same type of layer resistance can be used even in processes where there are many types of layer resistance. Thus, an emitter resistor and a collector resistor can be formed. Therefore, a high gain differential amplifier circuit that is not affected by manufacturing deviations can be obtained. There is an effect.
第１図は本発明を実施していない通常の差動増
幅回路、第２図は仮想抵抗を挿入した回路また第
３図は本発明を実施しREを△変換した差動増幅
回路を示す。
１，１′……コレクタ抵抗RC、２，２′……エ
ミツタ抵抗RE、３，３′……トランジスタ、４…
…定電流源、５，５′……入力、６，６′……出
力、７，８……直流電源、９……仮想エミツタ抵
抗、１０，１０′，１０″……△変換後エミツタ抵
抗。
FIG. 1 shows a normal differential amplifier circuit in which the present invention is not implemented, FIG. 2 shows a circuit in which a virtual resistor is inserted, and FIG. 3 shows a differential amplifier circuit in which the present invention is implemented and RE is Δ-converted. 1, 1'...Collector resistance RC, 2, 2'...Emitter resistance RE, 3, 3'...Transistor, 4...
... Constant current source, 5, 5'... Input, 6, 6'... Output, 7, 8... DC power supply, 9... Virtual emitter resistance, 10, 10', 10''... Emitter resistance after △ conversion .
Claims (1)
有する差動増幅回路において、該差動増幅回路を
構成する１対のトランジスタのエミツタ間を１本
の第１の抵抗にて結び、該１対のトランジスタの
前記エミツタに１本ずつの第２および第３の抵抗
をそれぞれ接続し、該第２および第３の抵抗の夫
夫の先端を共通に定電流源に接続し、該第１、第
２および第３の抵抗が前記エミツタ抵抗として用
いられ、該エミツタ抵抗と前記コレクタ抵抗とを
同種の層抵抗を有する抵抗にて構成したことを特
徴とする集積回路。1. In a differential amplifier circuit having an integrated collector resistor and emitter resistor, a first resistor connects the emitters of a pair of transistors constituting the differential amplifier circuit, and A second and a third resistor are respectively connected to the emitters of the emitters, and the ends of the second and third resistors are commonly connected to a constant current source. An integrated circuit characterized in that a third resistor is used as the emitter resistor, and the emitter resistor and the collector resistor are composed of resistors having the same type of layer resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13140383A JPS6022814A (en) | 1983-07-19 | 1983-07-19 | Integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13140383A JPS6022814A (en) | 1983-07-19 | 1983-07-19 | Integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6022814A JPS6022814A (en) | 1985-02-05 |
| JPH0151210B2 true JPH0151210B2 (en) | 1989-11-02 |
Family
ID=15057156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13140383A Granted JPS6022814A (en) | 1983-07-19 | 1983-07-19 | Integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6022814A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5234183A (en) * | 1975-09-12 | 1977-03-15 | Toshiba Mach Co Ltd | Synchronous feed control system |
| JPS5744310A (en) * | 1980-06-26 | 1982-03-12 | Rca Corp | Televison intermediate frequency amplifying system |
-
1983
- 1983-07-19 JP JP13140383A patent/JPS6022814A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5234183A (en) * | 1975-09-12 | 1977-03-15 | Toshiba Mach Co Ltd | Synchronous feed control system |
| JPS5744310A (en) * | 1980-06-26 | 1982-03-12 | Rca Corp | Televison intermediate frequency amplifying system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6022814A (en) | 1985-02-05 |
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