JP2897522B2 - Current mirror circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current mirror circuit, and more particularly, to a current mirror circuit which operates so as to limit an output current with respect to an input current exceeding a certain value.

[0002]

2. Description of the Related Art A conventional current mirror circuit of this type includes NPN transistors 22 and 23 and a PNP transistor 24 corresponding to a current input terminal 39 and a current output terminal 40, as shown in FIG. And resistance 2
5, 26 and 27. Such a conventional example is disclosed in Japanese Utility Model Application Publication No. 61-456.
There is an output current limiting type current mirror circuit as disclosed in Japanese Patent Application Publication No.

[0003] In FIG 4, the input current at the current input terminal 39 of the current mirror circuit and I _i, NPN
Assuming that the resistances R ₂₆ and R ₂₇ of the resistors 26 and 27 connected to the respective emitters of the transistors 22 and 23 have the same value R, the voltage appearing between the base and the emitter of the NPN transistor 24 is I _i × R. . _Assuming that the voltage between the base and the emitter of the NPN transistor 24 at the time when the NPN transistor 24 starts to turn on is V _BEi , when V _BEi > I _i × R, N _BE
The PN transistor 24 is turned off, so that the operation as a normal current mirror circuit is not affected.
Therefore, if the grounded emitter current gain β of the NPN transistors 22 and 23 is sufficiently large, and if the error of the current mirror circuit due to the grounded emitter current gain β is ignored, the following equation is established with the output current at the current output terminal as _Io One.

I _o = I _i ... (1) Next, when V _BEi <I _i × R, the NPN transistor 24 is turned on, whereby the current The state will affect the operation of the mirror circuit. In this state, the collector current I _c of the NPN transistor 24 flows through the resistor 25. Therefore, the resistance value of the resistor 25 is set to R ₂₅
Then, the base voltage of the NPN transistor 23 decreases due to the voltage drop due to I _c × R ₂₅ , whereby the current value of the collect current I _c of the NPN transistor 23 forming the output current of the current mirror circuit decreases. In this state, according to the input current I _i of the current mirror circuit increases, the output current I of the companion no current mirror circuit to the output current I _i of the current mirror circuit increases
_o decreases conversely. That is, the following equation holds.

I _o <I _i ... (2) It should be _{noted that} the relationship between the input current I _i and the output current I _{o in} the current mirror circuit is represented by a graph. FIG.
Is shown in

[0006]

In the conventional output current control type current mirror circuit described above, a resistor is inserted between the bases of a pair of NPN transistors constituting the current mirror circuit. In addition, there is a disadvantage that the current accuracy in the current mirror circuit deteriorates due to the voltage drop due to the base current flowing through the resistor.

[0007]

A current mirror circuit according to the present invention is a current mirror circuit including a first transistor on a current input side and a second transistor on a current output side, wherein an emitter is connected to the current mirror circuit. Connected to corresponding current input terminals, the base is commonly connected to the collector and base of the first transistor, and the base of the second transistor, and the collector is connected to the emitter of the second transistor. A third transistor having a conductivity type opposite to that of the first and second transistors, a first resistor connected between an emitter and a base of the third transistor, and a predetermined transistor connected to an emitter of the first transistor. A second power supply connected to the first power supply;
And a third resistor connected between the emitter of the second transistor and the first power supply.

The current mirror circuit is configured as a multi-output type current mirror circuit including a plurality of transistors of the same conductivity type as the first and second transistors as transistors on the current output side. , And a plurality of resistors individually connected between the emitter and the first power supply, the third transistor is configured as a multi-collector, and the collector of the multi-collector is individually connected to the emitters of the plurality of transistors. The base may be connected to the current input terminal, the emitter may be commonly connected to the bases of the first transistor and the second transistor, and the collector may be connected to a predetermined second power supply. And a fourth transistor having the same conductivity type as the first and second transistors. Configuration may be.

[0009]

Next, the present invention will be described with reference to the drawings.

FIG. 1A is a circuit diagram showing a first embodiment of the present invention. As shown in FIG. 1A, in the present embodiment, NPN transistors 1 and 2, a PNP transistor 3, and resistors 4, 5 and 6 are connected to a current input terminal 31 and a current output terminal 32, respectively. This is an example of a case where the present invention is applied to a Widlar type current mirror circuit.

In FIG. 1A, an input current at a current input terminal 31 of the current mirror circuit is represented by I _i ,
Assuming that the resistance value of the resistor 4 is R ₄ , the NPN transistor 3
The voltage appearing between the emitter and the base when is in the off state is I _i × R ₄ . And NPN transistor 3
The voltage between the emitter and the base when the transistor starts to turn on is V _BE3
Assuming that the grounded emitter current gain β of the NPN transistors 1 and 2 is sufficiently large and the error of the current mirror circuit due to the grounded emitter current gain β can be ignored, V _BE3 > I _i × R _{In the case of 4,} the NPN transistor 3 is turned off, and does not affect the operation as a normal current mirror circuit. Therefore, if the grounded emitter current gain β of the NPN transistors 1 and 2 is sufficiently large, and ignoring the error of the current mirror circuit due to the grounded emitter current gain β, the output current at the current output terminal 32 is _defined as _Io .
The following equation holds between the input and output currents.

I _o = I _i ... (1) Next, when V _BE3 <I _i × R ₄ , the NPN transistor 3 is turned on. some of the input current I _i flows as a collector current in the NPN transistor 3, this current flows to ground via a resistor 6, NP
The emitter potential of the N transistor 2 is raised. As a result, the collector current of the NPN transistor 2 is decreased, the output current I _o which is output from the current output terminal 32 is as given by the following equation, is limited to less current than the input current I _i.

I _o <I _i ... (2) In this state, the larger the input current I _i is, the larger the collector current of the NPN transistor 3 is. becomes, thereby the voltage drop across the resistor R ₆ is further increased, and to Yuku also increases the emitter voltage of the NPN transistor 2, the collector current of the NPN transistor 2 is decreased more and more. A graph showing the relationship between the input current Ii and the output current Io in this state is shown in FIG. 3, as in the conventional example, as shown in FIG. Is a characteristic that is limited.
In this state, the collector current I _c of the NPN transistor 24 flows through the resistor 25. Therefore, the resistance 2
Assuming that the resistance value of R5 is R ₂ , the base voltage of NPN transistor 23 decreases due to the voltage drop due to I _c × R ₂ , thereby reducing the collect current I _c of NPN transistor 23 forming the output current of the current mirror circuit. The current value decreases. In this state, according to the input current I _i of the current mirror circuit increases, the output current I _o of the companion no current mirror circuit to the output current I _i of the current mirror circuit is increased, decreased conversely. That is, the following equation holds.

I _o <I _i ... (2) It should be _{noted that} the relationship between the input current I _i and the output current I _{o in} the current mirror circuit is represented by a graph. FIG.
Is shown in

Next, a second embodiment of the present invention will be described.

FIG. 1B is a circuit diagram showing a second embodiment of the present invention. As shown in FIG. 1B, in the present embodiment, NPN transistors 7, 8, and 10 and P are provided corresponding to the current input terminal 33 and the current output terminals 34 and 35.
NP transistor 9 and resistors 11, 12, 13 and 1
4 is an example in which the current mirror circuit has a plurality of outputs. That is, as another NPN transistor for current output, an NPN transistor 10 whose base is commonly connected to the NPN transistor and the bases of the transistors 7 and 8 is provided, and a resistor 14 is connected between the emitter and the ground point. I have. Also,
The NPN transistor 9 is of the multi-collector type, with its collector connected to NPN transistors 8 and 10 respectively.
Are connected.

Now, when the NPN transistor 9 is turned on, its emitter current is distributed to the respective collectors, and the respective collector currents flow to the ground via the resistors 13 and 14, and the respective NPN transistors 8
And the emitter potential of 10 are increased. This allows
The collector currents of NPN transistors 8 and 10 decrease, so that the current values output from current output terminals 34 and 35 are limited. Relationship between the output photoelectric I _o corresponding to the input current I _i is the Tori seen in FIG. In addition,
Similarly, when the PNP transistor 9 is configured as a multi-output type multi-connector and the number of NPN transistors for current output is increased to increase the number of outputs to three or more,
It goes without saying that the present invention is applied.

Next, FIG. 3 shows an embodiment in which the present invention is applied to a base current compensation type current mirror circuit. As shown in FIG. 3, in the present embodiment, NPN transistors 15, 16 and 18 correspond to a current input terminal 36, a current output terminal 38 and a power supply terminal 37.
, A PNP transistor 17, and resistors 19, 20, and 21. As is clear from the comparison with the first embodiment shown in FIG.
The connection between the base and the collector of the transistor 1 is removed, the collector is connected to the power supply terminal 37, and the base is connected to the PN.
An NPN transistor 18 connected to the emitter of the P transistor 17 and having the emitter connected to the bases of the NPN transistors 15 and 16 is added.

This embodiment is an example in which the present invention is applied to the base current compensation type current mirror circuit as described above in order to reduce the error of the current mirror circuit due to the base current in the first embodiment. Other operations are the same as those of the first embodiment in FIG. 1, and the description thereof is omitted. Although the present embodiment is an example of a one-output type, it goes without saying that the present embodiment can be applied to a multi-output type current mirror circuit by combining the circuits shown in FIG.

In each of the above embodiments, N
The present invention is also effectively applied to the current mirror circuit configured by alternately replacing the PN transistor and the PNP transistor with each other and exchanging the high potential side and the low potential side of the supply power supply voltage, and the above is applied. It goes without saying that the function can be obtained.

[0021]

As described above, according to the present invention, the emitter is connected to the current input terminal, the resistor inserted into the current input circuit of the current mirror circuit is connected between the emitter and the base, and the collector is connected to the current input terminal. By providing a transistor connected to the emitter of the current output transistor of the mirror circuit and controlling the emitter potential of the current output transistor in accordance with the current input amount, the operating characteristics of the current mirror circuit due to the base current of the output transistor This has the effect of preventing deterioration of the device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing first, second and third embodiments of the present invention.

FIG. 2 is a circuit diagram showing a conventional example.

FIG. 3 is a diagram showing input / output current characteristics of a current mirror circuit.

[Explanation of symbols]

1, 2, 7, 8, 10, 15, 16, 18, 22, 23
NPN transistor 3, 9, 17, 24 PNP transistor 4-6, 12-14, 19-21, 25-27 Resistance

Claims (3)

(57) [Claims] In a current mirror circuit including a first transistor on a current input side and a second transistor on a current output side, an emitter is connected to a current input terminal corresponding to the current mirror circuit, and a base is connected to the current mirror. The first and second transistors commonly connected to a collector and a base of a first transistor and a base of the second transistor, and a collector connected to an emitter of the second transistor;
A third transistor of a conductivity type opposite to that of the third transistor, a first resistor connected between an emitter and a base of the third transistor, an emitter of the first transistor and a predetermined first power supply, And a third resistor connected between the emitter of the second transistor and the first power supply. 2. The current mirror circuit is configured as a multi-output type current mirror circuit including a plurality of transistors of the same conductivity type as the first and second transistors as transistors on the current output side. , And a plurality of resistors individually connected between the emitter and the first power supply, the third transistor is configured as a multi-collector, and the collector of the multi-collector is individually connected to the emitters of the plurality of transistors. The current mirror circuit according to claim 1, which is connected. 3. A base is connected to the current input terminal,
A fourth transistor having the same conductivity type as the first and second transistors, having an emitter commonly connected to the bases of the first and second transistors and a collector connected to a predetermined second power supply; The current mirror circuit according to claim 1, further comprising: