JPH0150127B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the configuration of a switched capacitor amplifier circuit composed of a switch, a capacitor, and an active element. The present invention relates to the configuration of a multistage amplifier circuit using a method of inputting an amplified signal again.

FIG. 1 shows a conventional multistage amplifier circuit. Conventional multistage amplifier circuits generally have a power supply voltage of V _dd , a bias resistance R _go , a load resistance R _do , and an active element Q _o (n
is an integer proportional to the number of stages) constitutes a single stage amplifier circuit, which is connected in multiple stages by a coupling capacitor C _{c (o-1)} . Also, the signal to be amplified is
It enters from the signal input terminal V _io , is amplified and output from the signal output terminal V _put . For this reason, conventional multi-stage amplifier circuits do not have the function of holding the output signals of each stage, and therefore require active elements, bias resistors, load resistors, and coupling capacitors proportional to the number of stages. For this reason, in order to configure a multistage amplifier circuit, the number of elements is extremely large, and when integrating it, it is difficult to create resistors that are accurate and meet the needs. Because it is difficult to make a capacitor with a large capacity, it is not suitable for integration. Further, in the conventional multi-stage amplifier circuit, each stage is connected by a coupling capacitor, so that it is impossible to amplify a DC signal.

In the multi-stage amplifier circuit according to the present invention, by using a switched capacitor circuit, the active elements operate intermittently and the output signals of each stage can be held, so that the active elements can be used effectively in time. By holding the amplified signal and inputting it again, 1
With active elements and a set of peripheral elements,
This makes it possible to configure a multi-stage amplifier circuit. Therefore, compared to conventional multi-stage amplifier circuits, it is possible to expect lower power consumption, significantly reduce the circuit scale, and eliminate the need for large capacitance capacitors, making it suitable for integration. Since it is not used, it is also possible to amplify the DC signal.

Next, as an embodiment of the present invention, a four-stage amplifier circuit will be taken as an example and explained with reference to the drawings.

FIG. 2 shows a multistage amplifier circuit according to an embodiment of the present invention. The multistage amplifier circuit of this embodiment includes double contact switches S ₁ , S ₂ , S ₃ , S ₄ , S ₅ , S ₆ , single contact switches S ₇ ,
S ₈ , S ₉ , S ₁₀ , S ₁₁ , S ₁₂ , S ₁₃ , capacitor C _g1 ,
It is composed of C _g2 , C _d1 , C _d2 , C _b1 , C _b2 , and a field effect transistor (FET) Q. S ₁ is a switch that changes whether to apply the input signal to the gate of Q or the amplified signal to the gate of Q. The movable contact of S ₁ is applied to the gate of Q, and one fixed contact is applied to the gate of Q. , and the other fixed contact is connected to the movable contacts S ₅ and S ₁₃ to the input terminal. _S2 ,
The circuit composed of S ₃ , C _g1 , and C _g2 is a bias circuit, and the movable contact of S ₂ is connected to one terminal of C _{g1 .}
The other terminal of is grounded. One fixed contact of _S2 is connected to the gate of Q, and the other fixed contact is grounded. The moving contact of S ₃ is connected to one terminal of C _g2 , and the other terminal of C _g3 is
Grounded. One fixed contact of _S3 is connected to the gate of Q, and the other fixed contact is grounded.
The circuit composed of S ₄ , S ₅ , S ₆ , S ₉ , S ₁₀ , C _d1 , and C _d2 is a load circuit. One terminal of C _d1 is S ₄
The other terminal is connected to the movable contact of S ₉ and the fixed contact of S ₈ . One terminal of C _d2 is connected to the S ₆ moving contact, the other terminal is connected to the S ₁₀
The movable contact of S ₁₁ is connected to the fixed contact.
One fixed contact of _S4 is connected to the source of Q and one fixed contact of _S6 , and the other fixed contact is connected to one fixed contact of _S5 . The fixed contacts S ₉ and S ₁₀ are connected to the power supply voltage V _dd . One fixed contact of _S5 is connected to one fixed contact of _S4 , and the other fixed contact is connected to one fixed contact of _S6 . The circuit composed of S ₇ , S ₈ , S ₁₁ , S ₁₂ , C _b1 , and C _b2 is a circuit that removes the bias voltage generated in the amplifier circuit. One terminal of C _b1 is connected to the fixed contact of S ₇ and the movable contact of S ₈ , and the other terminal is grounded. The movable contact of S ₇ is bias voltage
Connected to V _b . One terminal of C _b2 is S ₁₁
The movable contact of S ₁₂ is connected to the fixed contact, and the other terminal is grounded. The movable contact of S ₁₂ is
Connected to bias voltage V _b . _S13 is a switch that takes out the output signal of the multistage amplifier circuit, and the movable contacts are the movable contact of _S5 and one fixed contact of _S1 .
The fixed contact is connected to the output terminal.

Next, the operation of the multistage amplifier circuit of the present invention will be explained. The multi-stage amplifier circuit of the present invention operates with a four-phase clock, and by turning on the switch according to the clock phase corresponding to the number written on each switch in the figure, it can be operated using the conventional multi-stage amplifier circuit shown in FIG. The operation is equivalent to . In the bias circuit composed of S ₂ , S ₃ , C _g1 , and C _g2 in Figure 2, if the period at which S ₂ and S ₃ are turned on is T, then the equivalent resistance R _g is expressed by the following formula. .

R _g = 1/C _g1 T = -1/C _g2 T (1) A circuit composed of S ₄ , S ₅ , S ₆ , S ₉ , S ₁₀ , C _d1 and C _d2 has S in the load circuit. ₄ , _S5 , _S6 , _S9 ,
If the period for turning on S ₁₀ is T, its equivalent resistance R _d is expressed by the following equation.

R _d = 1/C _d1 T = 1/C _d2 T (2) Next, the output signal from the FET, that is, C _d1 ,
Alternatively, the voltage V ₀ generated across C _d2 is expressed by the following equation, where V _i is the signal voltage applied to the gate of the FET, k is the amplifier circuit per stage, and V _bb is the bias voltage generated by the amplifier circuit.

V _p =kV _i +V _dd −V _bb (3) Here, if V _dd −V _bb =V _b , then V _p =kV _i +V _b (4). Since the required output signal is kV _i in the second equation, it is necessary to subtract V _b from the FET output signal V _p . The circuit that subtracts this V _b is S ₇ , S ₈ ,
This circuit is composed of S ₁₁ , S ₁₂ , C _b1 , and C _b2 . The signal flow of the multistage amplifier circuit shown in Fig. 2 is such that the input signal V io is amplified in the first phase of the clock, and the input signal V _io is amplified in the first phase of the clock.
The amplified signal is inputted again in the fourth phase, and taken out as the output signal V _put in the next first phase.

The multi-stage amplifier circuit according to the present invention is configured and operates as described above, so the configuration can be simplified, and
Moreover, it is possible to reduce power consumption, is suitable for integration into an integrated circuit, and can also be amplified from a DC signal.

[Brief explanation of drawings]

FIG. 1 shows a conventional four-stage amplifier circuit composed of resistors and capacitors, and FIG. 2 shows a multi-stage amplifier circuit according to an embodiment of the present invention. Q...transistor, S ₁ , S ₂ , S ₃ , S ₄ , S ₅ ,
S ₆ , S _{7 , S 8} , S ₉ , S ₁₀ , S ₁₁ , S ₁₂ , S ₁₃ ... Switch, C _{g1 ,} C _g2 , C _b1 , C _b2 , C _d1 , C _d2 ... Capacitor.

Claims (1)

[Claims] 1. A switched capacitor amplifier circuit, comprising: an active element that amplifies a signal; a plurality of bias circuits each connected to the input side of the active element and made up of switched capacitors; and an output side of the active element. After inputting a signal, the plurality of bias circuits and the plurality of load circuits are connected to the plurality of load circuits connected to the plurality of switch capacitors, and the plurality of load circuits are switched to store and circulate the signal, and the active element is multistage amplified. 1. A multistage amplifier circuit comprising: switching means for performing the following steps.