JPH01500785A - integrated circuit - Google Patents

integrated circuit

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Publication number
JPH01500785A
JPH01500785A JP61504865A JP50486586A JPH01500785A JP H01500785 A JPH01500785 A JP H01500785A JP 61504865 A JP61504865 A JP 61504865A JP 50486586 A JP50486586 A JP 50486586A JP H01500785 A JPH01500785 A JP H01500785A
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circuit
integrated circuit
monitor
voltage
pattern
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ピツト,マイケル ジェフリイ
マッコウヘン,ダニエル ヴィンセント,
Original Assignee
ザ ゼネラル エレクトリック カンパニー,ピー.エル.シー.
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Publication of JPH01500785A publication Critical patent/JPH01500785A/en
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/32Monitoring with visual or acoustical indication of the functioning of the machine
    • G06F11/324Display of status information
    • G06F11/327Alarm or error message display
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/14Modifications for compensating variations of physical values, e.g. of temperature
    • H03K17/145Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるため要約のデータは記録されません。 (57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 集積回路 この発明は集積回路に関する。[Detailed description of the invention] integrated circuit This invention relates to integrated circuits.

近年の集積回路は大規模集積回路に傾いてきている。In recent years, integrated circuits have been leaning toward large-scale integrated circuits.

このような大規模集積回路では、回路が破損する前に、回路内の個々の成分のパ ラメータを使用中に変更する余地が少ない。このような破損は、例えば、回路内 の導電トラックの電気移動(Electromigration)によりトラッ クの短絡又は開路が生じると、起きる。この破損はトラックに過剰電流が流れる と、生じる。また、トラックの横断面積が少し変化しても、回路の破損までの時 間が大幅に短縮する。回路の破損につながると考えられるパラメータ変化の別な 例は、ゲート酸化物中のイオン拡散、ホットキャリヤトラッピングや電離性放射 線の効果による限界電圧の不安定性、例えば回路内のMO8装置のそれである。In these large scale integrated circuits, the performance of individual components within the circuit must be controlled before the circuit is damaged. There is little room to change parameters while in use. Such damage can be caused by e.g. Tracking is achieved by electromigration of conductive tracks. Occurs when a short or open circuit occurs. This damage causes excessive current to flow through the track. And it happens. In addition, even if the cross-sectional area of the track changes slightly, it will take a long time to break the circuit. The time will be significantly reduced. Other parameter changes that may lead to circuit damage Examples are ion diffusion in gate oxides, hot carrier trapping and ionizing radiation. Limit voltage instability due to line effects, for example that of MO8 devices in the circuit.

多数の小規模集積回路からなるシステムでは、これら小規模集積回路は簡単に試 験でき、交換できるが、これは一つ以上の大規模回路からな゛るシステムではか なり難しい。In systems consisting of many small integrated circuits, these small integrated circuits are easily tested. can be tested and replaced, but this may not be possible in systems consisting of one or more large circuits. It's difficult.

本発明の目的は、この問題のない集積回路を提供することにある。The object of the invention is to provide an integrated circuit that does not have this problem.

本発明によれば、集積回路の動作停止状態を続けながら、集積回路の動作停止萌 に、破損するようにしたモニター回路と、このモニター回路が破損した時期を表 示する手段を備えた集積回路が提供される。According to the present invention, while the operation of the integrated circuit continues to be stopped, the operation of the integrated circuit is stopped. shows the monitor circuit that caused the damage and when this monitor circuit broke. An integrated circuit is provided with means for indicating.

本発明による一つの特定集積回路では、モニター回路は導電パターンと、このパ ターンを流れる電流の電流密度が集積回路の動作停止時よりも高くなるように該 パターンに電流を流す手段とを備えている。このようなモニター回路は、電気移 動により集積回路導電部の破損をモニターするのに使用できる。In one particular integrated circuit according to the invention, the monitor circuit includes a conductive pattern and a The current density of the current flowing through the turns is higher than when the integrated circuit is stopped. and means for passing a current through the pattern. Such a monitor circuit is It can be used to monitor damage to integrated circuit conductive parts due to

このような集積回路では、上記表示手段がパターンに開路が生じた時期を表示す る。あるいは、上記表示手段は、パターンと隣接導電体との間に短絡が生じた時 期を表示してもよい。In such an integrated circuit, the display means indicates when an open circuit occurs in the pattern. Ru. Alternatively, the above-mentioned indicating means may indicate when a short circuit occurs between the pattern and an adjacent conductor. The period may also be displayed.

本発明による別な集積回路では、モニター回路は電界効実装置、この装置に電気 的に応力を加える手段及び該装置の限界電圧と基準電圧を比較する手段からなる 。In another integrated circuit according to the invention, the monitor circuit is a field effect device, which and means for comparing the limiting voltage of the device with a reference voltage. .

特表千1−500785 (2) このようなモニター回路は電界効実装置における限界電圧の変化をモニターする のに使用できる。Special Table Sen1-500785 (2) Such a monitor circuit monitors changes in the limiting voltage in a field effect device. Can be used for.

以下、例示のみを目的とした添付図面について、本発明による2つの集積回路を 説明していく。In the following, two integrated circuits according to the invention are illustrated with reference to the accompanying drawings, which are for illustrative purposes only. I'll explain.

第1図は、第1集積回路に組み込んだモニター回路を示す概略図であり、 第2図は、モニター回路のスイッチを第!の構成配置にした、第2集積回路に組 み込んだモニター回路を示す概略図であり、そして 第3図は、モニター回路のスイッチを第2の構成配置にした、第2図のモニター 回路を示す図である。FIG. 1 is a schematic diagram showing a monitor circuit incorporated in a first integrated circuit; Figure 2 shows the monitor circuit switch. Assembled into the second integrated circuit with the configuration and arrangement of 1 is a schematic diagram illustrating a built-in monitor circuit, and Figure 3 shows the monitor of Figure 2 with the monitor circuit switches arranged in a second configuration. It is a diagram showing a circuit.

まづ最初に第1図について説明すると、第1回路に組み込んだモニター回路は電 気移動による集積回路内の金属トラックの考えられる破損をモニターするように なっている。モニター回路は、2つの給電レール5.7間に設けた抵抗器3に直 列接続した、ストライプIの形を取る金属テストパターンからなる。このテスト パターンは集積回路に、回路内の他の導電トラックと同時に形成して、処理変化 によるトラック肉厚の変化がストライプIに反映されるようにする。モニター回 路を組み込んだ集積回路の動作時に、ストライプIを流れる電流の電流密度が、 通常集積回路内の蒸着パターンの最大定格値とされている値より大きくなるよう に抵抗器3の値を設定する。ストライプlを部分的に取り囲むU字状の導電トラ ック9を、集積回路内の最大推奨ライン間隔に等しい距離だけストライプlから 離間する。トラック9は、抵抗値が抵抗器3より幾分大きい抵抗器11によって 給電レール7に接続する。First, to explain Figure 1, the monitor circuit built into the first circuit is a power source. to monitor possible damage to metal tracks in integrated circuits due to air migration. It has become. The monitor circuit is connected directly to the resistor 3 placed between the two feed rails 5.7. It consists of a metal test pattern in the form of stripes I connected in columns. this test Patterns are formed on integrated circuits at the same time as other conductive tracks in the circuit, allowing for processing changes. The change in track thickness caused by this change is reflected in the stripe I. monitor times During operation of an integrated circuit incorporating stripe I, the current density of the current flowing through stripe I is Normally, the value is larger than the maximum rating value of the vapor deposition pattern in the integrated circuit. Set the value of resistor 3 to . U-shaped conductive track that partially surrounds stripe l 9 from stripe l by a distance equal to the maximum recommended line spacing in the integrated circuit. Separate. The track 9 is connected by a resistor 11 whose resistance value is somewhat larger than that of the resistor 3. Connect to power supply rail 7.

集積回路の動作時に、それぞれアースについて測定した、ストライプIと抵抗器 3との間にある点の電圧■!及び導電トラック上にある点の電圧■2を連続モニ ターする。ストライプの抵抗が抵抗器3の抵抗よりかなり大きいので、例えば電 気移動によりストライプIに開路が生じて、電圧Vlがレール7のそれに近くな るまで、電圧■lはレール5のそれに近い状態になっている。通常、警告回路( 図示せず)は集積回路に接続するか、これに組み込んでおくが、この回路は、モ ニターされた電圧Vtがストライプ1間路かに生じたこと示した時に、電圧Vl に応答して警告を発する。また、この回路は、集積回路が、場合によって致命的 な破損を起こしそうな場合に、早期警告を発する。次に、高い信頼性が要求され る場合には、集積回路を組み込んだシステムから集積回路を完全に取り外すなど の適当な措置を取ればよい。Stripe I and resistor, each measured with respect to earth, during operation of the integrated circuit Voltage at a point between 3■! Continuously monitor the voltage at a point on the conductive track tar. Since the resistance of the stripe is much larger than the resistance of resistor 3, e.g. Air movement causes an open circuit in stripe I, causing voltage Vl to be close to that of rail 7. The voltage ■l is close to that of the rail 5 until it reaches the rail 5. Usually the warning circuit ( (not shown) are connected to or incorporated into an integrated circuit; When the monitored voltage Vt appears across stripe 1, the voltage Vl issue a warning in response. In addition, this circuit is designed to Provides an early warning when serious damage is likely to occur. Second, high reliability is required. If the integrated circuit Appropriate measures should be taken.

警告回路はまた、通常はゼロであるが、電気移動によりストライプ1が電気的に トラック9に接続される場合には、レール5上の電圧値に近付く電圧v2にも応 答する。The warning circuit also indicates that stripe 1 is electrically When connected to track 9, it also responds to voltage v2 approaching the voltage value on rail 5. answer.

なお、テストパターンは、考えられる破損モードをシミュレートするために、多 くの形を取ることができる。Note that the test pattern is designed to simulate possible failure modes. It can take the form of

例えば、下のポリシリコンライン上に段部を、又は境界接触ホールを備えたもの でもよい。For example, with a step on the underlying polysilicon line or with border contact holes. But that's fine.

また、電気移動による金属トラックの考えられる破損に応答するようになったモ ニター装置は、場合によっては、ストライプの開路又は短絡のみに応答するよう に構成してもよい。Also, the motor now responds to the possible damage of the metal track due to electromobility. The monitor device may be designed to respond only to opens or shorts in the stripe. It may be configured as follows.

次に、第2図について説明すると、第2の集積回路は集積回路内に設けたMOS トランジスタ中の限界電圧不安定性をモニターするように構成しである。第2図 に示すように、モニタートランジスタ2目よ2つの給電レール23.25の間に 接続する。このトランジスタ2Iのゲートはレール23を介して二位置スイッチ 27の可動接点及び固定接点に接続し、そしてトランジスタのドレインはバイア ス抵抗器29を介してレール23に接続し、そしてスイッチ27の他方の固定接 点はドレインと抵抗器29との間にある点30に接続する。また、直列に接続し た、抵抗値が同じある2つの抵抗器31,33はレール23.25間に接続する 。第2の三路スイッチ35の固定接点は2つの抵抗器31.33の接続部間に接 続し、可動接点はコンデンサ37の一方の電極に接続し、そしてスイッチ35の 他方の固定接点はトランジスタ21のドレインと抵抗器29との間jこある接点 30Jこ接続する。コンデンサ37の第2電極は一つのnチャネル39及び一つ のpチャネル41M0S)ランジスタのゲート電極に接続し、nチャネルトラン ジスタ39のドレインはレール25に接続L、nチャネルトランジスタ41のソ ースはレール23に接続し、そして残りのソース及びドレインは一緒に接続する 。また、コンデンサの第2電極はスイッチ43を介して、トランジスタ39のソ ース及びトランジスタ4Iのドレインを接続する導体に接続して、第2図に示す ように閉じる。この点で電圧特表平1−500785(3) v3をモニターする。Next, to explain FIG. 2, the second integrated circuit is a MOS provided within the integrated circuit. The circuit is configured to monitor critical voltage instability in the transistor. Figure 2 As shown in the figure, monitor transistor 2 is connected between the two power supply rails 23 and 25. Connecting. The gate of this transistor 2I is connected to a two-position switch via a rail 23. 27 movable contacts and fixed contacts, and the drain of the transistor is connected to the via and the other fixed connection of switch 27 to rail 23 through resistor 29. The point connects to a point 30 between the drain and resistor 29. Also, connect in series In addition, two resistors 31 and 33 with the same resistance value are connected between rails 23 and 25. . The fixed contacts of the second three-way switch 35 are connected between the connections of the two resistors 31 and 33. The movable contact is connected to one electrode of the capacitor 37, and the movable contact is connected to one electrode of the capacitor 37, and the movable contact is connected to one electrode of the The other fixed contact is a contact located between the drain of the transistor 21 and the resistor 29. Connect 30J. The second electrode of the capacitor 37 has one n-channel 39 and one connected to the gate electrode of the p-channel 41M0S) transistor, and connected to the gate electrode of the n-channel transistor. The drain of the resistor 39 is connected to the rail 25, and the drain of the n-channel transistor 41 is connected to the rail 25. the source is connected to rail 23, and the remaining sources and drains are connected together. . Further, the second electrode of the capacitor is connected to the solenoid of the transistor 39 via the switch 43. 2 to the conductor connecting the ground and the drain of transistor 4I, as shown in FIG. Close like this. In this regard, Voltage Special Table Hei 1-500785 (3) Monitor v3.

スイッチ27.35及び43はいずれも同期した伝達ゲート回路からなる。集積 回路の動作時、その時間の約90%、スイッチは第2図に示す位置にセットされ ている。従つて、モニタートランジスタ21のゲートはレール23に直接接続し て、最大ゲートバイアスを与える。Switches 27, 35 and 43 both consist of synchronized transmission gate circuits. accumulation Approximately 90% of the time when the circuit is operating, the switch is in the position shown in Figure 2. ing. Therefore, the gate of monitor transistor 21 is directly connected to rail 23. to give maximum gate bias.

出力電圧v3はレール23.25間の電位差のほぼ半分、即ち第2図に示すV− REFであり、この電圧までコンデンサ37が充電する。第3図に示すスイッチ 位置にスイッチを入れると、モニタートランジスタ21のゲートがドレインに接 続し、抵抗器29b(十分高い値をもつと仮定するなら、その電圧がトランジス タの電圧V・Tの付近で落ち着く。従って、スイッチ35を第3図に示す位置に 入れ、そしてスイッチ43を開くと、コンデンサ37に印加される電圧がV−T −V−REFだけ上昇する。V−TがV−REFより大きいと、トランジスタ4 Iのみが導電性になり、電圧v3がレール25のそれになる。ところが、■・T がV−REFよい小さいと、トランジスタ39のみが導電性になり、電圧v3が レール23のそれになる。この場合、限界電圧V−TがV−REFより小さいと 、警告回路(図示せず)が■3の値を使用して、警告信号を発する。The output voltage v3 is approximately half the potential difference between the rails 23.25, i.e. V- as shown in FIG. REF, and the capacitor 37 charges up to this voltage. Switch shown in Figure 3 When the switch is turned on, the gate of the monitor transistor 21 is connected to the drain. Then resistor 29b (assuming it has a sufficiently high value, the voltage It settles down around the voltage V・T. Therefore, the switch 35 is placed in the position shown in FIG. When the switch 43 is turned on and the switch 43 is opened, the voltage applied to the capacitor 37 becomes V-T. -V-REF increases. When V-T is greater than V-REF, transistor 4 Only I becomes conductive and the voltage v3 becomes that of rail 25. However, ■・T When V-REF is small, only transistor 39 becomes conductive and the voltage v3 becomes It will be that of Rail 23. In this case, if the limit voltage VT is smaller than V-REF, , a warning circuit (not shown) uses the value of ■3 to issue a warning signal.

なお、V−REFの値は、抵抗器31,33の値を相対的に選択すれば、容易に 設定できる。また、一般的には、本発明による集積回路に少なくとも4つの、考 えられる限界電圧不安定性をモニターするモニター回路を組み込むと、nチャネ ル限界電圧の最大・最小値に対する変化及びpチャネル限界電圧の最大・最小値 に対する変化を検出できる。Note that the value of V-REF can be easily determined by selecting the values of resistors 31 and 33 relatively. Can be set. It is also generally expected that an integrated circuit according to the invention will have at least four considerations. Incorporating a monitor circuit to monitor the potential voltage instability Changes in maximum and minimum values of p-channel limit voltage and maximum and minimum values of p-channel limit voltage Changes in can be detected.

以上、電気移動又は限界電圧変化によって生じると考えられる破損をモニターす ることに関してモニター回路を説明してきたが、本発明によるモニター回路を組 み込んだ本発明による集積回路では、回路の破損につながる恐れのあるパラメー タにおいて多くの変更が可能である。The above explains how to monitor damage that may be caused by electrical migration or critical voltage changes. The monitor circuit according to the present invention has been described. In the integrated circuit according to the present invention, there are no parameters that may lead to damage to the circuit. Many changes are possible in the data.

国際調査報告 m5−+wll@MI A#Ma14 NL PCT/GB 95/QQ547international search report m5-+wll@MI A#Ma14 NL PCT/GB 95/QQ547

Claims (5)

【特許請求の範囲】[Claims] 1.集積回路の動作停止状態を続けながら、集積回路の動作停止前に、破損する ようにしたモニター回路(1、3、9、11)と、このモニター回路(1、3、 9、11)が破損した時期を表示する手段とを備えたことを特徴とする集積回路 。1. Damage occurs before the integrated circuit stops operating while the integrated circuit continues to stop operating. This monitor circuit (1, 3, 9, 11) and this monitor circuit (1, 3, 9, 11) means for displaying when the item was damaged. . 2.モニター回路(1、3、9、11)が導電パターン(1)を流れる電流の電 流密度が集積回路の動作停止時より大きくなるように設けた導電パターン(1) を備えている、請求の範囲第1項に記載の集積回路。2. The monitor circuit (1, 3, 9, 11) detects the current flowing through the conductive pattern (1). Conductive pattern (1) provided so that the current density is higher than when the integrated circuit is not operating An integrated circuit according to claim 1, comprising: 3.上記表示手段がパターン(1)に開路が生じた時期を表示する、請求の範囲 第2項に記載の集積回路。3. Claims wherein the display means displays the time when an open circuit occurs in pattern (1). The integrated circuit according to paragraph 2. 4.上記表示手段がパターン(1)と隣接導電体(9)との間に短絡が生じた時 期を表示する、請求の範囲第2項に記載の集積回路。4. When the above display means causes a short circuit between the pattern (1) and the adjacent conductor (9) 3. The integrated circuit according to claim 2, which displays a period. 5.モニター回路が電界効果装置(21)、この装置(21)に電気的に応力を 加える手段(30)及び該装置の限界電圧と基準電圧(v・ref)を比較する 手段からなる、請求の範囲第1項に記載の装置。5. A monitoring circuit electrically applies stress to the field effect device (21). Comparing the limiting voltage of the applying means (30) and the device with a reference voltage (vref) Apparatus according to claim 1, comprising means.
JP61504865A 1986-09-17 1986-09-17 integrated circuit Pending JPH01500785A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/GB1986/000547 WO1988002123A1 (en) 1986-09-17 1986-09-17 Integrated circuits

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JPH01500785A true JPH01500785A (en) 1989-03-16

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US4243937A (en) * 1979-04-06 1981-01-06 General Instrument Corporation Microelectronic device and method for testing same
JPS602775B2 (en) * 1981-08-28 1985-01-23 富士通株式会社 Large-scale integrated circuit with monitor function and its manufacturing method
US4528505A (en) * 1983-03-29 1985-07-09 Motorola, Inc. On chip voltage monitor and method for using same

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Publication number Publication date
WO1988002123A1 (en) 1988-03-24
EP0281552A1 (en) 1988-09-14

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