EP0281552A1 - Integrated circuits - Google Patents

Integrated circuits

Info

Publication number
EP0281552A1
EP0281552A1 EP19860905368 EP86905368A EP0281552A1 EP 0281552 A1 EP0281552 A1 EP 0281552A1 EP 19860905368 EP19860905368 EP 19860905368 EP 86905368 A EP86905368 A EP 86905368A EP 0281552 A1 EP0281552 A1 EP 0281552A1
Authority
EP
European Patent Office
Prior art keywords
integrated circuit
circuit
monitor
pattern
indication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19860905368
Other languages
German (de)
French (fr)
Inventor
Michael Geoffrey Pitt
Daniel Vincent Mccaughan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co PLC
Original Assignee
General Electric Co PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co PLC filed Critical General Electric Co PLC
Publication of EP0281552A1 publication Critical patent/EP0281552A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
    • G06F11/324—Display of status information
    • G06F11/327—Alarm or error message display
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
    • H03K17/145—Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches

Definitions

  • This invention relates to integrated circuits.
  • large scale integrated circuits reduce the margins for in- service variations of the parameters of the individual components within the circuits, before failure of the circuit.
  • Such failures may occur, for example due to electromigration in conductive tracks within the circuits causing open or short circuits of the tracks this occurring when excessive current passes through a conductive track.
  • Small changes in cross-sectional areas of the tracks may also drastically reduce the time to failure of the circuit.
  • Another example of a possible variation leading to failure of the circuit is that of threshold voltage instabilities, for example MOS devices within the circuit due to ion diffusion in the gate oxide, hot carrier trapping, or the effects of ionising radiation. Whilst in systems made up of a large number of smaller integrated circuits, the smaller integrated circuits can be easily tested and replaced, this is more difficult in systems made up of one or more large scale integrated circuits.
  • an object of the present invention to provide an integrated circuit wherein this problem is alleviated.
  • an integrated circuit including a monitor circuit designed to fail prior to the rest of the integrated circuit whilst allowing the rest of the integrated circuit to function, and means for providing an indication of when the monitor circuit has failed.
  • the monitor circuit includes a conductive pattern and means for providing current through the pattern such that the current density through the pattern is greater than for the rest of the integrated circuit.
  • a monitor circuit finds application monitoring possible failures of conductive portions within the integrated circuit due to electromigration.
  • the means for providing an indication provides the indication when an open circuit has occurred in the pattern.
  • the means for providing an indication provides the indicat ⁇ ion when a short circuit has occurred between the pattern and an adjacent conductor.
  • the monitor circuit comprises a field effect device, means for electrically stressing the device, and means for comparing the threshold voltage of the device to a reference voltage.
  • Such a monitor circuit finds application in monitoring possible variations of threshold voltages in field effect devices.
  • Figure 1 is a schematic diagram of a monitor circuit incorporated in the first integrated circuit
  • Figure 2 is a schematic diagram of a monitor circuit incorporated in the second integrated circuit with the monitor circuit's switches in a first configuration
  • Figure 3 shows the monitor circuit of Figure 2 with its switches in a second configuration.
  • the monitor circuit incorporated in the first integrated circuit to be described is designed to monitor possible failure of metallic tracks within the integrated circuit due to electromigration.
  • the monitor circuit comprises a metallic test pattern in the form of a stripe indicated as 1 connected in series with a resistor 3 across two supply rails 5, 7.
  • the test pattern is formed on the integrated circuit at the same time as the other conductive tracks within the circuit such that variations in track thickness due to processing variations will be reflected in the stripe 1.
  • the value of the resistor 3 is chosen such that in operation of the integrated circuit incorporating the monitor circuit, the current density through the stripe 1 is greater than the value usually regarded as a maximum rating for a metallisation pattern within the integrated circuit.
  • a U- shaped conductive track 9 Spaced from the stripe 1 by a distance equivalent to the minimum recommended line spacing in the integrated circuit.
  • the track 9 is connected to the supply rail 7 by a resistor 11 having a somewhat greater value of resistance than that of the resistor 3.
  • the voltages V1 of a point between the stripe 1 and resitor 3, and V2 of a point on the conductive track 5 each measured with respect to earth are continuously monitored.
  • the resistance of the stripe will be much less than the resistance of the resistor 3
  • the voltage V1 will remain close to that of the rail 5 until an open circuit in the stripe 1 , due to for example -H- electromigration, occurs, in which case the voltage V1 will become close to that of the rail 7.
  • a warning circuit (not shown) will normally be either connected to or incorporated in the integrated circuit which is responsive to the voltage V1 to provide a warning when the monitored voltage V1 indicates that an open circuit has occurred In the stripe 1 , this then providing an early warning that the integrated circuit is likely to fail before the integrated circuit actually fails which may, in some circumstances be catastrophic. Appropriate action can then be taken such as total removal of the integrated circuit from the system in which it is incorporated where high reliability is required.
  • the warning circuit will also be responsive to the voltage V2 which normally will be zero, but will approach the value of the voltage on the rail 5 in the event that electromigration causes the stripe 1 to become electrically connected to the track 9. It will be appreciated that the test pattern may take many forms in order to simulate possible failure modes, e.g. it may include steps over under ⁇ lying polysilicon lines, or border contact holes.
  • a monitoring circuit designed to be responsive to possible failure through elctromigration of metallic tracks need, in some circumstances, .be only responsive to open circuits or short circuits in the test stripe.
  • the second integrated circuit to be described includes a monitor circuit designed to monitor possible threshold voltage instabilities in MOS transistors within the integrated circuit.
  • a monitor transistor 21 is connected as shown in this figure across two supply rails 23, 25, the gate of the transistor 21 being connected to the rail 23 via a moveable contact and a fixed contact of a two position switch 27, and the drain of the transistor being connected to the rail 23 via a biassing resistor 29, with the other fixed contact of the switch 27 being connected to a point 30 between the drain and the resistor 29.
  • a series arrangement of two similarly valued resistors 31, 33 are also connected across the rails 23, 25.
  • a fixed contact of a second two way switch 35 is connected to a point between the junction of the two resistors 31, 33, the moveable contact of the switch being connected to one electrode of a capacitor 37, the other fixed contact of the switch 35 being connected to the point 30 between the drain of the transistor 21 and the resistor 29.
  • the second electrode of the capacitor 37 is connected to the gate electrodes of one n channel 39 and one p channel 41 MOS transistors, the drain of the n channel transistor 39, being connected to the rail 25, the source of the p channel transistor 41 being connected to the rail 23, and the remaining source and drain being connected together.
  • the second electrode of the capacitor is also connected via a switch 43, shown closed in Figure 2 to the conductor connecting the source of the transistor 39 and the drain of the transistor 41, the voltage V3 being monitored at this point.
  • the switches 27, 35 and 43 all consist of transmission gate circuits clocked synchronously.
  • the switches are set in the positions shown in Figure 2.
  • the gate of the monitor transistor 21 is thus directly connected to the rail 23 so as to provide a maximum gate bias.
  • the output voltage V3 will be approximately half the potential difference across the rails 23, 25 i.e. V RE as indicated in the figure, the capacitor 37 charging up to this voltage.
  • the gate of the monitor transistor 21 is connected to the drain which will settle to around the threshold voltage V ⁇ 0 f the transistor, assuming the resistor 29 is of sufficiently high value.
  • the voltage applied to the capacitor 37 will thus increase by V_--V_, p _- as switch 35 is switched to the position shown in Figure 3, and switch 43 is opened.
  • V- is greater than V-.-.-. then only transistor 41 will be conductive, and the voltage V3 will be that of the line 25. If however V-_ is less than V-.-,-., then only transistor 39 will be conductive, and the voltage V3 will be that of the line 23.
  • a warning circuit (not shown) may then use the value of V3 to give a warning signal if the threshold voltage V ⁇ is less than -,_---. It will be appreciated that the value of
  • monitoring circuits described herebefore by way of example monitor possible failures due to electro- migration, or variation of threshold voltages
  • integrated circuits in accordance with the invention incorporating monitoring circuits in accordance with the invention incorporating monitoring circuits for monitoring many other variations in parameters likely to lead to circuit failure are also possible.

Abstract

Un circuit intégré comprend un circuit moniteur (1, 3) destiné à défaillir avant le reste du circuit intégré, tout en permettant au reste du circuit intégré de continuer à fonctionner. Un circuit d'avertissement indique quand le circuit moniteur (1, 3) tombe en panne.An integrated circuit includes a monitor circuit (1, 3) for failure before the rest of the integrated circuit, while allowing the rest of the integrated circuit to continue to operate. A warning circuit indicates when the monitor circuit (1, 3) has failed.

Description

Integrated Circuits
This invention relates to integrated circuits. In recent years there has been a tendency towards large scale integrated circuits. Such large scale integrated circuits reduce the margins for in- service variations of the parameters of the individual components within the circuits, before failure of the circuit. Such failures may occur, for example due to electromigration in conductive tracks within the circuits causing open or short circuits of the tracks this occurring when excessive current passes through a conductive track. Small changes in cross-sectional areas of the tracks may also drastically reduce the time to failure of the circuit. Another example of a possible variation leading to failure of the circuit is that of threshold voltage instabilities, for example MOS devices within the circuit due to ion diffusion in the gate oxide, hot carrier trapping, or the effects of ionising radiation. Whilst in systems made up of a large number of smaller integrated circuits, the smaller integrated circuits can be easily tested and replaced, this is more difficult in systems made up of one or more large scale integrated circuits.
It is an object of the present invention to provide an integrated circuit wherein this problem is alleviated. According to the present invention there is provided an integrated circuit including a monitor circuit designed to fail prior to the rest of the integrated circuit whilst allowing the rest of the integrated circuit to function, and means for providing an indication of when the monitor circuit has failed.
In one particular integrated circuit in accordance with the invention, the monitor circuit includes a conductive pattern and means for providing current through the pattern such that the current density through the pattern is greater than for the rest of the integrated circuit. Such a monitor circuit finds application monitoring possible failures of conductive portions within the integrated circuit due to electromigration. In such a particular integrated circuit, the means for providing an indication provides the indication when an open circuit has occurred in the pattern. Alternatively the means for providing an indication provides the indicat¬ ion when a short circuit has occurred between the pattern and an adjacent conductor.
In another particular integrated circuit in accordance with the invention, the monitor circuit comprises a field effect device, means for electrically stressing the device, and means for comparing the threshold voltage of the device to a reference voltage.
Such a monitor circuit finds application in monitoring possible variations of threshold voltages in field effect devices.
Two integrated circuits in accordance with the invention will now be described, by way of example only, with reference to the accompanying drawings in which Figure 1 is a schematic diagram of a monitor circuit incorporated in the first integrated circuit, Figure 2 is a schematic diagram of a monitor circuit incorporated in the second integrated circuit with the monitor circuit's switches in a first configuration and Figure 3 shows the monitor circuit of Figure 2 with its switches in a second configuration.
Referring firstly to Figure 1 , the monitor circuit incorporated in the first integrated circuit to be described is designed to monitor possible failure of metallic tracks within the integrated circuit due to electromigration. The monitor circuit comprises a metallic test pattern in the form of a stripe indicated as 1 connected in series with a resistor 3 across two supply rails 5, 7. The test pattern is formed on the integrated circuit at the same time as the other conductive tracks within the circuit such that variations in track thickness due to processing variations will be reflected in the stripe 1. The value of the resistor 3 is chosen such that in operation of the integrated circuit incorporating the monitor circuit, the current density through the stripe 1 is greater than the value usually regarded as a maximum rating for a metallisation pattern within the integrated circuit. Partially surrounding the stripe 1 is a U- shaped conductive track 9 spaced from the stripe 1 by a distance equivalent to the minimum recommended line spacing in the integrated circuit. The track 9 is connected to the supply rail 7 by a resistor 11 having a somewhat greater value of resistance than that of the resistor 3.
In operation of the integrated circuit, the voltages V1 of a point between the stripe 1 and resitor 3, and V2 of a point on the conductive track 5 each measured with respect to earth are continuously monitored. As the resistance of the stripe will be much less than the resistance of the resistor 3, the voltage V1 will remain close to that of the rail 5 until an open circuit in the stripe 1 , due to for example -H- electromigration, occurs, in which case the voltage V1 will become close to that of the rail 7. A warning circuit (not shown) will normally be either connected to or incorporated in the integrated circuit which is responsive to the voltage V1 to provide a warning when the monitored voltage V1 indicates that an open circuit has occurred In the stripe 1 , this then providing an early warning that the integrated circuit is likely to fail before the integrated circuit actually fails which may, in some circumstances be catastrophic. Appropriate action can then be taken such as total removal of the integrated circuit from the system in which it is incorporated where high reliability is required. The warning circuit will also be responsive to the voltage V2 which normally will be zero, but will approach the value of the voltage on the rail 5 in the event that electromigration causes the stripe 1 to become electrically connected to the track 9. It will be appreciated that the test pattern may take many forms in order to simulate possible failure modes, e.g. it may include steps over under¬ lying polysilicon lines, or border contact holes.
It will also be appreciated that a monitoring circuit designed to be responsive to possible failure through elctromigration of metallic tracks need, in some circumstances, .be only responsive to open circuits or short circuits in the test stripe.
Referring now to Figure 2 the second integrated circuit to be described includes a monitor circuit designed to monitor possible threshold voltage instabilities in MOS transistors within the integrated circuit. A monitor transistor 21 is connected as shown in this figure across two supply rails 23, 25, the gate of the transistor 21 being connected to the rail 23 via a moveable contact and a fixed contact of a two position switch 27, and the drain of the transistor being connected to the rail 23 via a biassing resistor 29, with the other fixed contact of the switch 27 being connected to a point 30 between the drain and the resistor 29. A series arrangement of two similarly valued resistors 31, 33 are also connected across the rails 23, 25. A fixed contact of a second two way switch 35 is connected to a point between the junction of the two resistors 31, 33, the moveable contact of the switch being connected to one electrode of a capacitor 37, the other fixed contact of the switch 35 being connected to the point 30 between the drain of the transistor 21 and the resistor 29. The second electrode of the capacitor 37 is connected to the gate electrodes of one n channel 39 and one p channel 41 MOS transistors, the drain of the n channel transistor 39, being connected to the rail 25, the source of the p channel transistor 41 being connected to the rail 23, and the remaining source and drain being connected together. The second electrode of the capacitor is also connected via a switch 43, shown closed in Figure 2 to the conductor connecting the source of the transistor 39 and the drain of the transistor 41, the voltage V3 being monitored at this point.
The switches 27, 35 and 43 all consist of transmission gate circuits clocked synchronously.
In operation of the integrated circuit, for about 90% of the time, the switches are set in the positions shown in Figure 2. The gate of the monitor transistor 21 is thus directly connected to the rail 23 so as to provide a maximum gate bias. The output voltage V3 will be approximately half the potential difference across the rails 23, 25 i.e. VRE as indicated in the figure, the capacitor 37 charging up to this voltage. On switching to the switch positions shown in Figure 3, the gate of the monitor transistor 21 is connected to the drain which will settle to around the threshold voltage Vτ 0f the transistor, assuming the resistor 29 is of sufficiently high value. The voltage applied to the capacitor 37 will thus increase by V_--V_,p_- as switch 35 is switched to the position shown in Figure 3, and switch 43 is opened. If V-, is greater than V-.-.-. then only transistor 41 will be conductive, and the voltage V3 will be that of the line 25. If however V-_ is less than V-.-,-., then only transistor 39 will be conductive, and the voltage V3 will be that of the line 23. A warning circuit (not shown) may then use the value of V3 to give a warning signal if the threshold voltage Vτ is less than -,_---. It will be appreciated that the value of
V-.„p is readily settable by choice of the relative values of the resistors 31, 33- It will also be appreciated that generally at least four monitoring circuits for monitoring potential threshold voltage Instabilities will be incorporated in an integrated circuit In accordance with the invention, so as to detect changes in n-channel threshold voltages with respect to a minimum and a maximum value, and changes in p-channel threshold voltages with respect to a minimum and a maximum value.
It will be appreciated that whilst the monitoring circuits described herebefore by way of example monitor possible failures due to electro- migration, or variation of threshold voltages, integrated circuits in accordance with the invention incorporating monitoring circuits in accordance with the invention incorporating monitoring circuits for monitoring many other variations in parameters likely to lead to circuit failure are also possible.

Claims

1. An integrated circuit characterised in that it includes a monitor circuit (1, 3, 9, 11) designed to fail prior to the rest of the integrated circuit whilst allowing the rest of the integrated circuit to function, and means for providing an indication that the monitor circuit (1, 3, 9, 11) has failed.
2. An integrated circuit according to Claim 1 in which the monitor circuit (1, 3, 9, 11) includes a conductive pattern (1) arranged such that the current density through the pattern (1) is greater than for the rest of the integrated circuit.
3. An integrated circuit according to Claim 2 in which the means for providing an indication provides the indication when an open circuit has occurred on the pattern ( 1 ) .
4. An integrated circuit according to Claim 2 in which the means for providing an indication provides the indication when a short circuit has occurred be¬ tween the pattern (1) and an adjacent conductor (9).
5. An integrated circuit according to Claim 1 in which the monitor circuit comprises a field effect device (21), means (30) for electrically stressing the device (21), and means for comparing the threshold voltage of the device to a reference voltage (v ref)-
EP19860905368 1986-09-17 1986-09-17 Integrated circuits Withdrawn EP0281552A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/GB1986/000547 WO1988002123A1 (en) 1986-09-17 1986-09-17 Integrated circuits

Publications (1)

Publication Number Publication Date
EP0281552A1 true EP0281552A1 (en) 1988-09-14

Family

ID=10591172

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19860905368 Withdrawn EP0281552A1 (en) 1986-09-17 1986-09-17 Integrated circuits

Country Status (3)

Country Link
EP (1) EP0281552A1 (en)
JP (1) JPH01500785A (en)
WO (1) WO1988002123A1 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3750018A (en) * 1971-11-24 1973-07-31 Ibm Ungated fet method for measuring integrated circuit passivation film charge density
US4243937A (en) * 1979-04-06 1981-01-06 General Instrument Corporation Microelectronic device and method for testing same
JPS602775B2 (en) * 1981-08-28 1985-01-23 富士通株式会社 Large-scale integrated circuit with monitor function and its manufacturing method
US4528505A (en) * 1983-03-29 1985-07-09 Motorola, Inc. On chip voltage monitor and method for using same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8802123A1 *

Also Published As

Publication number Publication date
JPH01500785A (en) 1989-03-16
WO1988002123A1 (en) 1988-03-24

Similar Documents

Publication Publication Date Title
KR100282432B1 (en) Time dependent dielectric breakdown test pattern and method for testing tddb of mos capacitor dielectric
US7471101B2 (en) Systems and methods for controlling of electro-migration
US2456499A (en) Electrical control and/or measuring system
EP0822418A2 (en) Sensor diagnostic apparatus and method thereof
US20010013788A1 (en) On-chip substrate regular test mode
CN101796424A (en) Semiconductor device test system having reduced current leakage
US7595968B2 (en) Circuit to reduce internal ESD stress on device having multiple power supply domains
US4841240A (en) Method and apparatus for verifying the continuity between a circuit board and a test fixture
US6433616B1 (en) Method and apparatus for detection of electrical overstress
DE102016107274A1 (en) switching device
JP2956855B2 (en) Monitor device and monitor method for integrated circuit
CN110690195B (en) Test structure of semiconductor device and test method thereof
EP0281552A1 (en) Integrated circuits
KR20010029742A (en) Characteristics evaluation circuit for semiconductor wafer and its evaluation method
DE102004028695B3 (en) Breakage sensor for installation near edge of semiconductor substrate has isolation layer and several electrode layers with terminals connected to sensor circuit
GB2176352A (en) Integrated circuits
US6219808B1 (en) Semiconductor device capable of carrying out high speed fault detecting test
US6005385A (en) Test board circuit for detecting tester malfunction and protecting devices under test
US20010050576A1 (en) On-chip substrate regulator test mode
CN113495203B (en) Test circuit and semiconductor test method
US10247770B2 (en) Gate oxide soft breakdown detection circuit
US10958067B2 (en) Single event latch-up (SEL) mitigation detect and mitigation
Sidiropulos et al. Implementation of BIC monitor in balanced analogue self-test
JPH06350092A (en) High-reliability integrated circuit structure for mos power device
JP2583338Y2 (en) Electronic circuit failure diagnosis device

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19880525

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR IT NL

17Q First examination report despatched

Effective date: 19881027

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19890228