JP2583338Y2 - Electronic circuit failure diagnosis device - Google Patents

Description

[Detailed description of the invention]

[0001]

The present invention is intended to reliably detect the presence or absence of a power supply open abnormality in an electronic circuit using a CMOS IC.
The present invention relates to an electronic circuit failure diagnosis device that can be used .

[0002]

2. Description of the Related Art A MOS is a CMOS IC shown in FIG.
Inverter such as that shown in (1) (10, 20,...)
There are those in which a plurality of sets built, the inverter includes a P-channel MOS FET (13,23, ···), N
Are complementary connected to the channel MOS FETs (15, 25,...).
S is called CMOS.

The withstand voltage of the oxide film of the insulated gate of the MOS FET is close to 100 V, but since the resistance value is extremely high, a voltage of approximately 1000 V may be applied due to static electricity or the like, and the gate may be destroyed.

[0004] Therefore, in the CMOS, there is a constant gap between input and output.
A protection diode for preventing edge destruction is provided, and when the voltage becomes high, the diode (11, 21,...) Discharges to prevent gate destruction. For a pulse-shaped input that is faster than the turn-on time of the diode for preventing dielectric breakdown , a resistance (14, 24,.
・ ・) And diode (1)
2, 22, ...).

[0005] Diodes for preventing dielectric breakdown (11, 21,
... 12, 22, ...) because the area occupied in the IC chip is small, a large forward current to not flow, the maximum 10mA about.

[0006]

[Problems to be Solved by the Invention] Now, CMOS IC
The power supply (1) is supplied from a VDD power supply connected to a power supply terminal (2) common to the inverters via a resistor (3), and a current flows through a path indicated by an arrow (4) in the figure.

However, due to an open failure of the power supply , etc.
Source when the terminal (2) Voltage successfully is not supplied, the power supply of
The circuit should never work when the supply is cut off
But it is, above inverter (10, 20,...) Was Tsu Kotogaa to <br/> behavior.

This is because when the input waveform of the input terminal 2 (26) becomes a high level as shown at (261), it passes through the dielectric breakdown preventing diode (21) as shown by the arrow (5). This is because current is supplied to the power supply line (6).

Even if such a phenomenon occurs, since the circuit is operating, a failure is not immediately found, and there is a risk that a serious accident will be caused later.

[0010] The failure as described aboveIf left, 1. Even one of the inputs of multiple input terminals
If there is an input, power is supplied via the abnormal path as described above.
The IC operates as if there is no abnormality,
No power supply when all inputs are low
No longer. 2. When power is supplied from the input terminal, all of the input terminals
The stage circuit may be overloaded and destroyed eventually.
You. 3. Protection diodes (11, 21, ...) are overloaded
Could lead to destruction. 4. Input levelFluctuationAndFor insulation breakdown preventionWith diode
The output level becomes abnormal due to the voltage drop of.There was a problem that caused problems such as .Also,
No. 3-278114 "Output Circuit" has CMOS type
Diagnosis of an IC having a plurality of output buffer circuits
Therefore, input a predetermined test pattern signal and output
Noise level mixed into power supply line instead of checking method
There is disclosed a circuit configured to detect and output a signal.
However, this circuit does not isolate the gate of the inverter.
Identify the input sneak through the destruction prevention diode
It is not a circuit to detect a power supply open fault,
Also, even if test pattern signals are used,
Requires several types of signals.
There was a problem that there was. In addition,
No. 56-50629 "Complementary MOS integrated circuits"
When the input voltage exceeds the power supply voltage, the complementary MO
A circuit for shutting off a power supply of an S integrated circuit is disclosed.
ing. However, this is not the input end of the device.
To protect the device from the overvoltage applied to the
It is a circuit and cannot determine a power supply open fault.
There was nothing. Furthermore, the actual opening 61-5771
No. 7 “Failure prevention circuit” includes multiple
In a number of CMOS circuits, one gate
If the power supply drops to 0V, the gate that becomes another load malfunctions
A circuit that does not work is disclosed. However
This circuit prevents malfunction of other circuits before the gate.
The purpose of this is simply to provide a voltage dividing resistor for the purpose of
Does not detect a power supply open fault with
In addition, only each gate operates with a different system power supply
Even if a power supply open fault is diagnosed,
Circuit that operates multiple inverters on a common power supply
It is difficult to narrow down the diagnosis target easily as in the configuration.
It had problems such as inevitable complication.

[0011]

SUMMARY OF to the present invention has been made in order to solve such problems, P-channel MOS
Complementary connection between FET and N-channel MOS FET
A plurality of CMOS inverters are provided in parallel with each other.
Inverter P-channel MOS FET
Connected to a common power supply and die to prevent dielectric breakdown.
Connected to the cathode of the diode, and
An electronic circuit comprising an anode connected to a gate,
Of the output terminal of one of the plurality of inverters
A level detection circuit for detecting a signal level;
Low-level diagnostic pulse is supplied simultaneously to each data gate
The output level of the level detection circuit is low.
If there is an open error in the power supply,
Fault diagnosis means for determining that the
It is characterized by the following .

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. 1, but those having the same reference numerals as in FIG. 3 will not be described again.

(9) checks whether there is an open failure of the power supply.
Power supply open detection device
Ri, diagnosis signal generating section (91), Ri Do from the output detecting transistor and (93) and load resistance (94), Invar
It comprises a level detection circuit for detecting the output level of the data , a judgment unit (95), an alarm device drive unit (96), and an alarm output device (97).

The operation of the present apparatus will be described with reference to the flowchart of FIG. 2. First, when a failure diagnosis mode (step 201) is entered, all of the input terminals (16, 26,. ..) Are supplied to a low level (step 202), the output level of the output terminal 1 (17) at this time is detected by the level detection circuit, and the determination section (95) makes the determination. (Step 20
3).

If the output level is high, the power supply circuit is normal (step 204). If the output level is low, it is determined that the power supply circuit is abnormal, and the alarm output device (9)
The abnormal alarm is output from 7) (step 205).

[0016]

[Effects of the Invention] As described above, according to the present invention ,
One of the inverters that make up the electronic circuit
Level detection circuit that detects the signal level of the output terminal of the inverter.
Low-level diagnostics on the
Supply a disconnection pulse and the output level of the level detection circuit becomes low.
If it is at the level, there is an open error in the power supply,
If it does not exist, it has failure diagnosis means to determine that it is normal
Therefore, even if there is an open failure in the power supply,
Supplied to one of the inverters
Gate current is supplied to the power supply
Wrong to the child side, it is as if the power supply is alive
Even if a solution is given, each fault
Low-level diagnostic pulse is supplied simultaneously to each data gate
If the output level at that time is low level,
Open faults can be reliably detected and therefore input
Power is supplied from the
Die to prevent breakdown due to load and dielectric breakdown
Aether is overloaded, destroyed or even entered
Voltage at the diode for preventing level fluctuation and dielectric breakdown
The inconvenience that the output level becomes abnormal due to the drop
An excellent effect is obtained such that the combination can be eliminated .

[Brief description of the drawings]

FIG. 1 shows an embodiment of an electronic circuit failure diagnosis device of the present invention.
FIG.

FIG. 2 illustrates the operation of the electronic circuit failure diagnostic device shown in FIG .
It is a flowchart for clarifying.

FIG. 3 is a circuit diagram showing a conventional example of a CMOS IC circuit.
You.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 CMOS IC 3, 14, 24, 92, 94 resistor 2 power supply terminal 3 power supply series resistor 4 normal current path 5 abnormal current path 6 power supply line 9 power supply open detection device 10, 20 inverter circuit 11, 21, 12 , 22 Protective diode 13, 23 P-channel MOS FET 15, 25 N-channel MOS FET 16, 26 Input terminal 17, 27 Output terminal 91 Signal generator 93 Transistor 95 Judgment unit 96 Driving unit 97 Alarm output device 161, 262 Input waveform 171 , 272 output waveform

Claims (1)

(57) [Scope of request for utility model registration] 1. A P-channel MOSFET and an N-channel MOSFET.
CMOS configuration with complementary connection of
A plurality of inverters are provided in parallel, and the P-channel
For a MOSFET, connect the source to a common power supply.
To the cathode of the diode for preventing dielectric breakdown
And connect the anode of the diode to prevent breakdown.
An electronic circuit connected to the inverter and the plurality of inverters.
Detect the signal level of the output terminal of one of the inverters
Level detection circuit and the gates of the inverters.
Sometimes a low level diagnostic pulse is supplied to detect the level
When the output level of the circuit is low,
If there is an open error, otherwise it is considered normal.
An electronic circuit failure diagnosis apparatus, comprising: