JPH0150037B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to semiconductor devices, and more particularly to sense amplifier circuits for dynamic read/write memory devices. (Conventional technology) Dynamic MOS read/write memory
Devices are White, McAdams and Redwine
U.S. Patent No. 4081701 (16K) issued for
DYNAMIC RAM) or US Patent No. issued to McAlexander, White and Rao.
No. 4239993 (64K Dynamic RAM), both manufactured by Texas Instruments.
The device is generally constructed as shown in a patent assigned to Incorporated Instruments. This kind of memory
As devices are fabricated at higher densities, such as 256K and 1 Mbit and above, the problem of limiting the peak current delivered to the chip becomes complicated. In a 1 megabit DRAM that is refreshed 512 times per period, there are 2048 sense amplifiers that flip simultaneously during the active cycle. Each one of these requires a current to charge the bit line to Vdd, discharge the bit line to Vss, or both, depending on the precharge level. Thus, the voltage source to the chip experiences very large current spikes over short periods of time, and as the access time is increased, the magnitude of the current spike increases. Thus, it has been advisable to carefully size the latch and return transistors to minimize unnecessary current consumption. Nori Kitagawa, which was transferred to Texas Instruments
Kitagawa)
No. 4,050,061 discloses a method for limiting peak current by partitioning the array into blocks and fully activating the sense amplifiers only in the addressed blocks. In this case the other blocks are operated at a lower level and at a slower speed. In dynamic RAM, the sensing operation is latched.
Depends strictly on the transistor. These transistors must operate reliably to within 10%
Threshold voltages Vt and KP must be balanced. (KP means the evaluation value K' regarding channel length (L) and width (W), oxide thickness, mobility, etc. For a given bar, everything is constant except W/L. Therefore, K′ is W/
means L. ) Prior art sense amplifiers using only N-channel transistors
An active pull-up circuit was required to create complete rail-to-rail isolation of the line. CMOS latches provide rail-to-rail isolation without such pull-up circuits. However, the latch becomes unreliable when a P-channel transistor is used in the initial sensing. OBJECT AND SUMMARY OF THE INVENTION An object of the present invention is to provide a power efficient sense amplifier for semiconductor memory. This purpose includes a memory cell addressing line; a sense amplifier for sensing the voltage on at least one of said lines; first and second resistive paths connected in parallel to said sense amplifier; and a power return circuit;
The resistance of the resistive path is less than the resistance of the second resistive path, the second resistive path being selected when the line is being refreshed, and at least the first resistive path being selected when the line is being addressed. This is achieved by a sense amplifier of a semiconductor memory device, characterized in that it is selected. (Embodiment) According to one embodiment of the present invention, the dynamic
A CMOS sense amplifier circuit for read/write memory uses cross-coupled N-channel transistors and cross-coupled P-channel transistors returned to a voltage source, with P-channel transistors selectively activated by a sense clock. and ground through two other sets of N-channel transistors. The return transistor is operated in either fast sensing or slow sensing depending on the address input. Selected columns are sensed at maximum speed, and unselected columns that are only being refreshed are sensed at a slower rate. The large return transistor is switched into a dedicated fast sensing circuit, while other smaller transistors perform the slow sensing function with a high resistance return to the voltage source such that the peak or instantaneous current is lower. In another embodiment, the differential inputs of the sense amplifier are held on when the word and dummy lines go high, and then turned off while the sense amplifier is activated by the sense clock. Connected to the bit line via a coupling transistor. The coupling transistor is then turned on in the selected column before being turned on in the unselected column. With these characteristics,
The current required to charge and discharge the bit line is thus spread out and the peak current is reduced. According to another feature, an N-channel transistor is used for initial sensing, and then both N-channel and P-channel transistors are used in an amplification order to restore the one level. This results in better balance and allows the use of smaller N and P channel latch transistors.
Area is saved, power is saved, and speed is increased. The novel features of the invention are pointed out in the claims. However, the invention itself, as well as other features and advantages thereof, may be best understood from the following detailed description taken in conjunction with the accompanying drawings. Referring to FIG. 1, a sense amplifier circuit for a dynamic RAM array is shown in accordance with one embodiment of the present invention. The sense amplifier in this example consists of a pair of N-channel driver transistors N1 and N2.
and a pair of P-channel pull-up transistors P1 and P2. The N-channel transistors are connected to ground through a pair of N-channel transistors N3 and N4 with sense clocks S1 and S2 on their respective gates, and the P-channel transistors are the complement of sense clocks S1 and S2 on their respective gates. A pair of P channels with 1 and 2
Coupled to Vdd via transistors P3 and P4. Sensing nodes 1 and 2 at the drains of the N-channel transistors are coupled to bit lines B1 and 2B. Bit lines B1 and B2 contain a number of one bit lines.
Each is coupled to a transistor memory cell, each memory cell having a storage capacitor _Cs and an N-channel access transistor Ns. One cell is selected by the word line Xw voltage. The dummy cells on each line include a dummy capacitor Cd and an access transistor Nd. The dummy row line opposite the selected word line is
Operated by Xdum voltage. The sequence of operation of the elements of the sense amplifier of FIG. 1 is shown, by way of example, in the timing diagram of FIG. 2. The selected Xw and Xdum voltages are at time t1
0 to Vdd level, turning on one transistor Ns and one transistor Nd on opposite sides of the sense amplifier. This causes bit lines B1 and B2 to share charge by the storage capacitor Cs on one side and the dummy capacitor Cd on the other side. The precharge level and size of these capacitors are such that the voltage appearing on the bit line with Cs connected to it will be higher or lower than the voltage on the dummy side depending on the storage of a 1 or 0.
The bit line and sensing node are thus separated at a voltage just after t1. This voltage difference is
and 2 (transistors N1, N2, P1, P2
The capacitance (including the gate of ) is temporarily maintained. The circuit of FIG. 1 may be operated using either N-channel sensing or P-channel sensing. Assuming an N-channel type is used, at time t2, sense clock S1 goes to Vdd and 1 falls, turning on transistors N3 and P3, leaving the cross-coupled flip-flop circuit in high impedance. • Start the operation at level, i.e. at low gain. One of the nodes 1 and 2 decays slowly towards 0, and the other towards Vdd. Little current is consumed at this point because of the high series resistance of transistors N3 and P3. One of the larger transistors N4 or P4 must be turned on to bring bit lines B1 and B2 to full Vdd and 0 levels with fast sensing. To this end, following the example of N-channel sensing, voltage S2 becomes Vdd at time t3 if this is the selected column. The 0-way bit line B1 or B2 is rapidly discharged to ground through an N-channel transistor N1 or N2 and a large transistor N4. The unidirectional bit line is rapidly charged from the Vdd source through P-channel transistor P1 or P2 and transistor P3. That is, in this example of N-channel sensing, the large transistor P4 is not used, whereas in the case of P-channel sensing, transistor P4 is activated by 2 at t3, but transistor N4 is not used. The time required to achieve complete rail-to-rail isolation of the bit lines without introducing the large high gain transistor N4 (or P4), shown as time t4 in Figure 2, is determined by the dynamic
Too long to get reasonably fast access times in RAM. Thus, in large DRAMs where the number of cells in a row called for refresh is greater than the number called for data I/O,
The sense amplifier can have an S2 (or 2) voltage selectively applied. When S2 is applied, the 0 side quickly drops to 0 at t3 as seen in FIG. 2, and the data bit is sensed for read operations much faster than at t4 in this situation. Bit lines B1 and B2 are connected to data I/O by column select transistors, not shown.
coupled to the circuit. In the selected column, the bit
Since the line is driven far apart at time t3,
The data bits are coupled to a data output circuit for output from the chip. Other columns not selected by fast sensing are simply refreshed and
Therefore, the time delay until t4 is not disadvantageous since there is sufficient time until the end of the active read cycle. Vdd isolated for contribution by sense amplifier
And the current flowing into and out of the chip on the Vss line is also
As shown in the figure. There is no current in the sense amplifier until t2, and this current pulse at t2 is small because the series resistance is large. At t3, there is a current pulse as the selected line is rapidly charged and discharged, but the current in the unselected bit line is spread out over a longer period of time, so the peak current is smaller. Of course, there will likely be other current peaks (not shown) when RAS drops, when CAS drops, and when RAS goes high (precharge begins). Referring now to FIG. 3, a block diagram of an exemplary semiconductor dynamic read/write memory chip is shown that may utilize a sense amplifier circuit constructed in accordance with another embodiment of the present invention. . This device is a so-called 1 megabit device with ²²⁰ or 1048576 memory cells in an array of rows and columns. The array consists of four identical blocks 10a, 10b, 10
The block is divided into blocks c and 10d, and each block contains 262144 cells. Within each block there are 512 row lines, and every row line is connected to one of the row decoders 11a or 11b. Each row decoder 11a or 11b is
Receives nine bits of a 10-bit row address from address input pin 12 through row address latch 13 and line 14. The row decoder produces the row select voltage as described above. A 10-bit column address is also applied to input pin 12 in a time multiplexed manner and this column address is coupled to buffer 15. Eight data I/O lines 16 are located in the center of the array;
One of these eight is the selector 17 of 1 out of 8.
selected for data input or data output by One I/O line from this selector 17 is connected to a data input pin 18 and a data output pin 19 via a buffer. Selector 17 receives three bits of a column address on line 20 from column address buffer 15.
Two of the eight lines 16 are connected to each block 10a, 10b, 1 by an I/O line 21, respectively.
Connected to 0c and 10d. Column selection of 2 of 16 uses 3 bits of column address on line 23 from buffer 15 to select 16 for each block.
This is performed using intermediate output buffers 22. 1 out of 16
Column selection for each block 10a is performed using the 4 bits of the column address on line 25 from buffer 15.
- Each of the 16 intermediate output buffers 24 located at
It will be held in 16 groups. Each one of the 512 sense amplifiers 26 (as in FIG. 1) in each block is connected to one of the columns in the array (each example is one half of two column lines or "bit lines"). ). Each buffer 24 is coupled to one of two columns. This selection is based on one bit of the row address from buffer 13 on line 27. The memory device receives the row address strobe RAS on input pin 28 and also receives the row address strobe RAS on input pin 2.
9 receives the column address strobe CAS .
Selection of read or write operation is made using input pin 30.
This is done by R/control. Clock occurs/
Control circuit 31 makes all internal clocks and controls as necessary. For a single bit read (or write), RAS and CAS fall to 0 in the sequence shown in Figure 3a, resulting in a one bit data read (or write). Each block of the array is
4,081,701. From FIG. 4, I/O lines 16, intermediate output buffers 22 and 24, and sense amplifier 26 are shown in detail for one portion of blocks 10a-10d. In a given block, there are 16 intermediate output buffers 22, in this figure 22-
1...It is represented by 22-16. Batsuhua 2
2-1 to 22-8 are a group of eight buffers that are combined with one of the lines 16 of this block, and buffers 22-9 to 22-16 are combined with one of the lines 16 of this block by the line 21. Another group of eight buffers is connected to one of the buffers. In each of the 16 buffers 22-1...21-16, there is a set of 16 buffers 24.
Here these sets are represented by 24-1 to 24-16 (16 in each set). Each group of 16 buffers 24 is equipped with a group of 32 sense amplifiers 26, and each sense amplifier 26 is connected to two of the bit lines 33 (one column is the bit line in FIG. - equal to the 2-bit line corresponding to lines B1 and B2). bit line 3
3 intersects with the memory cell array.
There are 512 row lines 34. Dummy row line 3
2 also intersects with bit line 33, as will be described later. 2
One of the dummy lines of the book is assigned to the row decoder 11 using one bit of the 9-bit row address 14.
a, 11b. The 10th bit of the row address from buffer 13 is applied by line 27 to a multiplex circuit for sense amplifiers 26 and to the first level by line 37 in each pair of two sense amplifiers. The one connected to the intermediate buffer 24 is selected. This block has 16 pairs of data/data bar lines and 38
and 39, each pair being connected on one side to the selected buffer 24 by line 40 and to the selected buffer 22 on the other side by line 41. It is noted that the I/O varies from dual rails on lines 38 and 39 to a single rail on data I/O line 16 for write operations. From FIG. 5, a portion of the circuit of FIG. 4 is shown in detail. A sense amplifier 26 is shown combined with a set of 16 buffers 24-1.
There are actually 32 sense amplifiers 26 in this set. This set of 16 buffers 24-1 is represented in this figure by 24-1-1 through 24-1-16. Each sense amplifier 26 is
It has two bit lines 33 emanating from it in a so-called folded bit line structure. Thus,
All word lines 34 and both dummy rows 3
2 are on the same side of the sense amplifier. The row lines 34 intersect the bit lines, and the memory cells are just as in FIG. 1, but at the intersection of the folded row or word line and the bit line. Multiplexer 42 for each pair of sense amplifiers 26
Based on the address bits on line 27,
Each buffer 24-1- by line 37
Select the one connected to 1, 24-1-2, etc. 16 battles 24-1-1 to 24-1-
Only one of up to 16 is selected at any one time based on the four row address bits on line 25, so only one is selected by line 40 for data entering or exiting lines 38, 39. It will operate to combine read or write bits. Buffer 22-1 in FIG.
may be selected or not selected by a selection of 2 out of 16 provided by the 3 bits of . 6, one of the sense amplifiers 26 made in accordance with the present invention is shown in detail. This diagram also shows the two bit lines 3 for this sense amplifier.
3 and four of the 512 row lines 34 perpendicular to these bit lines are also shown. The sense amplifier consists of an N-channel driver transistor N1
and N2 and P-channel pull-up transistors P1 and P2 as shown in Figure 1.
Use cross-coupled flip-flops. Sensing nodes 1 and 2 are connected to bit line 33. The ground node Ng of this flip-flop has a sensing clock S1 on each gate.
and two N-channel transistors N3 and N4 with S2 connected to ground. Transistor N3, which has S1 on its gate, is much smaller than the other transistor N4, and clock S1 occurs first, so that initial sensing is in a low gain state. On the Vdd side, node Nh is coupled to the power supply via P-channel transistors P3 and P4 with detection clocks 1 and 2 on their respective gates. (The circuit is shown in FIG. 1 as being able to use N-channel or P-channel sensing. In the actual circuit, either transistor N4 or transistor P4 is selected and clock S2 or (It will be omitted.)
Sensing clocks 1 and 2 are S1 and S2
, so that P-channel transistors P3 and P4 begin to operate only when clocks S1 and S2 are activated. 2 interval sensing operation,
First in S1 (at low current levels) and then in S2 (or 2). transistors N3 and N4,
and P3 and P4 can be unique to each sense amplifier, or alternatively shared by all of the other sense amplifiers 26 in the two blocks 10a and 10b, ie, 1024 sense amplifiers.
Nodes Ng and Nh are precharged to approximately 1/2 Vdd by transistor 83 when E is high. Bit line 33 is precharged and equalized through three transistors 84 having an equalized clock voltage E on their respective gates. Two of these transistors are reference voltage
It has a source connected to Vref. Since this reference voltage value is approximately 1/2 Vdd, little or no net charge is required from the chip power supply Vdd to precharge all of the bit lines. That is, since one line 33 of each sense amplifier is high and the other line is low, one charges the other and Vref does not need to supply much of any difference that may occur. Clock E
is issued to the control circuit 31 after the active cycle is completed when RAS goes high. Each memory cycle in FIG. 6 consists of a capacitor Cs and an access transistor Ns exactly as in FIG. has been done. Since only one row line 34 of the 512 in the block is turned on at any one time, only one memory cell capacitor Cs is connected to the bit line 33 of a given sense amplifier 26. Connected. Bit Line Capacitance vs. Storage Capacitor
To reduce the ratio of the values of Cs, multiple bit line segments 87 are used for each associated bit line 33. These segments 87
is coupled to bit line 33 at a given time by one of transistors 88.
For example, each segment 87 has 32
In the embodiment disclosed herein, there must be 16 of these segments 87 for each sense amplifier (16×
32=512). Half of the segments are connected to bit lines and the other half to other bit lines. Row decoder 11a or 11b selects one row line 34 out of 512 based on a bit of the same nine address bits from line 14, and at the same time the segment select voltage is applied.
An appropriate one of the 16 lines 89 is selected by SS. In dummy row 32, a pair of dummy cells are provided in dummy row 32, a pair of dummy cells are provided for each associated bit line 33, and these dummy cells are connected to dummy capacitor Cd and access line 33.
As described above, it is composed of the transistor Nd. When the selected storage cell is on the left-hand bit line 33, the right-hand dummy
Cells are selected in the row decoders 11a, 11b by one of the decoder output lines 92, and vice versa, in the usual manner. One bit of the row address is used in the row decoder to select one or the other of these lines 92 of the dummy cell row 32. From FIG. 7, the operating order of the memory device is illustrated for a single bit read operation. The active cycle begins with the RAS voltage dropping from +5 to 0. Since this example is a read cycle, the R/ W input voltage is +5 at this point.
The time before this is the precharge cycle, during which the equalization voltage E is high, so all bit lines 33 and nodes Ng and Nh are approximately 1/2
It is precharged to the Vref voltage, which is thought to be Vdd or +2.5. Since the segment select signal SS appearing on all lines 89 is high, all of the segments 87 are also precharged to the Verf voltage.
The drop in RAS causes the equalization voltage E to drop, isolating the pair of bit lines 33 from each other and from Vref. Next, the segment selection signal SS drops,
All of segment 87 is isolated from bit line 33. As soon as the time for the row decoders 11a, 11b to respond to the row address is reached, time t1
, the Xw and Xdum voltages are 1 out of 512 selected
row line 34 and 1 dummy in the selected 2
It begins to rise by line 92. same time t1
Then, one of the lines 89 has a segment selection signal SS.
is generated. These address voltages Xw,
Xdum and SS are generated rather slowly,
Later, SS and Xw are boosted above Vdd for a short time after reaching the Vdd level, and access
Eliminates the Vt drop across transistors Ns and 88. The dummy voltage drops during initial sensing as the dummy cells complete their function, and the dummy capacitors are decoupled from the bit lines so they can be precharged. At time t2, sense amplifier 26 is first activated by the S1 voltage going high (low level);
High impedance N-channel transistor N
3 and turns on high impedance P-channel transistor P3. This begins to separate the bit lines 33 further than the separation due to the differential voltages of the storage cells and dummy cells. At this point, the current flowing to ground from the power supply Vdd or through transistors N1, N2, P1 and P2 is minimal. For the selected sense amplifier, sense voltage 2 is generated at t3 (or S
2 falls), large transistor N4 (or P4) begins to conduct, bringing the bit line to rail-to-rail conditions more quickly. One bit line 33 will be high and the other will be zero.
The sense amplifier selection voltage SAS1 or SAS2 (selected by address bit 27) is
When turned on, one of the sense amplifiers is connected to buffer 24 via line 37 in FIG. 5 using multiplexer 42. Just before this, the Y select output from the column decoder is valid so the selected data bit is valid on line 16, and shortly thereafter the data bit is valid on output pin 19. The selection of which sense amplifier is activated to produce high current sensing is based on address bits. In the embodiments shown in FIGS. 3 to 7,
There are 2048 sense amplifiers, half of which (including the selected column) receive the sense clock (i.e. 2), and the other half do not. One way to accomplish this is by using address bits appearing on line 27, similar to the method used in multiplexer 42 to select which sense amplifier 26 connects to the I/O circuit. As seen in FIG. 6, all of the sense amplifiers selected by SASO have a sense clock voltage S2 applied by line 95, and those selected by SAS1 receive a sense clock voltage from line 96. A pair of logic gates 97, which receive address bits 27 and its complement, and sense clock voltage S2, apply the appropriate voltages to transistor N4 (or P4). Thus, the current pulse that charges and discharges all 2048 pairs of bit lines is spread over twice the time, reducing the peak current. Referring to FIG. 8, a sense amplifier circuit for a dynamic RAM array is shown in accordance with another embodiment of the present invention. The sense amplifier uses a CMOS cross-coupled flip-flop circuit comprising a pair of N-channel driver transistors N1 and N2 and a pair of P-channel pull-up transistors P1 and P2. The N-channel transistor is coupled to ground through an N-channel transistor N3 that has a sense clock S on its gate, and the P-channel transistor is coupled to Vdd through a P-channel transistor P3 that has a sense clock S on its gate that is the complement of the sense clock S. ing. Sensing nodes 1 and 2 at the drains of the N-channel transistors are connected to the bit line B1 via a transfer transistor according to the invention.
and bound to B2. Transistor T1
and T2 has a clock T on its gate that clocks the sensing node during the high current portion of the sensing operation.
Decoupling from the line serves to spread the current draw of the power supply, ie, reduce peak current. Bit lines B1 and B2 are each coupled to a number of one-transistor memory cells, each memory cell connected to a storage capacitor Cs.
and an N-channel access transistor Ns. One cell is selected by the word line Xw voltage. dummy capacitor
There is a dummy cell in each line containing Cd and an access transistor Nd. Selected word
The dummy on the row line opposite the line is activated by the Xdum voltage. The operating sequence of the elements of the sense amplifier of FIG. 8 is shown in the timing diagram of FIG. Selected Xw
The and Xdum voltages go from 0 to the Vdd level at time t1, turning off one transistor NS and one transistor Nd on opposite sides of the sense amplifier. This causes bit line B1
and B2 are charge-shared by a storage capacitor Cs on one side and a dummy capacitor Cd on the other side. The precharge level and size of these capacitors are such that the voltage on the bit line due to Cs connected to it is higher or lower than the voltage on the dummy side depending on whether a 1 or a 0 is stored. . The bit line and sensing node are thus separated in voltage immediately after t1.
At time t2, the T voltage drops from Vdd to 0,
Bit lines B1 and B2 are decoupled from sensing nodes 1 and 2. However, the voltage difference between nodes 1 and 2 (transistors N1, N2, P1,
(including the gate of P2). At time t3, the sensing clock S goes to Vdd;
S falls, turning on transistors N3 and P3 and activating the cross-coupled flip-flop circuit. One of nodes 1 and 2 quickly drops to 0, while the other goes to Vdd. The reason that the current consumption at this point is small (current spike #1 in FIG. 9) is because the capacitance to be charged and discharged is small. The capacitance of nodes 1 and 2 is much smaller than that of bit lines B1 and B2. Transistors T1 and T2 are connected to the bit line B so that the selected capacitor Cs is restored to a full logic level.
1 and B2 must be turned back on to bring them to full Vdd and zero levels. To this end, according to this embodiment of the invention, the voltage T returns to Vdd at time t4 or t5, depending on whether it is the selected column or not. When T goes high at t4 or t5, the 0-way bit line B1 or B2 becomes an N-channel transistor N.
1 or N2, rapidly discharges to the ground, and 1
The direction bit line is charged from the Vdd supply through P-channel transistor P1 or P2 (current spike #2 at t4 in Figure 9).
, corresponds to #3 at t5). This charging and discharging causes voltage bumps at sensing nodes 1 and 2;
These bumps quickly subside before the data passes to the I/O circuits. Bit lines B1 and B2 are connected to data I/O by column select transistors, not shown.
coupled to the circuit. In the selected column, the bit
Since the line is rail-to-rail driven at time t4, data bits are coupled from the bit line to the data I/O circuitry for output from the chip. Other columns not selected by the column decoder are only refreshed, so
The time delay until t5 is not disadvantageous since there is sufficient time for the active read cycle to finish. Again, the voltage bump induced in response to current spike #3 decays in sufficient time until the word line is turned off, thus restoring data to the unselected cell. . isolated against the contribution by the sense amplifier,
The current flowing into and out of the chip on the Vdd and Vss lines is shown in FIG. The sense amplifier has t
There is no current until t3 and this current pulse #1 is small at t3 because sensing nodes 1 and 2 are small. At t4 and t5, there are current pulses #2 and #3 as the bit line is charged and discharged, but the current is spread out over a long time, so
The peak current is smaller. Of course, when descends, when descends, and
When RAS goes high (precharging begins),
Other current peaks (not shown) are likely present. 10, one of the sense amplifiers 26 in the devices of FIGS. 3-5 made in accordance with the FIG. 8 embodiment of the present invention is shown in detail. This diagram shows the two bit lines 3 for this sense amplifier.
3 and four of the 512 row lines 34 perpendicular to these bit lines are also shown. The sense amplifier consists of an N-channel driver transistor N1
and N2, and a CMOS cross-coupled flip-flop as shown in FIG. 8 with P-channel pull-up transistors P1 and P2. Sensing nodes 1 and 2 are connected to bit line 33 via the source-drain paths of isolation transistors T1 and T2.
Node 78 on the ground side of this flip-flop
is 2 with sensing clocks S1 and S on the gates.
N-channel transistor N3 to ground. Transistor N with S1 at the gate
3 is much smaller than the other transistor N3, and since clock S1 occurs first, the first sensing is at a lower gain state and is performed by N-channel transistors N1 and N2.
Node 81 on the Vdd side is coupled to the power supply via a P-channel transistor P3 with a sense clock on its gate. Since the sense clock is the complement of S, P-channel transistor P3 begins to operate only after clock S is activated.
There are two interval sensing operations, first S1 (at low current levels), then S and. Transistor N3
and P3 are two blocks 10a and 10
All of the other sense amplifiers 26 in b, i.e.
Shared by 1024 sense amplifiers. Node 78 connects transistor 8 when E is high.
3, it is precharged to about 1/2Vdd. Bit line 33 is precharged and equalized by three transistors 84 with equalizing clock voltage E on their gates. These transistors 8
The two sources of 4 are each connected to the reference voltage Vref. The value of this reference voltage is approximately 1/2Vdd
, so little or no net charge is required from the chip power supply Vdd to precharge all of the bit lines. That is, one line 33 for each sense amplifier is high and the others are low, so one charges the other and Verf only supplies any difference that may occur.
When RAS goes high, clock E is generated in control circuit 31 after the active cycle is completed. Each memory cell in Figure 10 has a capacitor Cs and an access transistor exactly as in Figure 8.
Ns, all gates of the 512 access transistors Ns in one row are connected to row line 34. Because only one row line 34 of the 512 in the block is turned on at any one time, the bit line 33 for sense amplifier 26 is provided with only one memory cell capacitor, Cs. It is connected to the. Multiple bit line segments 87 are used for each pair of bit lines 33 to reduce the ratio of bit line capacitance to the value of storage capacitance Cs. One of these segments 87 is coupled to bit line 33 at a given time by one of transistors 88. For example, each segment 87 may have 32 cells connected to it, so in the embodiment disclosed herein there must be 16 of these segments 87 for each sense amplifier (16× 32=512). Half of the segments are connected to one bit line and half to the other bit line. Row decoder 11a or 11b
selects the appropriate one of the 16 lines 89 by the segment select voltage SS, and at the same time the decoder selects the appropriate one of the 16 lines 89 based on some of the same 9 address bits from line 14. 1 row line 34 is selected. In the dummy row 32, each pair of bit lines 33
A pair of dummy cells are provided for the
Cd and an access transistor Nd. When the selected storage cell is on the left hand bit line 33, the right hand dummy cell is output to the row decoder 11a, by one of the decoder output lines 92.
11b in the usual manner, but vice versa. One bit of the row address is used in the row decoder to select one or the other of these lines 92 of the dummy cell row 32. Referring to FIG. 11, the operating order of the memory device is illustrated for a single bit read operation. The active cycle begins when the voltage drops from +5 to 0. Since this example is a read cycle, the R/input voltage is +5 at this point. The time before this is the precharge cycle, during which equalization voltage E is high, so bit line 33 and node 78 are all at the Verf voltage, which appears to be about 1/2Vdd or +2.5V. Pre-charged. Since the segment select signal SS appearing on all lines 89 is high, all of the segments 87 are also precharged to the Verf voltage. The drop in the bit line 33 causes the equalization voltage E to drop.
isolate the pairs from each other and from Verf. Next, the segment selection signal SS falls and the segment 87
from bit line 33. At time t1, Xw and
Xdum voltage is selected row line 3 of 1 out of 512
4 and the selected 1 of 2 dummy line 92 begins to rise. At the same time t1, line 8
9, the segment selection signal SS is raised.
These address voltages Xw, Xdum and SS are raised rather slowly, and later, some time after reaching the Vdd level, SS and
The access transistor is boosted over
Eliminate Vt drop across Ns and 88. The Xdum voltage drops as the dummy cell function is completed during the first sensing and the dummy capacitor is decoupled from the bit line so that it is precharged. Until time t2, sense amplifier 26 is
First, the S1 voltage is activated by going high, turning on the high impedance N-channel transistor N3. This begins to isolate the bit lines 33 more than the isolation caused by the differential voltages of the storage and dummy cells. However, from the power supply Vdd, transistors N1, N2, P
The T voltage drops at t2 before any significant current flows on bit line 3 and P2.
3 from sensing nodes 1 and 2. After the T voltage drops, the sensing voltage S is increased at t3, so that the large transistor N3 begins to conduct. As P-channel load transistor P3 begins to conduct, P-channel load transistor P3 begins to conduct. At this point current spike #2 in Figure 9 occurs (note that the circuit is also made so that T falls before S1 goes high). After S rises and falls, the T voltage is raised to Vdd at time t4 or t5 as described above. After isolation transistors T1 and T2 are turned back on, the bit lines are brought into a rail-to-rail condition. One bit line 33 is high, the other is zero. The sense amplifier selection voltage is SAS1 or SAS2 (selected by address bit 27).
When turned on, one of the sense amplifiers is connected to the multiplexer 42.
Buffer 2 via line 37 in FIG.
Connect to 4. As soon as this is done, the Y select output from the column decoder becomes valid, so the selected data bit becomes valid on line 16, and shortly thereafter the data bit becomes valid on output pin 19. The selection of the time t4 or t5 at which the T voltage is increased is based on the address bits. In the embodiment of Figures 3-5, there are 2048 sense amplifiers, half of which (including the selected column) receive a rising T voltage at t4 and the other half at t5. can. One way to achieve this is line 27
using the address bits of I/
The same method was used for multiplexer 42 to select which sense amplifier 26 connects to the O circuit. 10th
As can be seen, all of the sense amplifiers selected by SAS0 have a T voltage applied by line 95, and the sense amplifiers selected by SAS1 receive a T voltage from line 96. A pair of logic gates 97 receiving address bit 27 and its complement and two T voltages (ending at t4 or t5) apply the appropriate voltages to transistors T1 and T2. Thus, 2048 pairs of bits
The current pulses that charge and discharge all of the lines are spread out over twice the time, reducing peak current. The T voltage is boosted (by circuitry not shown) above Vdd to provide a complete unidirectional cell.
Ensures Vdd level is written. Referring to FIG. 12, a sense amplifier for a dynamic RAM array is shown in accordance with another embodiment of the present invention. As previously mentioned, the sense amplifier consists of a pair of N-channel driver transistors N1 and N
2, and a pair of P-channel pull-up transistors P1 and P2. N
The channel transistors consist of a pair of N-channel transistors with sensing clocks S1 and S2 on their gates.
Ground node Ng via transistors N3 and N4
The P-channel transistor is coupled from node Nh to Vdd through a P-channel transistor P3 which has S2 at its gate, which is the complement of the sense clock S2. Sensing nodes 1 and 2 at the drains of the N-channel transistors are connected to bit lines B1 and B.
It is connected to 2. According to this embodiment of the invention, N-channel transistors N1 and N2 are used for initial sensing by activating S1, while P-channel transistors P1 and P2 have no sensing function and are unidirectional. It just pulls up the bit line. Bit lines B1 and B2 are each coupled to a number of one transistor memory cells, each memory cell having a storage capacitor Cs and an N-channel access transistor Ns. One cell is selected by the word line Xw voltage. Dummy capacitor Cd and access transistor Nd
There are cells on each line. The dummy row line opposite the selected word line is activated by the Xdum voltage. The operating order of the elements of the sense amplifier in FIG.
This is shown in the timing diagram of FIG. During precharge cycles prior to t1, bit lines B1 and B
2, together with nodes Ng and Nh, are precharged to 1/2Vdd via transistors not shown.
The selected Xw and Xdum voltages rise from 0 to the Vdd level at time t1, turning on one of the cell transistors Ns and one dummy transistor Nd on the opposite side of the sense amplifier. This causes bit lines B1 and B2 to
shares charge with a storage capacitor Cs on one side and a dummy capacitor Cd on the other side. The precharge level and size of these capacitors are
Bit line with Cs connected to bit line.
The composite voltage appearing on the line is higher or lower than the composite voltage on the dummy side, depending on whether 1's or 0's are stored. Thus the bit line and the sensing node are t
The voltage separates just after 1. This voltage difference is applied to the node (bit line and transistors N1, N
2, P1, and P2). At time t2, sense clock S1 begins ramping towards Vdd, turning on transistor N3 and initiating operation of the cross-coupled flip-flop circuit. One of nodes 1 and 2 is attenuated toward 0, and the other is not attenuated. The size of transistor N3 is such that when reading the 0 stored in capacitor Cs on the bit line B1 side, transistor N2 is
It is chosen to be sufficiently gradual so as not to turn on transistor N1 when reading a 1 (even in the case of unbalanced conduction). It is important that N-channel transistors N1 and N2 perform the initial sensing. This is advantageous because N-channel transistors have a relatively higher conductivity than P-channel transistors, and are therefore smaller in size for a given amplification of the bit line signal, making it easier to use on-chip transistors. This is because area is saved. When S2 goes high at time t3, the 0-way bit line B1 or B2 connects to N-channel transistor N1 or N2 and transistor N4.
Because 2 quickly discharges to ground via , and 2 falls after the gate delay, the 1-way bit line is at the same time as 0-way node 1 or 2 goes low enough to turn on the P-channel transistor. It is charged from the Vdd supply through P-channel transistor P1 or P2 and transistor P3. Although the 2 clock may occur simultaneously with S2 without a slight delay, it is desirable for N4 to turn on before P3 to reduce peak current. If the N-channel transistors N1 and N2 and the P-channel transistors P1 and P2 have the same absolute value for their threshold voltages, and the node Ng is already less than Vdd/2, the latching behavior will be It begins to accelerate, and one side is recovered by the P-channel transistors P1 and P2. In this method, the size of transistor N4 is selected for latch speed, and transistor P3 is only large enough to restore the Vdd level in one direction to Vdd;
Power is thereby saved. For example, for a given channel length, the gain of transistor N4 is greater than the gain of transistor P3. The gain of transistor P3 is greater than the gain of transistor N3. The circuit of FIG. 12 has several advantages. Signal latching is faster due to the higher mobility in N-channel devices, and the sense transistor can also be made smaller, saving area on the chip. Additionally, the P-channel pull-up transistor can be smaller because the N-channel device completes its latch function before turning on the P-channel device. The small size of both the N-channel and P-channel transistors has the added benefit of lower current consumption. Bit lines B1 and B2 are connected to data I/O by column select transistors, not shown.
coupled to the circuit. For the selected column, the bit line is driven rail-to-rail at time t3 so that the data bit is coupled to the data I/O circuit for output from the chip. The currents flowing into and out of the chip in the Vdd and Vss lines are dense, isolated from those contributing to the sense amplifier.
This is important for DRAM. Before t2 there is no current in the sense amplifier, and some current starting at t2 flows to Vss as the zero side begins to discharge, but the resistance of transistor N1 is large. At t3, the current pulse becomes larger as the 0 side bit line is further discharged, then the Vdd pulse appears as the 1 side is charged, but the total current is spread over a longer time, so the peak current is become smaller. Of course, there will be other current peaks when falls, when falls, and when goes high (precharging begins). From FIG. 14, sense amplifier 26 of the device of FIGS. 3-5 is constructed using the features of FIG. 12 for N-channel sensing according to the embodiment of FIG.
One of them is shown in detail. Also shown in this figure are the two bit lines 33 for the sense amplifier and four of the 512 row lines 34 perpendicular to these bit lines. The sense amplifier is
12 with N-channel driver transistors N1 and N2 and P-channel pull-up transistors P1 and P2.
It uses CMOS cross-coupled flip-flops. Sensing nodes 1 and 2 are connected to bit line 33 via the source-drain paths of isolation transistors T1 and T2. This flip
The ground-side node Ng of the flop is connected to ground via two N-channel transistors N3 and N4, which have sensing clocks S1 and S2 on their gates. Since transistor N3 with S1 on its gate is much smaller than the other transistor N4, and since clock S1 occurs first, the first N-channel sensing is in a low gain state and is performed by N-channel transistors N1 and N2. The node Nh on the Vdd side is coupled to the power supply via a P-channel transistor P3 having a sense clock 2 at its gate. Since sense clock 2 is the complement of S2, P-channel transistor P3 begins to operate only after clock S2 is activated. Transistor sizing is as described above. There are two interval sensing operations, first S1 (relatively low current level), then S2 and 2. Transistors N3 and N4 and transistor P3 are shared by all of the other sense amplifiers 26 in the two blocks 10a and 10b, ie, 1024 sense amplifiers. Nodes Ng and Nh are E
When is high, approximately 1/
Precharged to 2Vdd. Bit line 33 is precharged and connected to three transistors 8 with equalizing clock voltage E on their gates.
It is equalized through 4. These transistors 84
Two of them have their respective sources connected to the reference voltage Vref
It is connected to the. The value of this reference voltage is approximately 1/2
Vdd, so little or no net charge is required from the chip power supply Vdd to precharge all the bit lines. That is, one of the lines 33 for each sense amplifier appears to be high and the other low, so one charges the other and
Vref only supplies any difference that may occur. When clock E goes high, control circuit 31 is activated after the active cycle ends.
occurs in Each memory cell in FIG. 6 is constructed by a capacitor Cs and an access transistor Ns exactly as in FIG. It is connected to the. in the block
Since only one row line 34 of the 512 is turned on at any one time, only one memory line 34 is turned on at any one time.
Cell capacitor Cs is given sense amplifier 2
6 bit line 33. Row decoder 11a or 11b is segment selection voltage
SS selects the appropriate one of the 16 lines 89 and at the same time the decoder selects the appropriate one of the 16 lines 89 based on some of the same 9 address bits from line 14.
1 row line 34 out of 512 is selected. In dummy row 32, a pair of dummy cells is provided for each pair of bit lines 33. One bit of the row address is used by the row decoder to select one or the other of these lines 92 of the dummy cell row 32. From FIG. 15, the operating order of the memory device is illustrated for a single bit read operation. As mentioned above, when the voltage drops to zero, the activation cycle begins. Since this example is a read cycle, the R/input voltage is +5V at this point. The time before this is the precharge cycle;
During that time, the equalization voltage E is high, so the bit
All of line 33 and nodes Ng and Nh are approximately 1/
It is precharged to the Verf voltage, which is thought to be 2Vdd, or +2.5V. Since the segment select signal SS appearing on all lines 89 is high, all of the segments 87 are also precharged to the Verf voltage.
The drop in RAS causes the equalization voltage E to drop, isolating the pair of bit lines 33 from each other and from Verf. The next time segment select signal SS falls, all of segment 87 will be on bit line 3.
Isolated from 3. While the row decoders 11a, 11b have time to respond to the row address, at time t1 the Xw and Xdum voltages are on the selected 1 of 512 row line 34 and the selected 1 of 2 dummy line 92. The segment selection signal begins to rise and appears on one of the lines 89 at the same time t.
SS will be increased. These address voltages Xw are
Xdum and SS are raised rather slowly,
Later, some time after reaching the Vdd level, SS
and Xw are boosted above Vdd to eliminate the Vt drop across access transistor Ns and 88. The function of the dummy cell is completed during the first sensing and the dummy capacitor is decoupled from the bit line so that it is precharged.
Xdum voltage drops. At time t1, sense amplifier 26 is first activated (at a low level) by the S1 voltage going high, turning on N-channel transistor N3. This begins to separate the bit lines 33 beyond the separation caused by the differential voltages of the storage cells and dummy cells. However, through transistor N1 or N2, the power supply Vss
Before a large current flows through, the T voltage drops,
Bit line 33 is isolated from sensing nodes 1 and 2. After the T voltage drops, the sensing voltage S2
is increased at t3, so the large transistor N4
begins to conduct. 2 also falls, so the P-channel pull-up transistor P3 begins to conduct. After S2 rises and 2 falls, the T voltage is raised to Vdd at time t4. After isolation transistors T1 and T2 are turned back on, the bit line is placed in a rail-to-rail condition. One bit line 33 is high and the other bit line 33 is zero. Sense amplification selection voltage SAS1 or SAS
2 (selected by address bit 27) is turned on and the fifth
One of the sense amplifiers is connected to buffer 24 via line 37 in the figure. Immediately after this, the Y select output from the column decoder becomes valid so that the selected data bit becomes valid on line 16, and shortly thereafter the data bit becomes valid at output pin 19. (Effects) According to the present invention, it is possible to save power consumption during operation of a sense amplifier and improve power efficiency. The following sections are further disclosed in connection with the above description. (1) a pair of bit lines and a plurality of memory cells connected to each bit line; an intersection having a ground node and a voltage source node; and a pair of sense nodes; a coupled latch circuit; a voltage source arrangement including a ground arrangement including a first transistor device; and a voltage source arrangement including a second transistor device, each transistor device having at least one source-drain path and one gate; - the drain path is connected between the ground node and the ground device, and the source-drain path of the second transistor device is connected between the voltage source node and the voltage source device; a voltage source arrangement; a means for coupling the pair of sensing nodes to the pair of bit lines; and a voltage source arrangement for coupling the pair of sensing nodes to the pair of bit lines; a control device for selectively actuating gates and then actuating selected ones of the gates of the transistor device at a second time after the first time of the actuation cycle. Sense amplifier circuit for devices. 2. The sense amplifier circuit of claim 1, wherein the first transistor device is a pair of N-channel transistors and the second transistor device is a P-channel transistor. 3. The sense amplifier circuit of claim 2, wherein the latch circuit is a CMOS latch having a second pair of N-channel driver transistors and a second pair of P-channel transistors. (4) The control device operates the selected one of the gates of the transistor device at the second time after the first time depending on an address applied to the memory device. A sensing amplifier circuit according to item 3. (5) The sense amplifier circuit according to item 4, wherein the memory cell is a one-transistor dynamic MOS read/write memory cell. (6) A sense amplifier circuit for a semiconductor memory array having a row line for selecting a cell based on an address and a bit line perpendicular to the row line and connected to the cell, the circuit having a differential input; a bistable latch circuit having first and second power supply nodes, each differential input being coupled to one of the bit lines for sensing the voltage present; first and second transistors having a source-drain path connected in parallel between the first power supply node and one terminal of the power supply, the first transistor having a high resistance and having a high resistance; the first and second transistors having gates connected to a first clock voltage, and the second transistor having a low resistance and having its gate connected to a second clock voltage; A source connected between the node and the other terminal of the power supply.
a third transistor having a drain path;
said third transistor having a high resistance and having its gate connected to a third clock voltage; applying said first clock voltage to the gate of said first transistor at a given time of an operating cycle; and a clock device for applying the third clock voltage to the gate of the third transistor at a later stage in the cycle. (7) a controller responsive to the address for selectively applying the second clock voltage to the gate of the second transistor at a certain time in the operating cycle after the given time; Sense amplifier circuit according to item 6. (8) The sense amplifier circuit according to item 6, wherein the first and second transistors are N-channel, and the third transistor is P-channel. (9) The sense amplifier circuit according to item 8, wherein the first terminal of the power source is grounded, and the second terminal is at a positive voltage. 10. The sense amplifier circuit of claim 6, wherein the bistable latch includes a pair of cross-coupled N-channel transistors and a pair of cross-coupled P-channel transistors. 11. The sense amplifier circuit of claim 10, wherein said pair of cross-coupled P-channel transistors have source-drain paths separately connecting said differential input to said second power supply node. (12) Application of only the first and third clock voltages produces a slow sensing operation, and application of the first, second and third clock voltages produces a fast sensing operation. A sensing amplifier circuit according to item 11. (13) The first cell is characterized in that the cell is a dynamic read/write memory cell.
Sense amplifier circuit according to item 2. (14) Having an array of rows and columns of partitioned memory cells that includes row lines that select cells within a group based on their address and that includes bit lines perpendicular to the row lines and connected to the cells. A semiconductor memory device comprising: (a) each sense amplifier including a bistable latch circuit having a differential input and having a positive supply node and a ground node; a plurality of sense amplifiers coupled to one of the lines; (b) a second sense amplifier having a gate and having a source-drain path connected in parallel between said ground node and the ground terminal of the power supply; one and a second N-channel transistor, the first transistor having a high resistance and having its gate connected to a first clock voltage, and the second transistor having a low resistance and having its gate connected to a second clock voltage. , the first and the first
(c) a third transistor having a gate and having a source-drain path connected between the positive power supply node and the positive voltage terminal of the power supply, the third transistor having a high resistance and having a high resistance; (d) said third transistor having its gate connected to a third clock voltage; (d) at a given time of the operating cycle said first transistor;
a clock device for applying a clock voltage to the gate of said first transistor and applying said third clock voltage to the gate of said third transistor after a subsequent such operating cycle; and a sense amplifier in a selected one of said groups. a control device responsive to the address for selectively applying the second clock voltage to the gate of the second transistor at a time in the operating cycle after the given time period; and the control device is not applied to the second transistor of the sense amplifier in the remaining group. (15) The memory cell is a dynamic one
15. A device according to claim 14, characterized in that it is a transistor memory cell. 16. The device according to claim 15, wherein the operating cycle is determined by an address strobe signal applied to the device. (17) A cross-coupled flip-flop circuit including a pair of bit lines, a plurality of memory cells connected to each bit line, a first transistor and a second pair of transistors, Each transistor has a source-drain passage and a gate, the source-drain passages of the first pair of transistors are connected between the pair of sensing nodes and a grounding device, and the source-drain passages of the second pair of transistors are connected between the pair of sensing nodes and a grounding device. the cross-coupled flip-flop circuit connected between the sensing node and the voltage source device; and a source-drain path separately connecting the pair of sensing nodes to the pair of bit lines. , and 1 with a gate connected to the control device
a pair of coupling transistors; activating the gate of the coupling transistor in an active cycle when the memory cell is activated to couple to the bit line; and then activating the gate of the coupling transistor in the active cycle when the grounding device is activated; A sense amplifier circuit for a memory device, comprising: the control device for deactivating the gate and then reactivating the gate of the coupling transistor. (18) The sense amplifier circuit according to item 17, wherein the first pair of transistors is an N-channel, and the second pair of transistors is a P-channel. (19) The sense amplifier circuit according to item 18, wherein the pair of coupling transistors is an N-channel transistor. 20. The sense amplifier circuit of claim 19, wherein the grounding device includes an N-channel transistor whose gate is activated during times when the gate of the coupling device is inactive. (21) The sense amplifier circuit according to claim 20, wherein the voltage source device includes a P-channel transistor having a gate that is activated after the gate of the grounding device is activated. 22. The control circuit according to claim 21, wherein the control circuit activates the gate of the coupling transistor after a variable time delay after the grounding device is activated, depending on an address applied to the memory device. Sensing amplifier circuit. (23) The memory cell is a one-transistor
Dynamic MOS read/write memory
23. The sense amplifier circuit according to claim 22, which is a cell. (24) Each cell selectively stores charge, and each block has a set of sense amplifiers arranged so that each sense amplifier selectively amplifies the charge stored in individual cells in the cell line. A memory cell of at least two blocks connected to a line of memory cells within the block, and a connection between each sense amplifier and its cell line, which connects each sense amplifier to its cell line during amplification operations. A switch device that temporarily disconnects from a line and then reconnects the sense amplifier to its respective line, with the option of making reconnections in the cell block containing the selected cell before reconnecting in other cell blocks. and the above-mentioned switch device including a time controller. (25) The sense amplifier has a power connection, and the clock circuit opens the power connection before the switch device disconnects the cell line, and then closes the power connection while the cell line is still disconnected;
25. A semiconductor memory having a combination according to claim 24, wherein the combination is connected to subsequently reconnect the cell lines. (26) There is a clock generator connected to provide cycles of different timing pulses, one such pulse being timed to initiate disconnection of cell lines in all memory blocks; Each subsequent pulse in a set is for a different cell block, and the start of the set first initiates cell line reconnection of the block with the designated cell;
25. A semiconductor memory having the combination of claim 24, wherein the semiconductor memory is responsive to a cell designation signal that then initiates cell line reconnection of the remaining block. (27) The memory has three or more blocks of memory cells, and the selectable time controller connects the sense amplifiers of different blocks to each memory cell block.
25. A semiconductor memory having a combination according to claim 24, characterized in that it is arranged to reconnect sets of lines separately and to make reconnections of each block at different times. (28) The memory is configured to operate with a voltage of a given supply voltage, and the switching device is configured to perform its switching at a switching voltage higher than said given supply voltage. 25. A semiconductor memory having the combination according to item 24. (29) Each cell selectively stores charge, and each line is connected via a transistor switch device to a separate sense amplifier to selectively amplify the charge stored in individual cells in that cell line. In a semiconductor memory having a line of memory cells, the switch device is configured to temporarily disconnect each sense amplifier from its line of cells during amplification operations, and further configured to operate at a boost voltage. The semiconductor memory characterized by: (30) a pair of bit lines, a plurality of memory cells connected to each bit line, a first pair of N-channel transistors and a second pair of P-channel transistors;
Each transistor is a cross-coupled latch circuit including a source-drain path and a gate, and each transistor has a source-drain path and a gate, and the source-drain path of the first pair of N-channel transistors is connected to a pair of sensing nodes. a third cross-coupled latch circuit connected between the sensing node and a ground device, the source-drain paths of a second pair of P-channel transistors being connected between the sensing node and a power supply device; the grounding device including a pair of N-channel transistors, each transistor having a source-drain path and a gate, the voltage source device including a second P-channel transistor; and the pair of sensing nodes. a coupling device for separately connecting points to said bit lines of said pair; and a coupling device for separately connecting said points to said bit lines of said pair; actuating one said gate and then actuating the other of said third pair at a second time when said grounding device is actuated, and then after said first time of said actuation cycle; , a control device for actuating the gate of the second P-channel transistor. 31. The sense amplifier circuit according to claim 30, wherein one of the third pair of N-channel transistors is much smaller than the other of the third pair. (32) The sense amplifier circuit according to claim 31, wherein the coupling device includes a pair of N-channel coupling transistors. (33) The grounding device including the third pair of N-channel transistors is connected to a ground node and a voltage source.
33. The sense amplifier circuit according to claim 32, wherein the sense amplifier circuit is connected between the Vss terminal and the Vss terminal. (34) The sense amplifier circuit according to claim 33, wherein the voltage source device includes a P-channel transistor connected to a positive voltage source terminal. (35) The sense amplifier circuit according to claim 34, wherein the control device operates the gates of the third pair of N-channel transistors and the third P-channel transistor. (36) The memory cell is a one-transistor
Dynamic MOS read/write memory
36. The sense amplifier circuit according to claim 35, which is a cell. (37) Semiconductor memory with row lines that select cells based on addresses and bit lines that are perpendicular to the row lines and connected to the cells.
A CMOS sense amplifier circuit for an array, each differential input of a CMOS bistable latch circuit having a differential input and having first and second power supply nodes coupled to one of the bit lines. The bistable latch circuit senses the voltage appearing at the
transistors, each driver transistor having a source-drain path connected between said first power supply node and one of the differential inputs, and a bistable latch circuit having a pair of cross-coupled P
said CMOS bistable latch circuit including a channel transistor, each said P-channel transistor having a source-drain path connected between said second power supply node and one of the differential inputs; first and second N-channel transistors having source-drain paths connected in parallel between the first power supply node and a reference terminal of the power supply, the first transistor having a high resistance and That gate is the first
said first and second N-channel transistors connected to a clock voltage, said second transistor having a low resistance and having its gate connected to a second clock voltage; a third P-channel transistor having a source-drain path connected between the node and the positive terminal of said power supply, having a high resistance and having its gate connected to the complement of said second clock voltage; the third P-channel transistor; applying the first clock voltage to the first transistor at a given time in an operating cycle; and thereafter applying the second clock voltage to the gate of the second transistor later in such operating cycle; and a complement of the second clock voltage to the third transistor;
The CMOS sense amplifier circuit characterized in that it has the following. (38) The sense amplifier circuit according to claim 37, wherein the pair of cross-coupled P-channel transistors have source-drain paths separately connecting the differential inputs to the second power supply node. . (39) Clause 38, characterized in that applying only the first and third clock voltages produces a slow sensing operation, and applying only the first, second and third clock voltages produces a fast sensing operation. Sensing amplifier circuit as described. (40) The sense amplifier circuit according to claim 39, wherein the cell is a one-transistor dynamic memory cell. (41) A semiconductor memory device having an array of rows and columns of memory cells including row lines for selecting cells based on addresses and bit lines perpendicular to the row lines and connected to the cells; (a) A plurality of sense amplifiers including a bistable CMOS latch circuit, each sense amplifier having a pair of sense nodes providing a difference input and having a positive node and a ground node; An input is coupled to one of the bit lines to sense the voltage appearing thereon, and the bistable latch circuit has a source-drain path separately connecting the sensing node to the ground node. the plurality of sense amplifiers including a pair of N-channel transistors and a pair of P-channel transistors having source-drain paths separately connecting the sense node to the power node; ) first and second N-channel transistors having gates and source-drain paths separately connected in parallel between the ground node and a ground terminal of a power source;
The first N-channel transistor has a high resistance and has its gate connected to a first clock voltage, and the second N-channel transistor has a low resistance and has its gate connected to a second clock voltage.
said first and second N-channel transistors connected to a clock voltage; (c) a source-drain path having a gate and connected between said positive power supply node and a positive voltage terminal of said power supply; (d) a third P-channel transistor having a high resistance and having its gate connected to a third clock voltage;
a clock device for applying a clock voltage to the gate of the first transistor and then applying the second clock voltage and the third clock voltage to the gates of the second and third transistors at a later stage in the operating cycle. The semiconductor memory device. (42) The device according to claim 41, wherein the third clock voltage is a complement of the second clock voltage. (43) The memory cell is a one-transistor
42. A device according to claim 41, characterized in that it is a dynamic memory cell. 44. A device according to claim 41, including a pair of coupling transistors separately connecting said sensing node to said bit line. (45) The device according to claim 41, wherein the gain of the third P-channel transistor is smaller than the gain of the second N-channel transistor.

[Brief explanation of drawings]

1 is an electrical schematic diagram of a sense amplifier circuit according to one embodiment of the present invention; FIG. 2 is a timing diagram showing voltage versus time relationships at various nodes in the circuit of FIG. 1; and FIG. Figure 3a is an electrical diagram in block form of a 1 megabit size dynamic memory device in which the sense amplifier circuit of the present invention may be used; single bit read (write);
Figure 4 is a block-form electrical diagram of part of the memory device in Figure 3, and Figure 5 is a block-form electrical diagram of part of the circuit in Figure 4. Figure 6 is an electrical diagram of the connection format of the sense amplifier and cell array shown in Figures 3 to 5, and Figure 7 shows voltage pairs at various nodes in the circuits shown in Figures 3 to 6. 8 is an electrical connection diagram of a sense amplifier circuit according to another embodiment of the present invention, and FIG. 9 is a timing diagram showing the time relationship.
10 is an electrical diagram of the sense amplifier and cell array connections used in the devices of FIGS. 3-5. , FIG. 11 is a timing diagram showing the voltage versus time relationship of various nodes in the circuits of FIGS. 3-5 and FIG. 10, and FIG. 12 is a sense amplifier according to another embodiment of the present invention. The electrical connection diagram of the circuit, Figure 13 is a timing diagram showing the relationship between voltage and time at various nodes in the circuit of Figure 12, and Figure 14 is a diagram of Figures 3 to 5.
Electrical diagram of the connection format of the sense amplifier and cell array of this example used in the device shown in Figure 1.
FIG. 5 is a timing diagram showing the voltage versus time relationship at various nodes in the circuits of FIGS. 3-5 and 14. FIG. Explanation of symbols: N1, N2, N3, N4, P1,
P2, P3, P4...transistor; B1, B2
... Bit line; 1, 2 ... Node point; 10
a, 10b, 10c, 10d...Memory cell
Array; 11a, 11b...decoder.

Claims (1)

Claims: 1. A sense amplifier for a semiconductor memory device, comprising: a memory cell addressing line; a sense amplifier that senses a voltage on at least one of said lines; and connected to said sense amplifier. and a power supply return circuit having first and second resistance paths connected in parallel, the resistance of the first resistance path being smaller than the resistance of the second resistance path, and the second resistance path A sense amplifier for a semiconductor memory device, wherein the sense amplifier is selected when the line is being refreshed, and wherein at least the first resistive path is selected when the line is being addressed. 2. A sense amplifier according to claim 1, characterized in that the first and second resistance paths include at least two transistors, one transistor having a larger size than the other transistors, Sense amplifier for semiconductor memory devices.