JPS61117792A - Cmos sensing amplifier with limited instantaneous power - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to semiconductor devices, and more particularly to sense amplifier circuits for dynamic read/write memory devices.

Dynamic MOS read/write memory devices are available in White, McAdams, and Redwine.
U.S. Pat.
as shown in U.S. Pat. As commonly fabricated memory devices of this type are manufactured to higher densities, such as 256 and over 1 megabit, the problem of limiting the peak current supplied to the chip becomes more difficult.

1 megapits refreshed at 512 per cycle)
In DRAM, 2 flips simultaneously during the active cycle.
There are 048 sense amplifiers (sense amplifier 7°).

Each one of these requires a current to charge the bit line to Vdd, discharge the bit line to Vss, or both, depending on the precharge level.

Thus, the voltage source to the chip experiences very large current spikes for short periods of time, and as the access time is increased, the magnitude of the current spike increases. Thus, it has been advisable to carefully size the latch and return transistors to minimize unnecessary current consumption. U.S. Patent IJ 4,050,061, issued to Nori Kitagawa, assigned to Texas Instruments, Inc., teaches that by partitioning an array into blocks and fully activating a sense amplifier only in the addressed blocks, ,
A method of limiting peak current is disclosed. In this case the other blocks are operated at a lower level and at a slower speed.

In dynamic RAM, the sensing operation depends strictly on latch-transistors. These transistors must be balanced with threshold voltages Vt and KP to within 10 degrees to operate reliably. N channel・
Prior art sense amplifiers using only transistors are
An active pull-up circuit was required to create complete rail-to-rail isolation of the bit lines. The CMOS latch provides rail-to-rail isolation with such a puller 7' circuit fx. However, when the latch is first detected, P
Uncertainty occurs when channel transistors are used.

A primary object of the present invention is to provide an improved sense amplifier circuit for high density dynamic RAM devices, particularly for high speed, low power devices.

Another object is to provide a sense amplifier circuit for a CMOS dynamic RAM that minimizes peak current. Another object is to provide a sense amplifier circuit for a CMOS dynamic RAM that minimizes size and improves reliability. Another object is to provide high speed, low current circuits for semiconductor devices, including bistable or latch circuits.

According to one embodiment of the present invention, dynamic read/
A CMOS sense amplifier circuit for write memory uses cross-coupled N-channel transistors and cross-coupled P-channel transistors returned to a voltage source, with P and N-channel transistors selectively activated by a sense clock. Ground through another two sets of transistors. The return transistor is operated in either fast sensing or slow sensing depending on the address. Selected columns are sensed at maximum speed, and unselected columns that are only being refreshed are sensed at a slower speed. The large return transistor is switched into a dedicated fast sensing circuit, while other smaller transistors perform the slow sensing function with a high resistance return to the voltage source such that the peak or instantaneous current is lower. In another embodiment, the differential inputs of the sense amplifiers are coupled to be held on when the two P lines and the dummy O line go high, and turned off while the next busy sense amplifier is activated by the sense clock. Connected to the bit line via a transistor. The coupling transistor is then turned on in the selected column before being turned on in the unselected column. Due to these features, the current required to charge and discharge the bit, line is thus spread out and the peak current is reduced. According to another feature, the N-channel transistor is used for initial sensing, and then both the N-channel and P-channel transistors are used in order of amplification to restore the 1 level. This results in better balance and allows the use of smaller N and P channel-latch transistors, saving area and power, and increasing speed.

The novel features of the invention are pointed out in the claims. However, the invention itself, as well as other features and advantages thereof, may be best understood from the following detailed description taken in conjunction with the accompanying drawings.

Referring to FIG. 1, a sense amplifier circuit for a dynamic RAM array is shown in accordance with one embodiment of the present invention. The sense amplifier of this example uses a CMOS cross-coupled clip-frozen circuit comprising a pair of N-channel driver transistors N1 and N2 and a pair of P-channel sol-up transistors P1 and P2.

The N-channel transistors are grounded through a pair of N-channel transistors N3 and N4 with respective gate busy sensing clocks S1 and B2, and the P-channel transistors are the complement of the sensing clocks S1 and B2 on their respective gates. V through a pair of P-channel transistors P6 and B4 with
(1(l). Sensing nodes 1 and 2 at the drains of the N-channel transistors are coupled to bit lines B1 and B2.

Bitni lines B1 and B2 are each coupled to a number of one-transistor memory cells.
The cell has a storage capacitor C8 and an N-channel access
A transistor Ns is provided. One cell is selected by the word line Xw voltage. The dummy cells in each line include a dummy 〇 capacitor Cd and an access transistor Nd. The busy dummy on the opposite side of the selected work line
um is actuated by pressure.

The sequence of operation of the elements of the sense amplifier of FIG. 1 is shown, by way of example, in the timing diagram of FIG. 2.

The selected Xw and Xdum voltages go from 0 to the Vdd level at time t1, turning on one transistor N8 and one transistor Nd on opposite sides of the sense amplifier. This causes bit lines B1 and B2 to share charge with storage capacitor C8 on one side and with dummy 0 capacitor Cd on the other side.

The precharge level and size of these capacitors are such that the voltage appearing on the bit line with Cs connected to it is higher or lower than the voltage on the dummy side depending on the storage of a 1 or 0. The bit line and sense node are thus separated at a voltage just after tl. This voltage difference is determined by nodes 1 and 2 (transistor N1
, N2, Pl, and the gates of B2).

The circuit of FIG. 1 can be operated using either N-channel sensing or P-channel sensing. Assuming that an N-channel type is used, at time t2 the sensing clock S1 is Wad
, Sl drops and transistors N3 and B6
turns on, causing the cross-coupled slip-flop circuit to start operating at a high impedance level, i.e., at low gain. One of nodes 1 and 2 decays slowly towards 0, the other towards Vdd Vc. At this point, little current is consumed because transistors N3 and B
This is because the series resistance of No. 3 is high. One of the larger transistors N4 or B4 must be turned on to bring the bit lines B1 and B2 to full d(L and 0 levels) with fast sensing. For this purpose, the N-channel sensing According to the example, voltage S2 is the column in which this is selected.

If there is, it becomes VdcL at time t3. The 0-way bit line B1 or B2 is rapidly discharged to ground through an N-channel 1 transistor N1 or N2 and a large transistor N4. One-way bit line is Vdd
i through P-channel transistor P1 or B2 and transistor P3, i.e., in this example of N-channel sensing, large transistor P4.
is not used, but on the other hand for P-channel sensing,
Transistor P4 is activated by 82 at t3, but
Transistor N4 is not used.

A large high gain transistor N4 (or Pa), shown as time t4 in FIG.
The time required to achieve complete rail-to-rail separation of lines is too long to obtain reasonably fast access times with dynamic RAM. Thus, in large DRAMs where the number of cells in a row that are busy being called for refresh is greater than the number that is being called for data 10, the sense amplifier can have 82 (or 82) voltages selectively applied. . 82 is added, the D side quickly drops to 0 at t6 as seen in FIG. 2, and the data bit is sensed for read operations much faster than at t4 in this situation.

Bit lines B1 and B2 are coupled to the data 10 circuit by column select transistors, not shown. For the selected column, the bit lines are driven apart at time t3 so that the data reference bits are coupled to the data output circuit for output from the chip. Other columns not selected with fast sensing are simply refreshed, so the time delay until t4 is not disadvantageous since there is plenty of time until the end of the active read cycle.

Also shown in FIG. 2 are currents into and out of the chip in the Vdd and Vss lines, separated for the contribution by the sense amplifier. There is no current in the sense amplifier until t2, and this current pulse at t2 is small because the series resistance is large. At t6, there is a current pulse as the selected line is rapidly charged and discharged, but the current in the unselected bit line is spread out over a longer period of time, so the peak current is smaller. Of course, there will be other current peaks (not shown) when RAS drops, when CAB drops, and when RAS goes to 7.i (precharge begins).

Referring now to FIG. 3, a block diagram of an example semiconductor dynamic read/write memory chip is shown that can use a sense amplifier circuit constructed in accordance with another embodiment of the present invention. . This device is
220 or 1,048,5 in an array of rows and columns
It is a so-called 1-bit device with 76 memory cells. The array consists of four identical blocks 10a,
1 (41).

It contains 1262,144 cells, 10c and 10 (partitioned into L, each pro/d). Within each block there are 512 row lines, and every row line is connected to one of the row decoders 1ia or 111). Each row decoder 11a or 11b, row address latch 13 and rider create a row select voltage as described above. A 10-bit column address is also applied to input pins 12&C in a time multiplexed manner and this column address is coupled to buffer 15. Eight data lines 16 are placed in the center of the array, and one of these eight lines is selected by a one of eight selector 17 for data input or data output. One I10 line from this selector 17 is connected to data output pin 18 and data output pin 19 via a buffer. Selector 17 receives three bits of column address on line 20 from column address buffer 15. Two of the eight lines 16 are connected to each block 10a by the construction 10 lines 21, respectively.
10b, 10c and 10 (connected to l. 16
The middle two column selections are performed in 16 intermediate output buffers 22 for each block using three bits of the column address on line 23 from buffer 15. Column selection of 1 of 16 is 4 of column address of line 25 from buffer 15.
The 16 bits in each block 1Qa-104
This is done for each of 16 sets of intermediate output buffers 24.

There are 512 sense amplifiers 26 in each block, each one connected to one of the columns in the array (as in FIG. ).

Each buffer 24 is coupled to one of two columns. This selection is based on one bit of the row address from buffer 13 on line 27.

The memory device receives a row address strobe RA8 at input pin 28 and a column address strobe RA8 at input pin 29.
Receive strobe. Selection of read or write operation is performed by R/W control of the input bin 30. Clock generation and control circuit 31 generates all internal clocks and controls as required. For a single bit read (or write), RAS and CAS are
It descends to 0 in the order shown in the figure, and the 1-bit data
A read (or write) occurs.

Each block of the array is manufactured by the aforementioned patent no. 4,293.993 or 4,0 no. 1,7 (41
2. Two rows of dummy cells 32 are included in the conventional manner as described in the above.

From FIG.
and 24, and sense amplifier 26 are connected to the processor 10a-io.
One part of a is shown in detail. There are 16 intermediate output buffers 22 in a given block, represented in this figure by 22-1...22-16. Buffers 22-1 to 22-8 are groups of eight buffers that are combined with one of the lines 16 of this block, and buffers 22-9 to 22-16 are connected by line 21 to the other lines 16 of this block. One group is connected to another group of eight buffers. 1
In each one of the six buffers 22-1...21-16, there are a set of 16 buffers 24. Here these sets are represented by 24-1 to 24-16 (16 in each set).

Each group of 16 buffers 24 is provided with a group of 32 sense amplifiers 26, each sense amplifier 26 being connected to two of the bit lines 33 (one column is the bit line in FIG.・2 bits corresponding to line B1 and B2 busy・
line).

Intersecting the bit war lines 33 are 512 row lines 34 in the memory cell array. Dummy row line 32 also intersects bit line 33 as described below. One of the two dummy lines is 9-bit row Ares 1
Selected by row decoders 11a and 11b using 1 bit of 4.

The tenth bit of the row address from buffer 13 is applied by line 2γ to a multiplex circuit for sense amplifier 26 and connected to the second level intermediate buffer 24Vc by line 37 in each pair of two sense amplifiers. Select the one you want. This block has 16 pairs of data/data per lines 38 and 39, 6 pairs connected on one side to the selected buffer 24 by line 40 and to the selected buffer 22 on the other side by line 41. ing. It is noted that the line 10 changes from dual rails on lines 38 and 39 to a single rail on the data I10 line 16 for write operations.

From FIG. 5, a portion of the circuit of FIG. 4 is shown in detail. , a sense amplifier 26 is shown combined with a set of 16 buffers 24-1.

There are actually 62 sense amplifiers 26 in this set.

This set of 16 buffers 24-1 is 2 in this figure.
4-1-1 to 24-1-16. Each individual amplifier 26 has two bit lines 3 emerging from it in a so-called folded bit line structure.
Has 3. Thus, all two-V lines 34 and both dummy rows 32 are on the same side of the sense amplifier. The row lines 34 intersect the bit lines, and the memory cells are at the intersection of the folded row or word write lines and bit lines, just as in FIG. A multiplexer 42 for the six pairs of sense amplifiers 26 selects which one to connect to each buffer 24-1-1, 24-1-2, etc. from line 37 based on the address bits on line 27. . 16 buffers 24-1-1 to 2
Only one of lines 4-1-16 is selected at any one time based on the 2504 row address bits;
Therefore only one line 38 .
39VC will operate to combine read or write bits of data in and out. Buffer 22-1 of FIG. 5 is used to couple dual rail I10 lines 38, 39 to the single rail I10 lines 16 of this group, selecting two of the 16 supplied by the three pits of line 23. It may or may not be selected.

From FIG. 6, one of the sense amplifiers 26 made in accordance with the present invention is shown.
are shown in detail. The figure also shows the two bit lines 33 for this sense amplifier and four of the 512 row 2-ins 34 perpendicular to these bit lines. The sense amplifier uses a CMOS cross-coupled flip-flop as shown in FIG. 1 with N-channel r driver transistors N1 and N2 and P-channel pull-up Φ transistors P1 and P2. Sensing nodes 1 and 2 are connected to bit line 33.

The ground node Ng of this clip 70 tube is connected to ground through two N-channel transistors N3 and N4 having sense clocks S1 and S2 on their respective gates. Transistor H3, which has the first gate at its gate, is much smaller than the other transistor N4, and clock s
1 occurs first, so the initial sensing is in a low gain state. On the /dd side, node Nh is coupled to the power supply via P-channel transistors P3 and P4 with detection clocks S1 and S2 on their respective gates. (Sensing clocks S1 and S2 are shown in such a way that channel sensing may be used. In an actual circuit, either one of transistor N4 or transistor P4 would be selected and its clock S2 or 82 would be omitted.) are sl and s
2's complement, where the P-channel transistor P
3 and P4 only begin to operate when clocks s1 and 82 are activated. There is a two-interval sensing operation, first at Sl (at low current level) and then at 82 (or 82). Transistors N3 and N4 and P6 and P4 can be unique to each sense amplifier, or alternatively shared by all of the other sense amplifiers 26 in the two blocks 10a and 10b, ie 1024 sense amplifiers. . Nodes Ng and Nh are precharged to about 1/2vdd by transistor 83 when E is high.

Bit line 33 is precharged and equalized through three transistors 84 having an equalized clock voltage E on their respective gates.

Two of these transistors have their sources connected to the reference voltage Vref. This reference voltage value is approximately 1/2vdd
, so little or no net charge is required from the current supply V(1) to precharge all of the bit lines; i.e., one line 33 of each sense amplifier is high and the others are Since the E line is low, one charges the other and Vref hardly needs to supply any difference that may occur.Clock E
is generated to control circuit 31 after the activation cycle is completed when RAS goes high.

Each memory cycle in FIG. 6 consists of a button, a capacitor Cs, and an access transistor N8 exactly as in FIG.
All gates of s are connected to row line 34.

Since only one row line 34 of the 512 in the block is turned on at any one time, the sense amplifier 26 bit line 33Vc connection is provided with only one memory cell capacitor Cθ. be done. bit·
Multiple bit line segments 87 are used for each village bit line 33 to reduce the ratio of line e capacitance to the value of storage capacitor C8. One of these segments 8γ is coupled to bit line 33 at a given time by one of transistors 88. For example, each segment 87 has three
Since there can be two cells, the embodiments disclosed herein have one of these segments 87 for each sense amplifier.
There must be 16 (16x32=512
). Half of the segments are connected to one bit line and the other half to the other bit line. Row decoder 11a
or 11b, this decoder selects one row line 34 of 512 based on some bit of the same 9 address bits from line 14, while the segment select voltage SS selects the appropriate one of 16 lines 89. Select.

In the dummy row 32, a pair of dummy cells are connected to the dummy row 32.
, and a pair of dummy cells are placed on bit line 3 of each village.
As mentioned above, these dummy cells are constituted by dummy capacitors Cd and access e-transistors Nd. When the selected storage cell is on the left-hand bit line 33, the right-hand dummy cell is placed on one of the decoder output lines 92 in the usual manner.
selected in row decoders 11&, 11b, and vice versa. One bit of the row address is used in the row decoder to select one or the other of these lines 92 of the dummy cell row 32.

From FIG. 7, the operating order of the memory device is illustrated for a single-bit read operation. Active cycle is +5
It begins with the RAS voltage dropping from to zero. This example is an IJ-r cycle, so at this point R/W
The input voltage is +5. The time before this is the precharge cycle, during which the equalization voltage E is high, so all of the bit lines 33 and nodes Ng and Nh are at the Vref voltage, which is believed to be approximately "/2Vad or +2°5. Segment select signal BB, which appears on all lines 89, is high, so segment 87
All of the batteries are also precharged to pressure Verf. The drop in voltage causes the equalization voltage E to drop, isolating the pair of bit lines 33 from each other and from Vref.

Next, the segment selection signal SS falls and the segment 8
7 from bit line 33. As soon as the time for the row decoders 11a, 11b to respond to the row address is reached, at time t1, Xw returns to Xdum it.
Pressure begins to rise with the selected 1 of 512 row line 34 and the remaining 1 of 2 dummy line 92. At the same time t1, a segment selection signal SS is generated on one of the lines 89. These address voltages Xw,
Xdum and BB are generated rather slowly and later, SS and Xw are boosted above Vdd for a short time after reaching the vdd level to eliminate the Vt drop across access transistors N8 and 88. The dummy voltage drops during initial sensing as the dummy cells complete their function, and the dummy capacitors are decoupled from the bit lines so that these capacitors can be precharged. At time t2, sense amplifier 26 is first activated (at a low level) by the S1 voltage going high;
High impedance N-channel transistor N3 and high impedance N-channel transistor P3 are turned on. This begins to isolate the bit lines 33 further than the isolation due to the differential voltages of the storage cells and dummy cells. At this point, the current flowing to ground from the power supply Vd (L or through transistors N1, N2, Pl and P2 is only minimal. With the selected sense amplifier, the sense voltage S2 is generated at t3 (or s2 is ), so large transistor N4 (or P4)
begins to conduct, bringing the bit line to a rail-to-rail condition more quickly. One bit line 33 goes high and the other goes to O. Sense amplifier selection voltage SAS 1
or SAS 2 (selected by address bit 27) is turned on to connect one of the sense amplifiers to buffer 24 via line 37 in FIG. 5 using multiplexer 42. Just before this, the Y select output from the column decoder is valid, so the selected data bit becomes valid on line 16, and shortly thereafter, the data bit becomes valid on output bin 19.

Selection of which sense amplifier is activated to produce high current sensing is based on address bits. In the embodiments of Figures 3 through 7, there are 2048 sense amplifiers, half of which (including the selected column) receive the sense clock (i.e., S2), while the other half receive this sense amplifier. do not receive. One method of accomplishing this is the same as that used in multiplexer 42 to select which sense amplifier 26 connects to the circuit 10 circuit by using address bits appearing on line 27. As seen in FIG. 6, all of the sense amplifiers selected by 5AEII O have a sense clock voltage S2 applied by line 95, and those selected by sas 1 receive a sense clock voltage from line 96. address·
A pair of logic gates 9γ, which receive bit 2γ and its complement, and sense clock voltage S2, apply the appropriate voltage to transistor N4 (or P4). Thus, the 'xfL pulse that charges and discharges all 2048 pairs of bit lines is spread over twice as long, reducing the peak current.

Referring to FIG. 8, a sense amplifier circuit for a dynamic RAM array is shown according to another embodiment of the present invention. The sense amplifier uses a CMOS cross-coupled clip 7-lop circuit with a pair of N-channel driver Φ transistors N1 and N2, K and a pair of P-channel pull-up transistors P1 and P2. . An N-channel transistor has a sensing clock S on its gate.
Grounded through channel transistor N3 and also connected to P
The channel transistor is coupled to Vdd via a P-channel transistor P3 with gate S being the complement of the sense clock S. Sensing nodes 1 and 2 at the drains of the N-channel transistors are coupled to the bit lines B1 and B2 via transfer transistors according to the invention. transistor T
1 and B2 have a clock T on their gates and serve to decouple the IC sensing node from the bit line during the high current portion of the sensing operation to spread out the current drain of the power supply, i.e. reduce the peak current. do.

Bit lines B1 and B2 are each coupled to a number of one-transistor memory cells, each memory cell having a storage capacitor c8 and an N-channel access transistor N8. A 1W voltage on the word line selects one cell. There is a dummy cell in each line that includes a dummy capacitor cd and an access transistor N(L).The dummy cell in the row line opposite the selected word line is
It is operated by Ti pressure.

The operating sequence of the elements of the sense amplifier of FIG. 8 is shown in the timing diagram of FIG. Selected XW and Xdum
The voltage changes from O to Vd (L level) at time t1, and one transistor N8 and 1 on the opposite side of the sense amplifier
transistor Nd is turned off. This causes bit lines B1 and B2 to share charge by the storage capacitor Cs on one side and the dummy It capacitor CdK on the other side. The precharge level and size of these capacitors are such that the voltage on the bit line due to C8 connected to it will be higher or lower than the voltage on the dummy side, depending on whether a 1 or a 0 is being stored. Thus the bit line and the sensing node are tl
The voltage separates immediately after.

At time t2, T[pressure drops from Vaa to 0, decoupling bit lines B1 and B2 from sensing nodes 1 and 2. However, the voltage difference is maintained at the capacitance of nodes 1 and 2 (including the gates of transistors N1, N2, Pl, B2). At time t3, the sensing clock 8 goes to V(ld, S drops and transistor N3
and B3 is turned on, activating the cross-coupled clip-flop circuit. One of nodes 1 and 2 quickly drops to 0, the other to T/da. The current consumption at this point is small (current spike #1 in FIG. 9) because the capacitance to be charged and discharged is small. The capacitance of nodes 1 and 2 is much smaller than that of bit lines B1 and B2.

Transistors T1 and B2 must be turned back on to bring bit lines B1 and B2 to full Vdd and zero e levels so that selected capacitor CB is restored to full logic levels. To this end, according to this embodiment of the invention, the voltage T is changed at time t4
Or it returns to Vdd at t5, depending on whether it is the selected column or not. When T goes high at t4 or t5,
The 0-way bit line B1 or B2 is rapidly discharged to ground through the N-channel ψ transistor N1 or N2, and the 1-way bit line is photovolted from the VAA source through the P-channel transistor P1 or B2. (In Fig. 9, t flow spike #2 at t4, t5
(This corresponds to #3). This charging and discharging creates voltage bumps at sensing nodes 1 and 2, but these bumps quickly subside before the data passes to the x7o circuit.

Bit lines B1 and B2 are coupled to data 110 circuitry by column select transistors, not shown. For the selected column, the bit line is rail-to-rail driven at time t4, so the data bit is coupled from the bit line to the delta 110 circuit for output from the chip. Other columns not selected by the column decoder are only refreshed, so
The time delay until t5 is not disadvantageous because there is sufficient time for the active read tickle to finish. Again, the current spike is restored.

The current flowing into and out of the chip on the /dd and V8e lines is isolated from the contribution by the sense amplifier.
As shown in the figure. There is no current in the sense amplifier until t3, and this current pulse #1 at t6 is small because sense nodes 1 and 2 are small. , t4 and t5
Now, when the bit line is charged and discharged, the current pulse #2
and #6, but the peak current is smaller because the current is spread over a longer period of time. Of course, there will be other current peaks (not shown) when RAS falls, when CA8 falls, and when RAS goes high (precharge begins).

10, one of the sense amplifiers 26 in the devices of FIGS. 3-5 made in accordance with the FIG. 8 embodiment of the present invention is shown in detail. This figure also shows the two bit lines 33 for this sense amplifier and four of the 512 row lines 34 perpendicular to these bit lines. The sense amplifier is a C-type amplifier as shown in FIG.
I am using MO13 cross-coupled flip/70 tube.

Sensing nodes 1 and 2 are connected to bit line 3 via source-to-rain paths of isolation transistors T1 and T2.
Connected to 3. The ground node 78 of this clip 70 tube is connected to ground through two N-channel transistors N3 with sense clocks S1 and S on their gates.

Transistor N3 with the first at the gate is much smaller than the other transistors N3, and since clock S1 occurs first, the first sensing is in a lower gain state and N
This is done by channel transistors N1 and N2. Node 1 on the Vdd side is coupled to the power supply via a P-channel transistor P3 with a sensing clock S on its gate. Since the sense clock S is the complement of S, the P-channel or transistor P3 only begins to operate after clock S is activated. There is a 2-interval sensing operation,
First (at low'Wt flow levels), then S and S. Transistors N6 and P6 are connected to the two blocks 1
0a and 10b'lc are shared by all of the other sense amplifiers 26, ie, 1024 sense amplifiers. Node 78 is precharged to approximately 1/2 vdd by transistor 83 when E is high.

Bit line 33 is precharged and equalized by three transistors 84 with equalized clock voltage E on their gates. The sources of these 8402 transistors are each connected to the reference voltage Vref. Since the value of this reference voltage is approximately 1/1 vdd, little or no net charge is required from the chip power supply vdd to precharge all of the bit lines. That is, one line 33 for each sense amplifier is high and the others are low, so one charges the other and Vref only supplies any difference that may occur.

When RA8 goes high, the clock K is generated to the control circuit 31 after the active cycle is completed.

Each memory cell in FIG. 10 consists of a capacitor C8 and an access transistor Ns, exactly as in FIG.
All of the 512 access transistors N8 in a row are connected to row line 34. Since only one row line 34 out of 512 in the block is turned on at any one time, only one memory cell capacitor Cm is provided for the sense amplifier 26 by bit line 33. It is connected to the. Multiple bit line segments 87 are used for the six bit line pairs 33 to reduce the ratio between the bit line capacitance and the value of the storage capacitance Ca. One of these segments 87 is coupled to the bitna line 331C at a given time by one of the transistors 88. For example, each segment 87 may have 62 cells connected to it, so in the presently disclosed embodiment there must be 16 of these segments 87 for each sense amplifier (16
X32=512). Half of the segments are connected to one bit line and half to the other bit line. The row decoder 11a or 11b selects an appropriate one of the 16 lines 89 by the segment selection voltage SS.
At the same time as selecting a book, the decoder selects row line 34, 1 of 512, based on some of the same nine address reference bits from line 14.

In the dummy row 32, a pair of dummy cells are provided for the six pairs of bit lines 33, these dummy cells consisting of a dummy capacitor Cd and an access transistor Nd, as described above. When the selected storage cell is on the left hand bit line 33, the right hand dummy cell is connected to the row decoder 11a by the decoder output line 92 (41).

11b in the usual manner, but vice versa. One bit of the row address is used in the row decoder to select one or the other of these lines 92 (41) of the dummy cell row 32.

From FIG. 11, the operating order of the memory device is illustrated for a single bit read operation. The active cycle is R
It begins when the AS voltage drops from +5 to 0. Since this example is a read cycle, the R/W input voltage is +5 at this point. The time before this is the precharge cycle, during which the equalization voltage E is high, so the bit
All of line 33 and node 78 are approximately 2Vdd
That is, it is precharged to the Vref voltage, which is thought to be +2.5V. Since the segment select signal SS appearing on all lines 89 is high, all of the segments 87 are also precharged to the Vref voltage. The drop in RAS causes the equalization voltage E to drop, isolating the pair of lines 33 from each other and from Vref. Segment select signal SS then falls to select all of segment 87 from bit line 3.
Isolate from 3. At time t1, Xv
and Xdum pressure begins to rise at the selected 1 of 512 row line 34 and the selected 1 of 2 dummy line 92. 1 on line 89 at the same time t1
Then, the segment selection signal SS is raised. these,
The voltages Xw, Xdum and 88 are raised rather slowly, and later, some time after the vdd level has reached SS and Xw are boosted above Vdd to reduce the Vt drop across the access ψ transistors Nθ and 88. Eliminate.

The Xdum voltage drops because the dummy cell's function is completed during the first sensing and the dummy capacitor is decoupled from the bit line so that it is precharged. Until time t2, sense amplifier 26 is first connected to the first '!'! ! Activated by the voltage going high, it turns on high impedance N-channel transistor N6. This begins to further isolate bit line 33 than the isolation due to the differential voltage of the storage cell and dummy cell. However, before any significant current flows from the power supply vd(L to transistors N1, N2, Pl and P2, the T voltage drops at t2, isolating bit line 33 from sensing nodes 1 and 2. After the voltage has dropped, the sensing voltage S is increased at t3, so that the large transistor N3 begins to conduct. Also, as S drops, the P-channel load transistor P3 begins to conduct. At this point, the 9th Current spike #2 in the diagram occurs (note that the circuit is also made so that T drops before Sl goes high)
. After S rises and S falls, the T voltage is raised to Vdd at time t4 or t5 as described above. After isolation transistors T1 and T2 are turned back on, the bit line is rotated rail-to-rail. One bit line 33 is high, the other is zero. Sense amplifier selection voltage 8hS 1 or SAS 2
(selected by address bit 27) is the turn
When turned on, one of the sense amplifiers is connected to buffer 24 via line 37 in FIG. 5 using multiplexer 42. As soon as this is done, the Y select output from the column decoder becomes valid, so the selected data bit becomes valid on line 16, and shortly thereafter the data bit becomes valid on line 16.
The bit is valid at output bin 19.

The selection of the time t4 or t5 at which the T voltage is increased is based on the address bits. In the embodiments of FIGS. 6 to 5,
There are 2048 sense amplifiers, half of which (including the selected column) can receive the rising T voltage at t4 and the other half at t5. One way to accomplish this is to use the address bits on line 2γ, similar to the method used by multiplexer 421C to select which sense amplifier 26 connects to the 110 circuit. 10th
As can be seen, all of the sense amplifiers selected by SAS OIc have a T voltage applied by line 95, and the sense amplifier selected by SAS 1 receives a voltage from line 96. A pair of logic gates 9γ receiving address bit 27 and its complement and two T voltages (ending at t4. or t5) apply the appropriate voltages to transistors T1 and T, MC. Thus, 20
The current pulse that photodischarges all 48 pairs of bit lines is spread out over twice the time to reduce the peak current. The T voltage is boosted above Vaa (by circuitry not shown) to ensure that the full Vaa level is written to the unidirectional cell.

From FIG. 12, a sense amplifier for a dynamic RAM array is shown according to another embodiment of the present invention.

As previously mentioned, the sense amplifier is a CMOS cross-coupled 7-lip 70 circuit with a pair of N-channel driver transistors N1 and N2 and a pair of P-channel pull-up transistors P1 and B2. I am using it. The N-channel transistors are connected to ground from a ground node Ng via a pair of N-channel transistors N3 and N4 with sense clocks S1 and B2 on their gates, and the P-channel transistors have sense clocks on their gates. P channel ψ with day 2 which is the complement of S2
The node Nh is coupled to Vdd via the transistor P3. Sensing nodes 1 and 2 at the drain buttons of the N-channel transistors are coupled to bit lines B1 and B2.

According to this embodiment of the invention, N-channel transistors N1 and N2 are used for initial sensing by activating Sl, while P-channel transistor P1
and B2 have no sensing function and only pull up the one-way bit line.

Bit conflict lines B1 and B2 are each coupled to a number of one-transistor memory cells, with each memory
The cell has storage capacitor Cs and N channel write access.
and a transistor Is. One cell is two
- Selected by the 1W voltage of the line. There is a dummy cell in each line, including a dummy capacitor Cd and an access transistor Nd. The dummy row line opposite the selected word line is activated by Xdumfl (pressure).

The operating sequence of the elements of the sense amplifier of FIG. 12 is shown in the timing diagram of FIG. In the precharge period before tl, bit lines B1 and B2 are connected to 1/2 through transistors not shown, along with nodes Ng and Nh.
Precharged to 2vdd. Selected Xw and Xd
The um voltage rises from 0 to the Vaa level at time t1 to 1 of the cell transistor Is on the opposite side of the sense amplifier.
and one dummy Φ transistor Nd are turned on. This causes bit lines B1 and B2
shares charge with a storage capacitor Cs on one side and a dummy capacitor Cd on the other side.

The precharge level and size of these capacitors, with C8 connected to the bit line, allows the composite voltage appearing on the bit line to be higher or lower than the composite voltage on the dummy side, depending on whether 1s or 0s are stored. It's like doing something like that. The bit line and sense node are thus separated in voltage just after tl. This voltage difference is applied to the node (bit line and transistor N
1, N2, pl, and B2). At time t2, sensing clock S1
begins to rise obliquely towards vda, and the transistor N
3 is turned on and the operation of the cross-coupled clip-flop circuit is started. One of the nodes 1 and 20 is attenuated toward 0, and the other is not attenuated. The size of transistor N3 is such that when reading O stored in capacitor CB on the bit line B1 side, transistor N2 is
It is chosen to be sufficiently smooth so as not to turn on transistor N1 when reading a 1 (even in the case of unbalanced conduction).

It is important that N-channel transistors N1 and N2 perform the initial sensing. This is advantageous because N
The channel transistor has a relatively higher conductivity than the P-channel transistor, so the bit
This is because for a given amplification of the line signal, the size is smaller and the area on the chip is saved.

When B2 goes high at time t3, the O-direction bit line B1 or B2 quickly discharges to ground through N-channel transistor N1 or N2 and transistor N4, and after the gate delay 82 falls, so that 1 The direction bit line is charged from the Vddli source through P-channel transistor P1 or B2 and transistor P3 at the same time that 0-direction node 1 or 2 goes low enough to turn on the P-channel transistor. Although the S2 clock may occur at the same time as 82 without a slight button delay, it is desirable for N4 to turn on before B6 to reduce peak current.

If the N-channel transistors N1 and N2 and the P-channel transistors P1 and B2 have the same absolute value for their threshold voltages and the node Ng is already smaller than vad72, the latching operation will be co-accelerated with the transistors N1 and N2. As a result, one side is restored by P-channel transistors P1 and B2. In this manner, the size of transistor N4 is selected for latch speed, and transistor P3 is only large enough to restore the Vdd level on one side to Vdd, thereby saving power. For example, for a given channel length, the gain of transistor N4 is equal to the gain of transistor P3.
is greater than the gain of . The gain of transistor P6 is greater than the gain of transistor N6.

The circuit of FIG. 12 has several advantages. Latching of signals is faster due to the higher mobility in N-channel devices, and the sense transistors can also be made smaller, saving area on the chip. On top of that,
P-channel pull-up fφ transistors can be more compact because the N-channel device completes its latch function before turning on the p-channel device. The small size of both the N-channel and P-channel transistors has the added benefit of lower current consumption.

The bit φ lines B1 and B2 are coupled to the data line 10 circuits by the illustrated inner column select transistors. In the selected column, the bit line is at time t3
Since the data bits are driven rail-to-rail, the data bits are coupled together in 10 circuits for output from the chip.

Vdd and V isolated from contributing to the sense amplifier
The current flowing into and out of the chip in the θ line is critical in high density DRAMs. Before t2, there is no current in the sense amplifier;
Some current starting at t2 flows to Vss as the zero side begins to discharge, but the resistance of transistor M1 is a dog. At t6, the current pulse becomes larger as the O side bit line is further discharged, then the Vdd pulse appears as the 1 side is charged, but the total current is spread over a longer time, so the peak current is become smaller. Of course, when RAS descends, C
Other current peaks appear to be present when A& drops and when RAG goes high (precharge begins).

14, there is shown in detail one of the sense amplifiers 26 of the device of FIGS. 3-5 made using the features of FIG. 12 for N-channel sensing according to the embodiment of FIG. This figure shows two bit lines 33 for this sense amplifier and 5 bit lines perpendicular to these bit lines.
Four of the twelve row lines 34 are also shown. The sense amplifier consists of an N-channel driver transistor N1
CMOS as in FIG. 12 with N2 and P-channel pull-up transistors P1 and P2.
I am using a cross-connected clip with 70 tubes. Sensing nodes 1 and 2 are connected to bit line 33 via source-drain paths of isolation transistors T1 and 2. The ground-side node Ng of this flip-flop is connected to ground via two N-channel transistors N6 and N4 having sense clocks S1 and S2 on their gates.

Since the transistor N3 with the first at the gate is much smaller than the other transistor N4 and the clock S1 occurs first, the first N-channel sensing is in a low gain state;
This is done by N-channel transistors N1 and N2. , Vaa side node Nh is coupled to the power supply via a P-channel transistor P3 having a sense clock 82 at its gate. Since sensing clock S2 is the complement of S2, P-channel transistor P6 begins to operate only after clock S2 is activated.

The transistor size is determined as described above.

There are two interval sensing operations, first (relatively low current level), then s2 and 82. transistors N3 and N4,
and transistor P6 connects two blocks 10a and 1
All of the other sense amplifiers 26 in 0b, i.e. 10
It is shared by 24 sense amplifiers. Node point N
g and Nh when LE is high transistor 83
The battery is precharged to approximately 1/21 tL.

The bit line 33 is precharged and equalized via three transistors 84 with a 'F''-)K equalization clock voltage E. Two of these transistors 84 have their respective sources referenced. Since the value of this reference voltage is approximately 2 vaa, little or no net charge is required from the chip power supply Vda to precharge all the bit lines, i.e.
One side of line 33 for each sense amplifier appears to be high and the other low, so one charges the other and Vr
ef only supplies any differences that may occur. Clock E is generated to control circuit 31 after the active cycle ends when RAEI goes high.

Each memory cell in FIG. 6 is constructed by a capacitor 0 and an access reference transistor Ns exactly as in FIG. It is connected to the. The only row line 3 among the 512 busy blocks
Since C4 is turned on at any one time, only one memory cell capacitor C8 is connected to the bit line 33 for a given sense amplifier 26. The row decoder 11a or 11b selects the appropriate one of the 16 lines 89 by means of the segment selection voltage se, and at the same time this decoder selects the 1 out of 512 lines based on a certain bit of the same 9 address bits from the line 14. row line 34
Select.

In dummy row 32, a pair of dummy cells are provided for six pairs of bit lines 33. One bit of the row address is used in the row decoder to select these lines 92 (41 or the other) of the dummy φ cell rows 32.

From FIG. 15, the operating order of the memory device is illustrated for a single bit read operation. As mentioned above, RAB
When the voltage drops to zero, the activation cycle begins. This example is a read cycle, at which point the R/W input voltage is +5v.

The time before this is the precharge cycle, during which the equalization voltage E is high, so all of the bit lines 33 and nodes Mg and Nh are at about 1/, Vdd or +
It is precharged to a Vref voltage which is believed to be 2.5v. Since the segment select signal SS appearing on all lines 89 is high, all of the segments 87 are also at Vref.
is precharged to pressure. The drop in RAS causes the equalization voltage E to drop, pulling the pair of bit lines 33 together and V
Isolate from ref.

The next time segment select signal SS falls, all of segments 8γ are isolated from bit line 33. Once the row decoders 11a, 11b have time to respond to the row address K, at time t1 the Xw and Xdum voltages are applied to the selected 1 of 512 row line 34 and selected 1 of 2 dummy line 92 The segment selection signal S starts rising at t and appears on one of the lines 89 at the same time t.
S is raised. These Azores voltages Xw%Xaum
and aS are raised rather slowly, and later, some time after the ld level, SS and Xw are raised to V'd
access transistor Ns
and 88 to eliminate the vt drop at both ends. The function of the dummy cell is completed during the first sensing and the dummy capacitor is decoupled from the bit line so that it is precharged so that Xdu! In voltage drops. At time t1, sense amplifier 26 is first activated (at a low level) by the S1 voltage going to NO, turning on N-channel transistor N3. This is more than the isolation caused by the differential voltage between the storage cell and the dummy cell.
Begin separating line 33. However, transistor N1
The T voltage drops to isolate bit line 33 from sensing nodes 1 and 2 before a large current flows through N2 to power supply v8G.

After the T voltage drops, the sense voltage S2 is increased at t6, so that the large transistor N4 begins to conduct. Also B
2 falls, so P-channel pull-up transistor P3 begins to conduct.

After B2 rises and B2 falls, the T voltage increases at time t
4, it will be raised to vdd. After isolation transistors T1 and B2 are turned back on, the bit cloud line is forced rail-to-rail B. 1 bit
Line 33 is noy and other bit lines 33
is 0. Sense amplification selection voltage 8A first or 8AS
2 (selected by address Φ bit 2γ) is turned on during each turn to connect one of the sense amplifiers to buffer 24 via 2-in 37 in FIG. 5 using multiplexer 42. Immediately after this, the Y select output from the column decoder becomes valid, so the selected data bit becomes valid on line 16, and shortly thereafter, the data bit goes to output bin 1.
It becomes valid at 9.

[Brief explanation of drawings]

1 is an electrical schematic diagram of a sense amplifier circuit according to one embodiment of the present invention; FIG. 2 is a timing diagram showing voltage versus time relationships at various nodes in the circuit of FIG. 1; and FIG. Figure 3a, an electrical diagram in block form of a 1 megapit size dynamic memory device in which the sense amplifier circuit of the present invention can be used, shows the states of RAS and CAB for a single bit read (write). 4 is a block-form electrical diagram of a part of the Memo IJ e device shown in FIG. 3; FIG. 5 is a block-form electrical diagram of a part of the circuit shown in FIG. 4; FIG. is an electrical diagram of the connection type of the sense amplifier and cell array of Figs. 3 to 5, and Fig. 7 shows the voltage versus time relationship at various nodes in the circuit of Figs. 3 to 6. a timing diagram; FIG. 8 is an electrical connection diagram of a sense amplifier circuit according to another embodiment of the present invention;
9 is a timing diagram showing voltage versus time at various nodes in the circuit of FIG. 8, and FIG. 10 is a timing diagram of the sense amplifier and cell array used in the device of FIGS. 5-5. 11 is an electrical diagram of the connection type; FIG. 11 is a timing diagram showing the relationship between voltage and time at various nodes in the circuits of FIGS. 3 to 5 and FIG. 10; FIG. 12 is another diagram of the present invention. Electrical connection diagram of a sense amplifier circuit according to two embodiments, 1st
Figure 3 is a timing diagram showing the voltage versus time relationship at various nodes in the circuit of Figure 12, and Figure 14 shows the sense amplifier and cell of this example used in the device of Figures 6-5.・Electrical diagram of array connection type, Figure 15 is 3rd
15 is a timing diagram showing voltage versus time relationships at various nodes in the circuits of FIGS. 5 and 14; FIG. Explanation of codes: N1. N2. N5. N4. Pl, B2. B5゜B4...
・Transistor; B1. B2... Bit cloudy line; 1
．． 2-...Node points; 10a, 10b, 10C. 10a...Memory cell array; 11a, 11b.
··decoder.

Claims (1)

[Scope of Claims] (1) having a pair of bit lines, a plurality of memory cells connected to each bit line, a ground node and a voltage source node, and a pair of sensing nodes; a cross-coupled latch circuit having a node; a grounding device including a first transistor device; and a voltage source device including a second transistor device, each transistor device having at least one source-drain path and one gate; A source-drain path of a first transistor device is connected between the ground node and a ground device, and a source-drain path of the second transistor device is connected between the voltage source node and a voltage source device. , the grounding device and the voltage source device; a device coupling the pair of sensing nodes to the pair of bit lines; and a device for coupling the pair of sensing nodes to the pair of bit lines;
control for selectively actuating the gates of the first and second transistor devices at a time and then actuating selected gates of the transistor devices at a second time after the first time of the actuation cycle; A sense amplifier circuit for a memory device, comprising: an apparatus; 2. A sense amplifier circuit according to claim 1, wherein said first transistor device is a pair of N-channel transistors and said second transistor device is a P-channel transistor. (3) The sense amplifier circuit according to claim 2, wherein the latch circuit is a CMOS latch having a second pair of N-channel driver transistors and a second pair of P-channel transistors. . (4) The control device operates the selected gate of the gates of the transistor device at the second time after the first time depending on an address applied to the memory device. A sense amplifier circuit according to claim 3. (5) The sense amplifier circuit according to claim 4, wherein the memory cell is a one-transistor dynamic MOS read/write memory cell. (6) A sense amplifier circuit for a semiconductor memory array having a row line for selecting a cell based on an address and having a bit line perpendicular to the row line and connected to the cell, the circuit having a differential input; a bistable latch circuit having first and second power nodes, each differential input being coupled to one of the bit lines for sensing the voltage present; first and second transistors having a high resistance and having a source-drain path connected in parallel between the first power supply node and one terminal of the power supply; the first and second transistors having gates connected to a first clock voltage, the second transistor having a low resistance and having its gates connected to a second clock voltage; a third transistor having a source-drain path connected between a node and another terminal of the power source, the third transistor having a high resistance and having its gate connected to a third clock voltage; applying the first clock voltage to the gate of the first transistor at a given time of an operating cycle;
and a clock device for applying the third clock voltage to the gate of the third transistor at a later stage of the operating cycle. (7) a controller responsive to the address for selectively applying the second clock voltage to the gate of the second transistor at a certain time in the operating cycle after the given time; A sense amplifier circuit according to claim 6. (8) The sense amplifier circuit according to claim 6, wherein the first and second transistors are N-channel, and the third transistor is P-channel. (9) The first terminal of the power source is grounded, and the second terminal is at a positive voltage.
Sense amplification circuit as described in section. 10. The sense amplifier circuit of claim 6, wherein the bistable latch includes a pair of cross-coupled N-channel transistors and a pair of cross-coupled P-channel transistors. 11. The pair of cross-coupled P-channel transistors having source-drain passages separately connecting the differential input to the second power supply node. Sensing amplifier circuit. (12) Application of only the first and third clock voltages produces a slow sensing operation, and application of the first, second and third clock voltages produces a fast sensing operation. A sense amplifier circuit according to claim 11. (13) Claim 1, wherein the cell is a dynamic read/write memory cell.
Sense amplifier circuit according to item 2. (14) an array of rows and columns of memory cells partitioned into groups including row lines for selecting cells within a group based on address and bit lines perpendicular to the row lines and connected to the cells; (a) each sense amplifier includes a bistable latch circuit having a differential input and having a positive power node and a ground node for sensing the voltage at which each differential input appears; a plurality of sense amplifiers coupled to one of said bit lines; (b) a source-drain path having a gate and connected in parallel between said ground node and a ground terminal of a power supply; first and second N-channel transistors, the first transistor having a high resistance and having its gate connected to a first clock voltage, and the second transistor having a low resistance and having its gate connected to a second clock voltage. (c) a first N-channel transistor having a gate and having a source-drain path connected between the positive power supply node and a positive voltage terminal of the power supply; (d) applying the first clock voltage to the gate of the first transistor at a given time of an operating cycle; a clock device for applying said third clock voltage to the gate of said third transistor after a subsequent such operating cycle; a controller responsive to the address for selectively applying the second clock voltage to the gates of the second transistors at certain times in the operating cycle; the control device not added to the two transistors; and the memory device (1)
5) A device according to claim 14, characterized in that the memory cell is a dynamic one-transistor memory cell. 16. A device according to claim 15, wherein said operating cycle is determined by an address strobe signal applied to said device. (17) a pair of bit lines, and each of the bit lines;
A cross-coupled flip-flop circuit including a plurality of memory cells connected to a line, a first transistor and a second pair of transistors, each transistor having a source-drain path and a gate, The source-drain paths of the transistors are connected between a pair of sensing nodes and a grounding device, and the source-drain paths of a second pair of transistors are connected between the sensing nodes and a voltage source device. , said cross-coupled flip-flock circuit, and a pair of couplings having source-drain passages separately connecting said pair of sensing nodes to said pair of bit lines and having a gate connected to a controller. a transistor; activating the gate of the coupling transistor in an active cycle when the memory cell is activated to couple to the bit line; and then activating the gate in the active cycle when the grounding device is activated. a sense amplifier circuit for a memory device, comprising: the control device for deactivating and then reactivating the gate of the coupling transistor. (18) The sense amplifier circuit according to claim 17, wherein the first pair of transistors is an N-channel transistor, and the second pair of transistors is a P-channel transistor. (19) The sense amplifier circuit according to claim 18, wherein the pair of coupling transistors are N-channel. (20) The grounding device comprises an N-channel transistor whose gate is activated during times when the gate of the coupling device is inactive.
A sensing amplifier circuit according to item 9. (21) The voltage source device includes a P-channel transistor having a gate that is activated after the gate of the grounding device is activated.
Sense amplification circuit as described in section. (22) The control circuit activates the gate of the coupling transistor after a variable time delay after the grounding device is activated, depending on an address applied to the memory device. A sensing amplifier circuit according to item 21. (23) The sense amplifier circuit according to claim 22, wherein the memory cell is a one-transistor dynamic MOS read/write memory cell. (24) Each cell selectively stores charge, and each block stores one
at least two sense amplifiers connected to a line of memory cells in the block such that each sense amplifier selectively amplifies the charge stored in an individual cell in the cell line; The connection between the block's memory cells and each sense amplifier and its cell line temporarily disconnects each sense amplifier from its cell line during amplification operation, and then connects the sense amplifier to its respective line. and a selectable time controller for making a reconnection in a cell block containing a selected cell before reconnecting in another cell block. Features of semiconductor memory. (25) The sense amplifier has a power connection, and the clock circuit opens the power connection before the switch device disconnects the cell line, then closes the power connection while the cell line is still disconnected, and then 25. A semiconductor memory having the combination according to claim 24, wherein the combination is connected to reconnect the cell lines. (26) a clock generator connected to provide cycles of different timing pulses, such one pulse being timed to initiate cell line disconnection in all memory blocks; Each subsequent pulse in a set is for a different cell block, and the start of the set first initiates the cell line reconnection of the block with the designated cell, and then the cell line reconnection of the remaining blocks. 25. A semiconductor memory having the combination according to claim 24, wherein the semiconductor memory is responsive to a cell designation signal for initiating a cell designation signal. (27) The memory has three or more blocks of memory cells, and the selectable time controller reconnects the sense amplifiers of different blocks to each set of memory cell lines separately and at different times. 25. A semiconductor memory having the combination according to claim 24, characterized in that it is configured to make reconnections of each block. (28) The memory is configured to operate with a voltage of a given supply voltage, and the switching device is configured to perform its switching at a switching voltage higher than the given supply voltage. A semiconductor memory having the combination according to claim 24. (29) Each cell selectively stores charge, and each line is connected via a transistor switch device to a separate sense amplifier to selectively amplify the charge stored in individual cells in that cell line. In a semiconductor memory having a line of memory cells, the switch device is configured to temporarily disconnect each sense amplifier from its line of cells during amplification operations, and further configured to operate at a boost voltage. The semiconductor memory characterized by: (30) a pair of bit lines, and each of the bit lines;
a cross-coupled latch circuit including a plurality of memory cells connected to the line, a first pair of N-channel transistors and a second pair of P-channel transistors, each transistor including a source-drain path and a gate. and each transistor has a source, a drain path, and a gate, the source-drain paths of the first pair of N-channel transistors are connected between the pair of sensing nodes and the grounding device, and the source-drain paths of the first pair of N-channel transistors are connected between the pair of sensing nodes and the ground device; - the source-drain path of the transistor is connected between the sensing node and the power supply, the cross-coupled latch circuit and the grounding device including a third pair of N-channel transistors, each of the transistors has a source-drain path and a gate, and the voltage source device includes a second P-channel transistor; a grounding device; and a coupling device separately connecting the pair of sensing nodes to the pair of bit lines; activating the gate of one of a third pair of transistors at a first time of an activation cycle when the memory cell is activated to couple to the bit line; and then the grounding device is activated. activating the other gate of the third pair at a second time when the second P-channel
A sense amplifier circuit for a memory device, comprising: a control device for operating a gate of a transistor; 31. A sense amplifier circuit according to claim 30, wherein one of the N-channel transistors of the third pair is much smaller than the other of the third pair. 32. The sense amplifier circuit according to claim 31, wherein the coupling device includes a pair of N-channel coupling transistors. 33. The grounding device including the third pair of N-channel transistors is connected between a grounding node and a Vss terminal of a voltage source.
Sense amplification circuit as described in section. (34) The voltage source device is connected to a positive voltage source terminal.
34. A sense amplifier circuit according to claim 33, comprising a channel transistor. 35. The sense amplifier circuit according to claim 34, wherein the control device operates the gates of the third pair of N-channel transistors and the third P-channel transistor. (36) The sense amplifier circuit according to claim 35, wherein the memory cell is a one-transistor dynamic MOS read/ride memory cell. (37) A CMOS sense amplifier circuit for a semiconductor memory array having a row line for selecting a cell based on an address and a bit line perpendicular to the row line and connected to the cell, the circuit having a differential input and having a bit line connected to the cell. Each differential input of a CMOS bistable latch circuit having first and second power supply nodes is coupled to one of said bit lines and said bistable latch circuit senses the voltage appearing thereon; The latch circuit consists of a matched pair of cross-coupled N-channel drivers.
transistors, each driver transistor having a source-drain path connected between the first power supply node and one of the differential inputs, and a bistable latch circuit having a pair of cross-coupled P-channels.・Including transistors,
Each of the P-channel transistors has a gate and a gate of the CMOS bistable latch circuit having a source-drain path connected between the second power supply node and one of the differential inputs. first and second N-channel transistors having source-drain paths connected in parallel between a power supply node and a reference terminal of the power supply, the first transistor being of high resistance and having its gate connected to a first clock; the first and second N-channel transistors connected to a voltage, and the second transistor having a low resistance and having its gate connected to a second clock voltage; a third P-channel transistor having a source-drain path connected between the point and the positive terminal of the power supply, the third P-channel transistor being of high resistance and having its gate connected to the complement of the second clock voltage; a third P-channel transistor; applying the first clock voltage to the first transistor at a given time of an operating cycle and thereafter applying the second clock voltage to the gate of the second transistor later in such operating cycle; and a clock device for applying the complement of the second clock voltage to the third transistor. 38. The pair of cross-coupled P-channel transistors include source-drain paths separately connecting the differential inputs to the second power supply node. sensing amplification circuit. (39) Applying only the first and third clock voltages creates a slow sensing operation;
39. A sense amplifier circuit according to claim 38, wherein application of a clock voltage produces fast sensing operation. (40) The sense amplifier circuit according to claim 39, wherein the cell is a one-transistor dynamic memory cell. (41) A semiconductor memory device having an array of rows and columns of memory cells including row lines for selecting cells based on addresses and bit lines perpendicular to the row lines and connected to the cells; (a) A bistable CM in which each sense amplifier has a pair of sensing nodes supplying differential inputs, and has a positive node and a ground node.
a plurality of sense amplifiers including an OS latch circuit, each differential input coupled to one of said bit lines to sense the voltage appearing thereon, said bistable latch circuit connecting said sense node to said sense amplifier; a pair of N-channel transistors having source-drain passages separately connecting the sensing node to the power node; and a pair of P-channel transistors having source-drain passages separately connecting the sensing node to the power node. - said plurality of sense amplifiers comprising transistors; (b) first and second sense amplifiers comprising gates and having source-drain passages connected separately in parallel between said ground node and a ground terminal of a power supply; a second N-channel transistor, the first N-channel transistor having a high resistance and having its gate connected to a first clock voltage; and the second N-channel transistor having a low resistance and having its gate connected to a second clock voltage. connected to,
(c) a third P-channel transistor having a gate and a source-drain passage connected between the positive power supply node and a positive voltage terminal of the power supply; can be,
(d) said third P-channel transistor having a high resistance and having its gate connected to a third clock voltage;
Applying the first clock voltage to the gate of the first transistor at a given time in an operating cycle, and thereafter applying the second clock voltage and the third clock voltage at a later stage of such operating cycle.
a clock device for applying a clock voltage to the gates of the second and third transistors. (42) The device according to claim 41, wherein the third clock voltage is a complement of the second clock voltage. (43) A device according to claim 41, wherein the memory cell is a one-transistor dynamic memory cell. 44. A device according to claim 41, including a pair of coupling transistors separately connecting said sensing nodes to said bit lines. 45. A device according to claim 41, wherein the gain of the third P-channel transistor is less than the gain of the second N-channel transistor.