JPH0149022B2 - - Google Patents
Info
- Publication number
- JPH0149022B2 JPH0149022B2 JP5736885A JP5736885A JPH0149022B2 JP H0149022 B2 JPH0149022 B2 JP H0149022B2 JP 5736885 A JP5736885 A JP 5736885A JP 5736885 A JP5736885 A JP 5736885A JP H0149022 B2 JPH0149022 B2 JP H0149022B2
- Authority
- JP
- Japan
- Prior art keywords
- plating
- leads
- glass
- conductive wire
- metal base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000007747 plating Methods 0.000 claims description 35
- 239000011521 glass Substances 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 16
- 238000003466 welding Methods 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 description 17
- 239000002184 metal Substances 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 15
- 238000005452 bending Methods 0.000 description 8
- 230000005611 electricity Effects 0.000 description 4
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 238000004804 winding Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4885—Wire-like parts or pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、複数のリードが半導体チツプ等の搭
載用の金属ベースにガラスなどで絶縁され、また
はスポツト溶接などにより固着されて植立されて
なるガラス端子のめつき方法に関するものであ
る。本発明は、特に、メツキ処理において、半導
体チツプ等の搭載部分に損傷やリードに曲りがな
く、金属ベースなどの半導体チツプ等の搭載面の
平坦度が確保されると共に、常にリードなどのへ
の通電が十分になされ良好なメツキ層を形成でき
るメツキ方法に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to a metal base for mounting a semiconductor chip, etc., in which a plurality of leads are insulated with glass or the like or fixed by spot welding or the like. The present invention relates to a method for plating glass terminals. In particular, the present invention ensures that during the plating process, there is no damage to the mounting part of the semiconductor chip, no bending of the leads, the flatness of the mounting surface of the semiconductor chip, such as a metal base, is ensured, and the leads, etc. are always kept flat. The present invention relates to a plating method that allows sufficient current flow to form a good plating layer.
従来、ガラス端子のメツキ処理方法としては、
複数のガラス端子のリードにそれぞれ導通線を巻
き付け、引掛治具等に引掛けて複数のガラス端子
を同時にメツキ液に浸し、メツキ層を形成する方
法と、メツキ用のバレルの中に複数のガラス端子
を入れ、そのバレルをメツキ液中で回転させ、ガ
ラス端子とバレルの電気的接続をとつてメツキ層
を形成する方法がある。
Conventionally, the plating processing method for glass terminals is as follows:
One method is to wrap conductive wires around the leads of multiple glass terminals, hook them onto a hooking jig, etc., and immerse the multiple glass terminals in plating liquid at the same time to form a plating layer. There is a method in which a terminal is inserted, the barrel is rotated in a plating solution, and an electrical connection is made between the glass terminal and the barrel to form a plating layer.
前者は、リードへの導通線の巻き付け作業及び
引掛治具への引掛け作業を要するので、作業性が
悪く、また、巻き付け不良や巻き付け状態のばら
つきが生じ、十分な通電が行われないため良好な
メツキ層が形成されず、形成されたメツキ層が不
均一になる欠点がある。 The former method requires winding the conductive wire around the lead and hooking it onto a hooking jig, so it is difficult to work with, and it also causes poor winding and variations in the winding condition, which prevents sufficient electricity from being applied. There is a drawback that a uniform plating layer is not formed and the formed plating layer becomes non-uniform.
後者は、前者と比べて、短時間で多数のガラス
端子をメツキ処理できるので作業の効率が良い
が、ガラス端子が互いにぶつかつたり、バレルに
ぶつかつたりするので、リードの曲りや半導体チ
ツプなどの搭載面が損傷するとともにメツキ層の
厚さが不均一になり易い欠点がある。したがつ
て、チツプ搭載部等において高品質を要求される
ガラス端子のメツキ処理の場合には、リード曲り
やチツプ搭載面の損傷が起こる後者の方法を用い
ず、前者の方法を用いる。 The latter is more efficient than the former because it can plate a large number of glass terminals in a short time, but the glass terminals collide with each other or against the barrel, which can cause problems such as bent leads and semiconductor chips. The disadvantage is that the mounting surface of the plate is damaged and the thickness of the plating layer tends to be uneven. Therefore, in the case of plating glass terminals that require high quality in chip mounting areas, etc., the former method is used instead of the latter method, which causes lead bending and damage to the chip mounting surface.
上述のように従来のガラス端子のメツキ処理方
法は、リードの曲りや金属ベースなどの半導体チ
ツプ搭載面が損傷し、その平坦度が劣ること、リ
ードへの通電の不良、ばらつきによりメツキが不
均一となる等の欠点があつた。
As mentioned above, the conventional method of plating glass terminals results in bending of the leads, damage to the semiconductor chip mounting surface such as the metal base, poor flatness, and uneven plating due to poor conduction of electricity to the leads and variations. There were some drawbacks such as.
本発明は、上述の欠点を除去しようとするもの
であり、メツキ処理において、半導体チツプ等の
搭載部分の損傷やリードの曲りがなく、金属ベー
スなどの半導体チツプ搭載面の平坦度が確保さ
れ、且つ常にリードへの通電が十分になされ良好
なメツキ層を効率良く形成できるメツキ方法を提
供するものである。 The present invention aims to eliminate the above-mentioned drawbacks, and in the plating process, there is no damage to the part on which the semiconductor chip is mounted, there is no bending of the leads, and the flatness of the semiconductor chip mounting surface, such as the metal base, is ensured. In addition, the present invention provides a plating method in which sufficient current is always applied to the leads and a good plating layer can be efficiently formed.
本発明によれば、上述の欠点は、複数のリード
を有するガラス端子の外部リード先端部分を溶接
により共通接続導電線に接続した後、該共通接続
導電線に通電してメツキ必要部分にメツキを施
し、その後、前記外部リード先端部分を切断して
前記ガラス端子と前記共通接続導電線とを分離す
ることを特徴とするガラス端子のメツキ方法によ
り解決される。
According to the present invention, the above-mentioned drawbacks can be solved by connecting the external lead tips of a glass terminal having a plurality of leads to a common connecting conductive wire by welding, and then applying electricity to the common connecting conductive wire to plate the parts that require plating. The problem is solved by a method for plating a glass terminal, which is characterized in that the glass terminal is separated from the common connection conductive wire by cutting the external lead end portion.
本発明では、ガラス端子のリードの所定箇所が
共通接続導電線に確実に接続され、ガラス端子が
互いにぶつかることがなく、半導体チツプ等の搭
載部の損傷やリードの曲りが生じない。また、リ
ードへの通電も十分に行え、均一な良質のメツキ
層が形成される。
In the present invention, the predetermined portions of the leads of the glass terminals are reliably connected to the common connection conductive wire, the glass terminals do not collide with each other, and the parts on which semiconductor chips or the like are mounted are not damaged and the leads are not bent. In addition, sufficient current can be applied to the leads, and a uniform, high-quality plating layer is formed.
第１図は本発明の一実施例を説明するための図
である。
FIG. 1 is a diagram for explaining one embodiment of the present invention.
第１図ａ及びｂはガラス端子が共通接続導電線
に接続された側面図及び上方から見た平面図であ
り、図で、１はリード、２は金属ベース、３は半
導体チツプ等の搭載部、４は共通接続導電線であ
る。以下、同図を用いて、本実施例のメツキ方法
を説明する。 Figures 1a and 1b are a side view and a top view of the glass terminal connected to the common connection conductive wire, in which 1 is a lead, 2 is a metal base, and 3 is a mounting part for semiconductor chips, etc. , 4 is a common connection conductive line. Hereinafter, the plating method of this embodiment will be explained using the same figure.
ガラス端子は、鉄（Fe）・ニツケル（Ni）合
金、コバール等からなる金属ベース２に同様の金
属材料からなるリード１が設けられ、また、必要
に応じて金属ベース２上面に銅等の熱放散性の良
い材料からなる半導体チツプ搭載部３が設けられ
る。（金属ベース表面を半導体チツプ搭載面とし
てもよい。）ここで、リード１を金属ベース２と
電気的に絶縁するには、一般にガラスが用いられ
る。 The glass terminal has a metal base 2 made of iron (Fe)/nickel (Ni) alloy, Kovar, etc., and a lead 1 made of the same metal material, and if necessary, a heat source such as copper or the like is provided on the top surface of the metal base 2. A semiconductor chip mounting portion 3 made of a material with good dissipation properties is provided. (The surface of the metal base may also be used as a semiconductor chip mounting surface.) Here, glass is generally used to electrically insulate the lead 1 from the metal base 2.
このガラス端子の、例えば半導体チツプ等の搭
載側の内部リードはワイヤボンデイング接続する
ためリード１の頭部にメツキ処理するが、先ず、
複数のガラス端子のリード１を平行に一列に並
べ、金属ベース２から所定の距離を有する外部リ
ード部分に鉄等からなる直線状の共通接続導電線
４を接続する。この接続は、スポツト溶接法によ
り連続的に行ない、第１図の如く、複数のガラス
端子が一つに連なつた状態となる。 The internal leads of this glass terminal on the side where a semiconductor chip or the like is mounted are plated on the head of lead 1 for wire bonding connection.
The leads 1 of a plurality of glass terminals are arranged in parallel in a row, and a straight common connection conductive wire 4 made of iron or the like is connected to an external lead portion having a predetermined distance from a metal base 2. This connection is made continuously by spot welding, and as shown in FIG. 1, a plurality of glass terminals are connected as one.
次に、第１図の如く、金属ベース２の半導体チ
ツプ等の搭載側を下にして、メツキ液（図示せ
ず）中に浸漬し、共通接続導電線４に通電して内
部リード頭部のボンデイング接続する部分にメツ
キ層を形成する。 Next, as shown in FIG. 1, the metal base 2 is immersed in plating liquid (not shown) with the side on which the semiconductor chip etc. is mounted facing down, and the common connection conductive wire 4 is energized to remove the internal lead heads. A plating layer is formed on the part to be bonded.
メツキ層を形成後、各ガラス端子の金属ベース
２と共通接続導電線４間のリード１の所定部分を
切断してそれぞれのガラス端子に分離する。 After forming the plating layer, a predetermined portion of the lead 1 between the metal base 2 of each glass terminal and the common connecting conductive wire 4 is cut to separate each glass terminal.
本方法によれば、半導体チツプ等の搭載部の損
傷やリードの曲りがなく、搭載部の平坦度が確保
され、リード曲りの修正作業が不要となる。と共
に、通電が均一、且つ良好になされ、均一で安定
したメツキ層が得られる。また、リード頭部のみ
に部分メツキを精度良く施すことができる。メツ
キ層の形成部位は、めつき液に浸漬される位置
で、半導体チツプ搭載面、金属ベース全体、ガラ
ス端子全体というように容易に選択できる。さら
に本方法によればメツキ層形成後の検査を連続的
に行うことができ、作業性の向上が図れる。必要
に応じて以後の製造工程もそのままで連続的に加
工し、適宜な工程でそれぞれのガラス端子に分離
してもよい。 According to this method, there is no damage to the mounting portion of the semiconductor chip or the like and bending of the leads, the flatness of the mounting portion is ensured, and there is no need to correct the bending of the leads. At the same time, electricity is uniformly and satisfactorily applied, and a uniform and stable plating layer can be obtained. In addition, partial plating can be performed with high accuracy only on the lead head. The plating layer can be formed at a position immersed in the plating solution, and can be easily selected from the semiconductor chip mounting surface, the entire metal base, and the entire glass terminal. Furthermore, according to this method, inspection after the plating layer is formed can be carried out continuously, and workability can be improved. If necessary, the glass terminals may be processed continuously in subsequent manufacturing steps and separated into individual glass terminals at appropriate steps.
本発明によれば、ガラス端子のメツキ処理にお
いて複数のガラス端子のリードを共通接続導電線
にスポツト溶接し、その共通接続導電線に通電し
てメツキ層を形成するので、金属ベースなどの半
導体チツプ等の搭載部の損傷やリードの曲りがな
く、搭載面の平坦度が確保され、リード曲りの修
正作業も不要となる。また、リードへの通電が均
一、且つ十分になされ均一で良好なメツキ層が安
定して効率よく形成でき、品質及び作業性が向上
する。
According to the present invention, in the plating process of glass terminals, the leads of a plurality of glass terminals are spot welded to a common connection conductive wire, and the common connection conductive wire is energized to form a plating layer, so that a semiconductor chip such as a metal base is There is no damage to the mounting part or bending of the leads, the flatness of the mounting surface is ensured, and there is no need to correct the bending of the leads. In addition, since the leads are uniformly and sufficiently energized, a uniform and good plating layer can be formed stably and efficiently, improving quality and workability.
第１図は本発明一実施例を説明するための図で
ある。図で、１はリード、２は金属ベース、３は
半導体チツプ搭載部、４は共通接続導電線であ
る。
FIG. 1 is a diagram for explaining one embodiment of the present invention. In the figure, 1 is a lead, 2 is a metal base, 3 is a semiconductor chip mounting part, and 4 is a common connection conductive line.
Claims (1)
ド先端部分を溶接により共通接続導電線に接続し
た後、該共通接続導電線に通電してメツキ必要部
分にメツキを施し、その後、前記外部リード先端
部分を切断して前記ガラス端子と前記共通接続導
電線とを分離することを特徴とするガラス端子の
メツキ方法。1. After connecting the external lead tip of a glass terminal having multiple leads to a common connection conductive wire by welding, energize the common connection conductive wire to plate the parts that require plating, and then A method for plating a glass terminal, comprising separating the glass terminal and the common connection conductive wire by cutting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5736885A JPS61216349A (en) | 1985-03-20 | 1985-03-20 | Plating method of glass terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5736885A JPS61216349A (en) | 1985-03-20 | 1985-03-20 | Plating method of glass terminal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61216349A JPS61216349A (en) | 1986-09-26 |
| JPH0149022B2 true JPH0149022B2 (en) | 1989-10-23 |
Family
ID=13053643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5736885A Granted JPS61216349A (en) | 1985-03-20 | 1985-03-20 | Plating method of glass terminal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61216349A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4854049B2 (en) * | 2009-08-31 | 2012-01-11 | エヌイーシー ショット コンポーネンツ株式会社 | Manufacturing method of electronic parts |
-
1985
- 1985-03-20 JP JP5736885A patent/JPS61216349A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61216349A (en) | 1986-09-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |