JPH0147939B2 - - Google Patents
Info
- Publication number
- JPH0147939B2 JPH0147939B2 JP54133116A JP13311679A JPH0147939B2 JP H0147939 B2 JPH0147939 B2 JP H0147939B2 JP 54133116 A JP54133116 A JP 54133116A JP 13311679 A JP13311679 A JP 13311679A JP H0147939 B2 JPH0147939 B2 JP H0147939B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- power supply
- memory transistor
- state
- supply terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000006870 function Effects 0.000 description 7
- 230000007246 mechanism Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
Landscapes
- Logic Circuits (AREA)
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
Description
【発明の詳細な説明】 本発明は集積回路装置に関する。[Detailed description of the invention] The present invention relates to integrated circuit devices.
従来、同一な、または、極めて類似なパターン
により製造され、使用目的により一部の機能切替
えが可能な集積回路装置を構成する場合、外部端
子による機能切替え装置を付加するか、パターン
の一部変更により機能変更を行つていた。かかる
手段による機能変更は、多機種、多機能の集積回
路装置を同一の、または類似したパターンで製造
できる利点を有するが、集積回路装置の外部端子
数の制限から制御端子の設定が困難である、また
はマスクパターンの一部変更を要するなどの欠点
を生じた。 Conventionally, when configuring an integrated circuit device that has been manufactured using the same or very similar pattern and allows some functions to be switched depending on the purpose of use, it is necessary to add a function switching device using external terminals or partially change the pattern. Functional changes were made. Changing functions by such means has the advantage that multi-model, multi-functional integrated circuit devices can be manufactured with the same or similar patterns, but it is difficult to set control terminals due to the limited number of external terminals of integrated circuit devices. , or the mask pattern had to be partially changed.
本発明の目的は容易な構成で機能制御のできる
集積回路装置を提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit device that can be easily configured and whose functions can be controlled.
本発明は、集積回路中に集積回路の電源により
状態を設定される記憶素子を設け、更この記憶素
子の状態で、回路の動作状態、動作箇所が変換さ
れるように構成することで、まつたく同一のマス
クパターンで製造された集積回路装置において他
に特殊な機構、または、外部に特定の端子を設け
ることなく、多機種な集積回路の製造、または、
機能選択を可能にする有効な構成を提供するもの
である。 The present invention provides a memory element whose state is set by the power supply of the integrated circuit in an integrated circuit, and furthermore, by configuring the state of the memory element to change the operating state and operating parts of the circuit, Manufacture of various types of integrated circuits without providing any other special mechanism or specific external terminals in integrated circuit devices manufactured with the same mask pattern, or
This provides an effective configuration that allows for functional selection.
本発明においては外部電源端子に印加される電
圧により状態が設定される記憶素子を設け、更
に、この記憶素子の状態で、回路の動作状態、ま
たは、動作箇所、またはそのいずれもが変換され
る集積回路装置によつて、外部に特定の端子、機
構を設けることなくまつたく同一なマスクパター
ンで製造された集積回路装置を、異機種に変換ま
たは、機能選択をする上で著じるしい効果があ
る。 In the present invention, a memory element whose state is set by a voltage applied to an external power supply terminal is provided, and further, the operating state of the circuit and/or the operating location is changed depending on the state of this memory element. A remarkable effect in converting integrated circuit devices manufactured with exactly the same mask pattern without providing specific external terminals or mechanisms into different models or selecting functions. There is.
次に本発明の実施例を第１図を参照して説明す
る。 Next, an embodiment of the present invention will be described with reference to FIG.
第１図を参照すると本発明の一実施例は本発明
がＮチヤンネルMOS集積回路に適用された場合
で内部に包含される記憶素子として、フローテイ
ングゲート構造をもつ電気的書込可能なメモリト
ランジスタを応用した例であり、フローテイング
ゲート構造の電気的書込可能なメモリトランジス
タ１、その負荷トランジスタ２、電源端子３、制
御信号４、被制御回路５を含む。かかる構成によ
れば初期状態では、メモリトランジスタ１の閾値
は通常動作時電源端子３に印加される電圧より低
いためトランジスタはオンし、制御信号４は
“０”が出力されている。ここで一旦、電圧端子
３にメモリトランジスタ１の書込電圧以上の電圧
であつて被制御回路５内の各素子を破壊させない
電圧が印加されるとフローテイングゲートに電荷
が蓄積され、その結果、メモリトランジスタ１の
閾値は高くなる。したがつて、電源端子３に通常
動作時の電源電圧が印加されてもメモリトランジ
スタ１はオフ状態となつており、制御信号４には
“１”が出力される。この制御信号４により回路
５の動作状態、または、箇所が変換されるよう構
成することで他に特殊な機構、または特定の外部
端子を設けることなく機能変更、または、機種変
更を可能にする。 Referring to FIG. 1, one embodiment of the present invention is an electrically writable memory transistor having a floating gate structure as a storage element included therein when the present invention is applied to an N-channel MOS integrated circuit. This is an example in which the circuit is applied, and includes an electrically writable memory transistor 1 having a floating gate structure, its load transistor 2, a power supply terminal 3, a control signal 4, and a controlled circuit 5. According to this configuration, in the initial state, the threshold value of the memory transistor 1 is lower than the voltage applied to the power supply terminal 3 during normal operation, so the transistor is turned on and the control signal 4 is outputted as "0". Once a voltage that is higher than the write voltage of the memory transistor 1 and does not destroy each element in the controlled circuit 5 is applied to the voltage terminal 3, charge is accumulated in the floating gate, and as a result, The threshold value of memory transistor 1 becomes higher. Therefore, even if the power supply voltage during normal operation is applied to the power supply terminal 3, the memory transistor 1 is in the off state, and the control signal 4 is outputted as "1". By configuring the control signal 4 to change the operating state or location of the circuit 5, it is possible to change the function or model without providing any other special mechanism or specific external terminal.
以上説明したように、集積回路の外部電源端子
に印加される電圧により状態が設定される記憶素
子を設け、更に、この記憶素子の状態により回路
の動作状態または、動作箇所が変換されるよう構
成することで外部に特定の端子を設けることな
く、同一マスクパターンで製造された集積回路装
置の機種変更、または、機能選択が可能な集積回
路を提供するものである。 As explained above, a memory element whose state is set by the voltage applied to the external power supply terminal of the integrated circuit is provided, and the circuit is configured such that the operating state or operating location is changed depending on the state of the memory element. By doing so, it is possible to provide an integrated circuit in which models of integrated circuit devices manufactured using the same mask pattern can be changed or functions can be selected without providing specific external terminals.
第１図は本発明に適用される例としてＮチヤン
ネルMOS集積回路中に電気的書込可能な記憶素
子を応用した回路構成図である。
１…フローテイングゲート構造を有す電気的書
込可能なメモリトランジスタ、２…負荷トランジ
スタ、３…電源端子、４…制御信号、５…被制御
回路。
FIG. 1 is a circuit configuration diagram in which an electrically writable memory element is applied to an N-channel MOS integrated circuit as an example to which the present invention is applied. DESCRIPTION OF SYMBOLS 1... Electrically writable memory transistor having a floating gate structure, 2... Load transistor, 3... Power supply terminal, 4... Control signal, 5... Controlled circuit.
Claims (1)
グゲート構造を有するメモリトランジスタとを第
１と第２の電源端子の間に直列に接続し、該メモ
リトランジスタのゲートを該第１の電源端子に接
続し、該負荷素子とメモリトランジスタの中間接
続点の電位によつて内部回路の状態が該第１電源
端子への電源の投入とともに設定されることを特
徴とする集積回路装置。1. A load element and a memory transistor having a floating gate structure capable of electrical writing are connected in series between first and second power supply terminals, and the gate of the memory transistor is connected to the first power supply terminal. an integrated circuit device, wherein the state of an internal circuit is set by the potential of an intermediate connection point between the load element and the memory transistor when power is applied to the first power supply terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13311679A JPS5657334A (en) | 1979-10-16 | 1979-10-16 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13311679A JPS5657334A (en) | 1979-10-16 | 1979-10-16 | Integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5657334A JPS5657334A (en) | 1981-05-19 |
| JPH0147939B2 true JPH0147939B2 (en) | 1989-10-17 |
Family
ID=15097163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13311679A Granted JPS5657334A (en) | 1979-10-16 | 1979-10-16 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5657334A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58137327A (en) * | 1982-02-10 | 1983-08-15 | Toshiba Corp | Semiconductor integrated circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4918437A (en) * | 1972-06-09 | 1974-02-18 |
-
1979
- 1979-10-16 JP JP13311679A patent/JPS5657334A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4918437A (en) * | 1972-06-09 | 1974-02-18 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5657334A (en) | 1981-05-19 |
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