JPH0147902B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated semiconductor device.

Below, an insulated gate field effect transistor (hereinafter referred to as
The prior art and the present invention will be specifically explained using an inverter circuit using MOS transistors as an example, but this is for convenience of explanation and does not limit the present invention.

Now, an inverter circuit using MOS transistors has a configuration in which a load MOS transistor and a drive MOS transistor integrated on a substrate are connected. An example of such a MOS inverter device is, for example, the IEEE JOURNAL OF SOLID-
STATE CIRCUITS) SC-13, No. 600~
64K x 1 bit published on page 606 (1978)
Dynamic ED-MOS RAM (“A64K×1Bit
Toshio titled “Dynamic ED-MOS RAM”)
This is also described in papers by Dr. Wada et al., and it was common for the source of the load MOS transistor formed on the active region of the substrate to be made common to the drain of the drive MOS transistor. .

However, as integrated semiconductor devices have increased in capacity and performance, higher density has been required. For this reason, even in the conventional inverter circuit as described above, attempts have been made to increase the integration of the load MOS transistors in a vertical manner. One example is the 1980 IEEE INTERNATIONAL SOLID Conference held in February 1980.
−STATE CIRCUITS CONFERENCE) Digest of Technical Papers (ISSCC DIGEST OF TECHNICAL
PAPERS), pages 56-57 (distributed simultaneously at the February 1980 conference), entitled “MOS Buried Load Logic”.
A paper by Yoshio Sakai et al. A sectional view of this inverter device is shown in FIG. In FIG. 1, 1 is an n-type substrate, 2 is an insulating field oxide film, 3 is a p-type well, 4 and 5 are n-type impurity regions, 6 is a gate oxide film, and 7 is a gate electrode. In this device, for the drive
The MOS transistor is a conventional type consisting of a gate electrode 7, an n-type region 5 that functions as a drain electrode, and an n-type region 4 that functions as a source electrode.
Although it is a MOS transistor, it is a load MOS transistor.
The transistor is a junction field effect transistor (J-FET) consisting of a p-type well 3 that functions as a gate electrode, an n-type substrate 1 that functions as a drain electrode, and an n-type region 5 that functions as a source electrode. . As a result, compared to conventional inverter devices, the area of the load transistors on the substrate has been saved and the degree of integration has been significantly improved.

The attempt by Yoshio Sakai et al. was excellent in this respect, but it was difficult to control the load current of the vertical J-FET, which is determined by the opening area of the p-type well 3, to a predetermined value. Control accuracy must be imposed on the entire manufacturing process, such as impurity diffusion into the well and push-in time, etc., and furthermore, since a J-FET is used as a load transistor, the inverter characteristics inevitably deteriorate.
This gave rise to new problems such as:

The present invention takes advantage of the advantages brought about by the efforts of Mr. Yoshio Sakai and others while eliminating the drawbacks, achieves sufficient integration and density, and enables large-capacity integration not only for inverter circuits but also for a wide range of applications. The present invention provides an integrated semiconductor device that can be applied to logic circuits, memory circuits, and the like. Its structural features are
A semiconductor substrate of a first conductivity type, a well of a second conductivity type provided in a surface layer of the substrate, and a film formed on the surface of the substrate so as to surround the well and gradually increase in thickness toward the periphery. an isolation insulator film provided in the well, first and second semiconductor regions of a first conductivity type provided at intervals on a surface layer portion of the substrate within the well; a thin insulating film provided so as to be in contact with or overlap with the semiconductor region; and a first electrode provided on the thin insulating film, one end of which is connected to the first semiconductor region or the second semiconductor region.
and a second electrode provided so as to be in contact with one surface of the semiconductor region and with the other end extending from the well to the isolation insulator film, the well being located below the second electrode. A conductive channel is formed in a boundary region between the semiconductor device and the isolation insulator film.

In the integrated semiconductor device of the present invention, for example,
If n-type is selected as the first conductivity type and p-type is selected as the second conductivity type, an inverter circuit using n-channel MOS transistors can be realized. In other words, the drive MOS transistor is composed of a first electrode serving as a gate electrode, first and second semiconductor regions serving as source and drain electrodes, and a load MOS transistor.
The MOS transistor includes a second electrode that serves as a gate electrode, the second semiconductor region that serves as a source electrode, and a semiconductor substrate that serves as a drain electrode. Moreover, since the load MOS transistor uses the tapered region of the active isolation oxide film, the area occupied on the substrate surface of this inverter device is limited to the drive area.
Determined only by MOS transistors, conventional MOS
The area is about half that of an inverter device using transistors. Namely, the said Yoshio Sakai
All the advantages of their attempt could be completely reproduced. Furthermore, in the case of the structure of the present invention, the p-type well can be created by impurity diffusion or ion implantation, so it can not only be realized using the same process steps as conventional methods, but also can be used as a load MOS transistor. Since the MOS transistors of the pletion type are used, there is an advantage that an E-D type inverter device with a wide operating margin can be created.
New and outstanding effects that could not be achieved with the attempts of Yoshio Sakai and others can be easily achieved.

EMBODIMENT OF THE INVENTION Hereinafter, one embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 2 is a perspective sectional view of one embodiment of the integrated semiconductor device of the present invention. In the figure, 1 is an n-type semiconductor substrate, 2 is a field oxide film which is an isolation insulator film, 30 is a p-type well modified according to the present invention,
4 is the n-type region which is the first semiconductor region, and 5 is the second semiconductor region.
6 is a gate oxide film, 7 is a polycrystalline silicon film which is a first electrode, 8 is an n-type region which is a semiconductor region of
9 indicates a polycrystalline silicon film which is a second electrode, and 9 indicates a conductive channel formed between the p-type well and the isolation insulator film. The equivalent circuit of FIG. 2 is shown in FIG. In this embodiment shown in FIGS. 2 and 3, the load depletion transistor T2
and drive enhancement transistor T
1, the drive transistor T1 is composed of a polycrystalline silicon film 7 serving as a gate electrode, an n-type region 4 serving as a source electrode, and an n-type region 5 serving as a drain electrode. T2 includes a polycrystalline silicon film 8 which becomes a gate electrode, an n-type region 5 which becomes a source electrode,
It is composed of an n-type substrate 1 which becomes a drain electrode. To operate as an inverter circuit, connect the n-type substrate 1 to the power line V _DD and the n-type region 4 to the ground line GND.
, the polycrystalline silicon film 7 is used as the input terminal IN, and the n-type region 5 or the polycrystalline silicon film 8 is used as the output terminal.
Just connect each to OUT. By doing this, the MOS transistor T1 operates as a normal n-channel MOS enhancement type MOS transistor, while the gate electrode and source electrode of the MOS transistor T2 are connected, so that
It operates as a depletion type n-channel MOS transistor. The channel of the MOS transistor T2 is formed in the boundary region 9 of the p-well 3 directly under the tapered portion of the field oxide film 2. In order to make the threshold voltage of this transistor T2 negative, the n-type region 5 may be formed deeper than the n-type region 4, or an n-type impurity may be implanted into the boundary region 9 that will become a channel. Good too. When a positive high voltage is input to the input terminal IN, the MOS transistor T1 becomes conductive, and the voltage at the output terminal OUT becomes approximately equal to the ground level. Conversely, when the voltage at the input terminal IN is set to the ground level, the MOS transistor T1 becomes non-conductive, so a current is supplied from the substrate 1 to the output terminal OUT through the load transistor T2, and the output voltage becomes the power supply voltage _VDD .

As is clear from the above explanation, when an inverter circuit is constructed using the integrated semiconductor device of the present invention, the load
Since it will constitute a MOS transistor,
The area occupied by the inverter circuit board surface is approximately
The area is equivalent to one MOS transistor, which is much smaller than the N-channel MOS transistor that has been put into practical use. Also, the aforementioned Yoshio
Vertical J- constructed by Mr. Sakai et al.
Compared to an inverter device using FETs, the area is equivalent, but since the integrated semiconductor device of the present invention uses depletion type load transistors, it is possible to create a circuit with excellent inverter characteristics. Gain new advantages.

Next, an example of a manufacturing method for obtaining the structure of the present invention will be briefly explained using FIG. 4. First, an oxide film SiO ₂ (not shown) and a nitride film are formed on the n-type substrate 1.
After growing Si ₃ N ₄ (not shown), a photoresist (not shown) is applied thereon, and the nitride film other than the active area is removed by photolithography. do. Next, a field oxide film 2 is formed by wet oxidation for several hours. Thereafter, the nitride film and oxide film remaining in the active region are removed to form the structure shown in FIG. 4a. Next, an impurity is selectively added by a method such as boron thermal diffusion, ion implantation, and forced oxidation to form a p-type well 30 having the characteristics of the present invention. Then, an oxide film (not shown) to be used as a gate oxide film with a thickness of about 100 Å is formed. Furthermore, after forming a polycrystalline silicon film (not shown) to be used as a first layer wiring, for example, a gate wiring in this case, a mask oxide film (not shown) is grown. Next, the remaining portions are etched away by a so-called photolithography method so that, for example, the polycrystalline silicon film 7 and oxide film 6 constituting the first gate electrode portion remain. This state is the structure shown in FIG. 4b.

Next, source/drain regions 4 and 5 of transistor T1 are formed by ion implantation of phosphorus or arsenic. This state is the structure shown in FIG. 4c. Next, the entire surface is thermally oxidized to form a thick oxide film on the first layer polycrystalline silicon film. Thereafter, the oxide film on the drain region is removed by photolithography, and then a second layer of polycrystalline silicon film is formed. Thereafter, a CVD oxide film is grown on the polycrystalline silicon film, and the oxide film and polycrystalline silicon film other than the second gate electrode portion 8 are removed by photolithography. This state is the structure shown in FIG. 4d. Thereafter, a PSG oxide film (not shown) is grown over the entire surface, contact areas are etched, and then aluminum wiring (not shown) is formed. If it is desired to make the threshold voltage of the MOS transistor T2 negative, it is also effective to ion-implant an n-type impurity, such as arsenic, into the boundary region 9 to form the conductive channel region 50. A sectional view of the present invention in this case is shown in FIG. This ion implantation step is performed before the formation of the field oxide film 2 in FIG. 4a.
The process may be carried out in the region that will become the channel of the MOS transistor T2, or by performing ion implantation at a high ion implantation acceleration voltage after forming the source and drain regions of the transistor T1 as shown in FIG. 4c. Alternatively, as another manufacturing method, when forming the source/drain regions 4 and 5 shown in FIG.
This can also be achieved by pushing the n-type impurity deeper than the above. A sectional view of the present invention in this case is shown in FIG. In this case, arsenic is added to the source region 4,
The process can be performed by ion-implanting phosphorus atoms into the drain region 5 to form a shallow n-type source layer 4 and a deep n-type drain layer 500.

As can be seen from the above explanation, the manufacturing process required to realize the integrated semiconductor device of the present invention is as follows:
One of the important advantages of the present invention is that the manufacturing method is simple, as it is substantially the same as the conventional two-layer polycrystalline silicon process.

As described above, the integrated semiconductor device of the present invention can be implemented immediately by making full use of conventional processes that are well established as manufacturing technology, and can realize an inverter circuit that is highly integrated and dense, and has a wide operating margin. Although it is clear that it is extremely useful in practice, the present invention is not limited to one inverter circuit, but is used to connect two or more load MOS transistors in series to one load MOS transistor. If you connect the tangled drive MOS transistors,
For drives with two or more connected in parallel to a NAND circuit or one load MOS transistor
If you connect a MOS transistor, it becomes a NOR circuit, 2
If these inverter circuits are cross-coupled, it can be widely applied to flip-flop circuits, logic circuits, memory circuits, etc., and its industrial effects are truly great.

In the present invention, for convenience of explanation, an n-channel MOS transistor is assumed, but
Naturally, it can also be applied to a p-channel MOS transistor, in which case the first conductivity type is p-type and the second conductivity type is n-type.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view for explaining an inverter device using a conventional vertical J-FET as a load transistor, and FIG. 2 is a cross-sectional view showing an inverter device similar to that shown in FIG. FIG. 3 is an equivalent circuit diagram of the embodiment of FIG. 2, and FIG.
Figures a, b, c, and d show an example of the manufacturing method required to realize this embodiment. In the figure, 1 is a semiconductor substrate of the first conductivity type, 2 is a field oxide film, 3 is a well of the second conductivity type, 4, 5
are first and second semiconductor regions of the first conductivity type, 6 is a gate oxide film, 7 and 8 are first and second electrodes, 9
is the conductive channel forming area, V _DD is the power line, GND is the ground line, IN is the input terminal, OUT is the output terminal, T is the
Each MOS transistor is shown. The major difference in structure between the conventional example shown in FIG. 1 and the embodiment of the present invention shown in FIGS. 2 to 6 is that the second conductivity type wells are separated into three
30, and a controlled conductive channel forming region 9 is newly provided. The first modification of conductive channel formation area control is
FIG. 5 shows a structure in which a conductive type impurity doped region 50 is provided, and a first conductive type second semiconductor region 5 is provided with a conductive type impurity doped region 50.
FIG. 6 shows an example of a configuration in which the holes are formed deeply as shown in FIG.

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type, a well of a second conductivity type provided in a surface layer of the substrate, and a film thickness of the semiconductor substrate gradually increasing toward the periphery so as to surround the well in the surface layer of the substrate. first and second semiconductor regions of a first conductivity type provided at intervals on the surface layer of the substrate within the well; a thin insulating film provided in contact with or overlapping the second semiconductor region; and a first insulating film provided on the thin insulating film.
and a second electrode provided such that one end is in contact with the surface of either the first semiconductor region or the second semiconductor region and the other end extends from the well onto the isolation insulator film. An integrated semiconductor device comprising: a conductive channel formed in a boundary region between the well located under the second electrode and the isolation insulator film.