JPH0146035B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an imaging device tester for testing a solid-state imaging device called an image sensor or the like or a television camera incorporating this solid-state imaging device, and in particular, the first invention of this application relates to It is an object of the present invention to provide a test device having means capable of performing arithmetic processing at high speed in order to eliminate the influence of

Further, the second invention of this application attempts to provide an imaging device tester that allows the number of photoelectric conversion cells of a solid-state imaging device to be tested to be freely selected regardless of the memory capacity of the tester.

<Background of the Invention> Solid-state image sensors have been developed and are being put into practical use for the purpose of downsizing and reducing power consumption of television cameras. As is well known, in a solid-state image sensor, a large number of photoelectric conversion cells made of semiconductor are arranged on one side, and the photoelectric conversion cells are sequentially selected one by one according to a selection signal and irradiated onto the photoelectric conversion cells. A pixel signal corresponding to the amount of light is obtained, and the selection of the photoelectric conversion cells is sequentially switched to perform image scanning to obtain an image signal.

Since each photoelectric conversion cell is formed on a semiconductor substrate by integrated circuit manufacturing technology, it is conceivable that defects may occur in the photoelectric conversion cells during the manufacturing process. Therefore, it is necessary to test whether each photoelectric conversion cell operates normally.

Various test items have been considered for testing solid-state image sensors, one of which is to irradiate the solid-state image sensor with uniform light and measure the photoelectric conversion of each photoelectric conversion cell while receiving the uniform light. Take the converted value and compare it with a predetermined expected value,
A cell that outputs a photoelectric conversion value that is significantly different from the expected value is determined to be defective, and the quality of the solid-state image sensor is determined based on where the defective cell is located on the light-receiving surface and how many there are. There are ways to determine whether it is defective.

<General description of the solid-state image sensor tester> FIG. 1 shows the overall configuration of the solid-state image sensor tester. In the figure, 101 indicates a solid-state image sensor to be tested. This solid-state image sensor 101 is of CCD formation or MOS type,
Furthermore, any CPD format that combines these features is acceptable. These formats can be considered to have the same optical characteristics, except for the format structure of the photoelectric conversion cell and the method of transferring charges from the photoelectric conversion cell.

Reference numeral 102 denotes a drive circuit that provides a cell selection signal to the solid-state image sensor 101. It is assumed that the drive circuit 102 selects and scans each of the CCD, MOS, and CPD type solid-state image sensors according to the arrangement of their respective photoelectric conversion cells, and sequentially obtains pixel signals. This scanning speed can be set equal to the standard scanning speed for television signals.

Pixel signal 10 obtained from solid-state image sensor 101
3 is amplified by a preamplifier 104 and provided to an AD converter 105. The AD converter 105 receives clock pulses 100 from the drive circuit 102.
The pixel signal is AD-converted in synchronization with, for example, an 8-bit digital pixel signal.

The pixel signal AD-converted by the AD converter 105 is taken into the data memory 106. The data memory 106 counts the clock pulses applied from the drive circuit 102 with an address counter 107, and the address is sequentially incremented by one address based on the count output, and the digital pixel signals output from the AD converter 105 are sequentially stored.

The digital pixel signals taken into data memory 106 are sequentially transferred to data processor 108. This data processor 108 has various comparison and determination means, and uses this determination means to determine the quality of the photoelectric conversion cell and the quality of the solid-state image sensor 101 as a whole.

109 is a controller. This controller 109 starts and stops the drive circuit 102 and controls the data processor 108. Further, a control signal is given to the optical control system 111 to perform control such as gradually changing the light amount of the light source 112 as the test progresses.

Reference numeral 113 denotes a monitor, which performs DA conversion on the digital pixel signals taken into the data memory 106 and projects an image on the screen based on the pixel signals obtained from each photoelectric conversion cell.

<Problems in Executing Tests> Solid-state imaging devices are tested using the configuration roughly shown in FIG. 1, but the following problems exist in executing the tests.

Since the photoelectric conversion output output from the image sensor 101 is a minute-level analog signal, it has a poor signal-to-noise ratio and is easily contaminated with noise.

There is a phenomenon in which a difference occurs in the dark current of each photoelectric conversion cell, or unevenness in the amount of light occurs due to distortion of an optical lens, etc., and as a result, a photoelectric conversion value outputs a different value for each photoelectric conversion cell. This phenomenon is called shading.

Figures 2A, B, and C show examples of the effects of shedding. The horizontal axis in the figure is the scanning position of the photoelectric conversion cell.
The vertical axis indicates the photoelectric conversion output value. As shown in this example, there is a phenomenon in which the photoelectric conversion output differs depending on the position of the photoelectric conversion cell due to dark current or uneven light intensity. If the test is performed without removing the influence of this shedding, even if the photoelectric conversion characteristics, that is, the sensitivity characteristics, etc. of each photoelectric conversion cell are the same, it will be determined to be a defective product. When assembled and used as a camera, the circuit is designed to eliminate the effects of these shadings, so if the sensitivity characteristics etc. are normal, it should be judged as a good product.

In order to solve the above-mentioned problems, the influence of noise can be removed by extracting the photoelectric conversion output from each photoelectric conversion cell multiple times and averaging the multiple photoelectric conversion outputs. Therefore, it is assumed that the pixel data taken into the data memory 106 shown in FIG. 1 is the average value of a plurality of times. The average value can be obtained by adding the digital pixel data each time and taking in the carry-over high-order bit signal.

On the other hand, to remove the effect of shedding,
The offset components (the average value of each photoelectric conversion cell when a certain amount of light is applied) due to shading as shown in Fig. 2 A, B, and C are loaded into the memory in advance, and the offset components loaded into this memory are used to This can be achieved by sequentially subtracting from the measurement data that has the average value when changing to the light intensity.

For this reason, the data memory 106 shown in FIG. 1 has a memory having a capacity to store one screen of the solid-state image sensor 101 as one memory block, and the memory blocks are designated as M ₁ to M ₁₆ in FIG. 3. A plurality of memory blocks M ₁ ~
Offset component B is stored in one of _M16 . Third
The example shown in the figure shows the case where offset component B is stored in _M11 .

The photoelectric conversion value A obtained when the light intensity is changed and the conditions are changed is stored in the memory block _M3 . The offset component B is subtracted from this photoelectric conversion value A, and the result of this subtraction is compared with the expected value in the data processor 108.

In this way, the influence of shading is removed, but the data processor 10 performs calculations to obtain data from which offset component B has been removed.
It is conceivable that this could be done by a computer installed at 8. FIG. 4 shows a program for performing calculations using a computer. In step, the data of the corresponding photoelectric conversion cells is taken out from memory blocks _M3 and _M11 . In step, data B taken out from memory block _M11 is subtracted from data A taken out from memory block _M3 to obtain A-B=C. This calculation result C is stored in the memory provided in the data processor 108 in a step. The operations in steps ~ are executed for each photoelectric conversion cell, and the data memory 108
The data from which the offset component B has been removed is obtained in the memory provided in the memory.

As described above, the arithmetic processing by the computer involves reading out data alternately from the memory blocks _M3 and _M11 for each photoelectric conversion cell and performing the arithmetic processing, which has the disadvantage of being time consuming. This increases the time required to test one solid-state image sensor.
This method has the disadvantage that a large number of expensive testers must be prepared in order to test a large number of devices.

<Objective of the first invention> The first invention of this application is to provide a solid-state image sensor tester that can perform arithmetic processing for removing offsets in a short time, and can therefore test many solid-state image sensors in a short time. That is.

<Summary of the first invention> In the first invention of this question, a plurality of memory blocks are configured so that they can be read out simultaneously in parallel, and in this way, the memory blocks storing data A and B are read out simultaneously, The readout output is applied to the subtracter, the subtraction result is immediately obtained from the subtracter, and the subtraction result is transferred to the data processor 108.

Therefore, according to the first invention of this application, data A
The subtraction result can be obtained at the same time as reading the memory block containing B and B, and the subtraction result C can be obtained in a short time. Therefore, there is an advantage that the time required for the test can be reduced accordingly.

<Embodiment of the first invention> FIG. 5 shows an embodiment of the first invention of this application. In FIG. 5, M ₁ , M ₂ , M _{3 .} . . M ₁₆ are the memory blocks described in FIG. 3. Since each memory block _M1 to _M16 has the same structure, only memory block _M1 will be described in detail here. That is, each memory block _M1 to _M16 is provided with block selectors 501 and 502. By outputting a select signal from these memory selectors 501 or 502, the memory main body 503 is selected and a read operation or a write operation is performed.

At the same time, one of the gates 504 and 505 is controlled to be open by the select signal of the block selectors 501 and 502, and the readout output of the memory main body 503 is transmitted to the input terminals 506a and 506 of the subtracter 506.
b.

Block selectors 501 and 502 are selected by block select signals output from block select signal generators 507 and 508 constituting means for simultaneously reading a plurality of memory blocks. Block select signal generator 507 selects a memory block storing offset data from among 16 memory blocks _M1 to _M16 using, for example, a 4-bit address signal. It is also assumed that the block select signal generator 508 selects a memory block storing measurement data.

For example, if the block select signal generator 507 outputs "0, 0, 1, 1" as an address signal, memory block _M3 is selected and the memory body 503 of memory block _M3 performs a read operation. Memory block _M3 is block selector 50
1, gate 504 of memory block _M3 is controlled to be open. Therefore, the offset data read from the memory body 503 of the memory block _M3 is supplied to the input terminal 506a of the subtracter 506 through the gate 504.

On the other hand, when the block select signal generator 508 outputs, for example, "0, 0, 0, 1", the block selector 502 of the memory block _M1 is selected. By selecting this block selector 502, the memory main body 50 of memory block _M1 is
3 is in the read operation state, and the gate 505 is controlled to be open. Therefore, the measurement data read from the memory main body 503 of the memory block _M1 is sent to the gate 50.
5 to the input terminal 506b of the subtracter 506.

Reference numeral 509 denotes an address signal generator that provides an address signal to the memory main body 503 provided in each memory block _M1 to _M16 . The address signal output from this address signal generator 509 is transmitted to all memory bodies 5 provided in each memory block _M1 to _M16 .
However, only the memory body 503 of the memory block selected by the block select signal generators 507 and 508 is read out by this address signal.

When writing, the block select signal generator 507
or 508, and stores the digital pixel data from the AD converter 105 in the memory body 503 of the selected memory block. On this memory
For example, if the number of bits of the AD converter 105 is 8 bits, the number of storage bits of the memory body 503 is 16 bits, and the AD conversion values output from the AD converter 105 are integrated for 128 times, the number of bits of the memory body 305 is The average pixel data for 128 times can be obtained from the upper 8 bits.

<Operations and Effects of the Invention> As described above, according to the present invention, two memory blocks are selected by the block select signal generators 507 and 508, and measurement data A and an offset are obtained from the two selected memory blocks. Data B is read out at the same time, and the readout output is subtracted by the subtracter 5.
Since the subtraction is performed in step 06, the subtraction result can be obtained at the same time as reading. Therefore, by transmitting this subtraction result to the data processor 108 described in FIG. 1, the data processor 108 can compare the photoelectric conversion data from which the influence of shedding has been removed with the expected value, allowing the test to be completed in a short time. can be done.

<Description of the second invention> In the first invention described above, each memory block M ₁ to
Solid-state image sensor 1 is installed in the memory main body 503 provided in _M16 .
The explanation has been made assuming that data of each photoelectric conversion cell of 01 is stored. However, the standard solid-state image sensing device 101 has, for example, a cell count of 512×512, but other types are also possible. Therefore, if the number of photoelectric conversion cells exceeds the capacity of the memory main body 503 provided in the memory blocks _M1 to _M16 , testing becomes impossible.

The second invention of this application is to provide an imaging device tester having a structure that allows testing even when the number of photoelectric conversion cells of the solid-state imaging device 101 is larger than the capacity of the memory main body 503.

<Embodiment of the second invention> FIG. 6 shows an embodiment of the second invention of this application.
The second invention of this application is provided with means for successively reading out adjacent memory blocks as required.

For this purpose, for example, adders 601 and 60 are connected to the output sides of block select signal generators 507 and 508.
2, supplying the carry output of the address generator 509 to the adders 601 and 602, and adding the carry output of the address generator 509 to the block select signal. With this configuration, the address generator 5
When 09 generates a carry output, adders 601 and 6
The output value of 02 is increased by +1. As a result, a memory block adjacent to the previously selected memory block is selected, and this memory block is accessed for writing or reading. This adder 6
The added value of 01 and 602 is reset by control commands 603 and 604 from the data processor 108 when the address signal of the address generator 509 reaches a predetermined address of an adjacent memory block, and is returned to the starting address of the original memory block. . Therefore, for example, it is possible to repeatedly store image signals for a plurality of screens while integrating them. Furthermore, when reading after writing, reading can be performed from the initial position.

<Operations and Effects of the Second Invention> According to the second invention shown in FIG. 6, adjacent memory blocks can be successively accessed as necessary. For this reason, for example, the solid-state image sensor 10
The number of photoelectric conversion cells of 1 is the memory block M ₁ ~
Even if the memory capacity becomes larger than _M16 , adjacent memory blocks can be accessed as necessary. Therefore, it is possible to freely test solid-state imaging devices of various sizes and to freely test highly versatile solid-state imaging devices, thereby providing a highly versatile solid-state imaging device tester.

In the above description, a solid-state image sensor is used as the object to be tested, but a camera using a solid-state image sensor can also be used as the object to be tested. When a camera is used as the test target, the optical system including the solid-state image sensor and the processing circuit for the signal output from the solid-state image sensor can also be tested, making it possible to conduct a comprehensive test.

[Brief explanation of drawings]

Figure 1 is a block diagram for explaining the overall solid-state image sensor, Figure 2 is a graph for explaining the influence of shedding that occurs in the solid-state image sensor, and Figure 3 is a graph for explaining the influence of shedding that occurs in the solid-state image sensor.
The figure is a diagram for explaining the configuration of the data memory explained in Figure 1, Figure 4 is a flowchart for explaining the program required for calculation to remove the influence of conventional shading, and Figure 5 is FIG. 6 is a block diagram showing an embodiment of the first invention of this application, and FIG. 6 is a block diagram showing an embodiment of the second invention of this application. 101: Solid-state image sensor, 106: Data memory, _M1 to _M16 : Memory block, 507, 50
8,509: Means for simultaneously reading out photoelectric conversion values taken into different memory blocks, 506: Arithmetic unit for processing data read from memory blocks, 601, 602: Means for successively accessing adjacent memory blocks. .

Claims (1)

[Scope of Claims] 1. A. An AD converter that sequentially performs AD conversion on an imaging signal output from an imaging device to be tested; B. A block selector and a memory main body.
When the block selector is selected by the block select signal, the AD converter is
A plurality of memory blocks capable of storing the AD conversion output in the memory body and storing the average value of the imaging signals for multiple screens output from the imaging device; A reading means for simultaneously reading out the average value of photoelectric conversion values for multiple screens having different captured light reception conditions in parallel; D a subtracter for subtracting this read output; E the subtracted output value of this subtracter is specified. an imaging device tester comprising: a determining means for determining whether or not the imaging device is within the range of 1 to determine whether the imaging device is good or bad; 2. A. An AD converter that sequentially performs AD conversion on the imaging signals output from the imaging device to be tested; B. A block selector and a memory main body.
When the block selector is selected by the block select signal, the AD converter is
A plurality of memory blocks capable of storing the AD conversion output in the memory body and storing the average value of the imaging signals for multiple screens output from the imaging device; A readout means for simultaneously reading out the average value of the photoelectric conversion values acquired under different light reception conditions in parallel; D. A subtracter for subtracting this readout output; E A carry signal is generated in the address signal of the above memory block. means for incrementing the value of the block select signal to select the block selector of an adjacent memory block and accessing that memory block; An imaging device tester comprising: a determining means for determining whether the imaging device is good or bad;