JP2003198958A - Cmos image sensor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable verification of the operation state of each pixel in a pixel array part and to simplify a device test to shorten the test time. <P>SOLUTION: A test logic part 14 is provided, which converts an electric signal which is an analog signal generated by a pixel array part 12 provided with a plurality of pixels for photoelectric conversion, to a digital signal by an A/D converter 13 and uses the A/D converted digital signal to verify whether the operation state of each pixel in the pixel array part 12 is normal or not. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

The present invention relates to a CMOS (Com)
Plenary Metal OxideSemi
and an image sensor formed by a transistor.
In particular, it relates to a CMOS image sensor having a self-diagnosis function capable of determining whether or not a component is operating normally.

[0002]

2. Description of the Related Art Generally, an image display device is a charge coupled device (hereinafter, referred to as C).
An image sensor formed by a CD) is used. However, such an image display device requires the application of a relatively high power supply voltage (about 12 V) during operation, and also requires a large number of steps when manufacturing a CCD.

Further, the image sensor formed by the CCD has an A for converting an analog signal into a digital signal.
A logic circuit such as a -D conversion circuit is required separately. Therefore, in the image sensor formed by the CCD, in the manufacturing process, the step of forming the sensor portion and the step of forming the logic circuit portion are different from each other, and the sensor portion and the logic circuit portion may not be formed in one chip. There is.

With respect to such a problem, Japanese Patent Laid-Open No. 11-3
Japanese Patent No. 31883 discloses a structure of a CMOS image sensor which can be driven at low power, and by forming all circuits necessary for image sensing in one chip to increase the degree of integration and speed up the processing speed of image data. Is disclosed. Further, this CMOS image sensor has a built-in diagnostic logic circuit capable of verifying the operating states of the components such as control and external system interface and analog-digital converter.

FIG. 6 is a block diagram showing the configuration of the CMOS image sensor disclosed in this publication. The CMOS image sensor shown in FIG. 6 is provided with a pixel array section 52 for arranging a plurality of pixels (pixels) for converting an optical signal by light into an electric signal and detecting information for an image (light) incident from the outside. There is. The analog voltage, which is an electric signal generated by the pixel array section 52, is output to the analog-digital converter 53, and the analog-digital converter 53 enables the analog voltage to be processed by a digital system. Analog-to-digital conversion to digital voltage. Further, the control and external system interface 51 is a state machine (FSM: Finish).
e State Machine), and is connected to the pixel array section 52 and the analog-digital converter 53 so as to control the overall operation of the image sensor. Control and external system interface 51
A diagnostic logic unit 54 for verifying whether the operating states of the control and external system interface 51 and the analog-digital converter 53 are normal is connected between the analog-digital converter 53 and the analog-digital converter 53.

The analog-to-digital converter 53 is provided with a comparator 56, and the analog voltage output from the pixel array section 52 is input to the comparator 56. The comparator 56 receives the reference voltage from the ramp voltage generator 55, compares the reference voltage with the analog voltage input from the pixel array unit 52, and converts the analog voltage into digital data. Then, the comparator 56 outputs the digital data to the double buffer 57 and the double buffer 5
7 stores digital data.

Further, the diagnostic logic section 54 verifies whether the operating state of the control and external system interface 51 is normal, and the operating states of the comparator 56 and the double buffer 57 in the analog-digital converter 53 are confirmed. Verify whether it is normal.

[0008]

As described above, in the CMOS image sensor shown in FIG. 6, the diagnostic logic section 54 allows the control / external system interface 51 and the analog-digital interface which are the peripheral portions of the pixel array section 52 in the pixel area. Although the operation state of the converter 53 is verified, the operation state of the pixel array section 52, which is the center of the CMOS image sensor, must be verified using another device such as a tester.

Normally, a CMOS image sensor is subjected to a device test for verifying the operation state of each constituent block in the manufacturing process. However, in order to test each pixel in the pixel array section, a general-purpose logic device or the like is used. It is necessary to provide a dedicated circuit in addition to the circuit for the logic tester for performing the device test.

A device test for a CMOS image sensor is a test used for a device test performed on a general-purpose logic device or the like because the pixel array section of the CMOS image sensor is provided with a plurality of pixels each having a photodiode. Unlike the program, it is necessary to use a test program specific to the CMOS image sensor.

For example, FIG. 7 is a flowchart showing a device test of the CMOS image sensor shown in FIG. 6 using a tester. As shown in FIG.
In the OS image sensor, the tester performs the imaging test of the pixel array unit after the continuity test and the peripheral logic unit test. In addition, the CMOS image sensor includes a calculation process for performing the above-described imaging test on the tester side, and an analog voltage or analog-digital converter (A / A / D) that converts an optical signal detected by the pixel array unit into an electric signal. In step D), a bitmap for storing the analog-to-digital converted digital signal and a fail bitmap must be generated. Therefore, the tester requires software or a dedicated logic circuit for performing arithmetic processing.

Further, in the CMOS image sensor, the density of pixels has been increased, and both the number of gates and the occupied area are increased as compared with the peripheral logic circuit which controls the CMOS image sensor. Therefore, as the density of the pixels of the CMOS image sensor increases, the device test time for each pixel of the pixel array section increases, and the ratio of the device test time for the pixel array section in the CMOS image sensor including the peripheral logic circuit increases. It is getting bigger.

From the viewpoint of productivity such as yield,
As the density of pixels increases, the size of one pixel also decreases, which may make it difficult to suppress the defect rate in the pixel array section, and further improvement in test accuracy is required in the device test process. Has been done.

The present invention is intended to solve such a problem, and an object thereof is to make it possible to verify the operating state of each pixel of a pixel array section in a CMOS image sensor and to perform a device test of the CMOS image sensor. (EN) Provided is a CMOS image sensor that simplifies the process and shortens the test time.

[0015]

A CMOS image sensor of the present invention includes a plurality of pixels that output analog signals corresponding to incident light, and an analog-type converter that converts the analog signals output from each pixel into digital signals. A CMOS image sensor having digital conversion means, wherein the operation state of each pixel is verified using the digital signal output from each pixel and subjected to analog-digital conversion by the analog-digital conversion means. The self-diagnosis execution means is provided.

The self-diagnosis executing means is provided with a control terminal, and the self-diagnosis executing means is switched between a normal operation mode and a self-diagnosis mode by a signal inputted to the control terminal.

The signal input to the control terminal is HI.
This is a GH (H) level signal.

The self-diagnosis executing means is the analog-
An arithmetic circuit block for arithmetically operating a digital signal output from the digital converting means, a program memory in which a program for arithmetic processing by the arithmetic circuit block is stored, and a data storage memory for storing the arithmetic processing result by the arithmetic circuit block. , And a flag register for storing the end flag of the self-diagnosis mode.

The data storage memory stores a bit map for storing a digital signal output from the analog-digital conversion means, a work memory for storing a calculation processing result by the calculation circuit block, and a self-diagnosis for each pixel. It has a fail bitmap that stores the results.

An interface for outputting the data in the flag register to an external device is connected to the self-diagnosis executing means.

The self-diagnosis execution means has a switching means for switching the data storage memory and the interface between a connected state and a disconnected state, and the data storage memory is provided with an external input / output terminal. ing.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a CMOS which is an embodiment of the present invention.
It is a block diagram which shows the structure of an image sensor.

The CMOS image sensor shown in FIG. 1 has a pixel array section 12 composed of a CMOS image sensing element which can be driven with low power. The pixel array unit 12 is formed to maximize the characteristic of converting an optical signal of detected light into an electrical signal.
It has × M pixels.

FIG. 5 is a circuit diagram showing an example of a pixel configuration. Each pixel includes a photodiode 21 that performs photoelectric conversion and a transfer (tra) that converts and transfers the signal charge accumulated in the photodiode 21 into an electric signal.
transfer transistor 22 and correlated double sampling (correlated double sampling).
It has a reset transistor 23 for performing ng: CDS) processing and a select transistor 24 for selectively outputting a signal from the photodiode 21 to a signal line, and is incident on each photodiode. Light information is detected.

Each pixel of the pixel array section 12 has
The analog-digital converter (A / D) 13 is connected, and the analog voltage value detected at each pixel is converted into digital data by the analog-digital converter (A / D) 13. It The analog-digital converter (A / D) 13 outputs the digital data to the test logic unit 14.

The test logic section 14 has an arithmetic circuit block 19 to which the digital data from the analog-digital converter (A / D) 13 is input. The arithmetic circuit block 19 includes an analog-digital converter (A / D) 1
Program memory (ROM) for each pixel data that has been converted from analog to digital in 3
Based on the program stored in 20, predetermined arithmetic operations such as addition, subtraction, multiplication and division are performed.

A timing generator (TG) 11 is connected to the arithmetic circuit block 19, and the timing generator (TG) 11 is an analog-digital converter (A).
/ D) 13 and the pixel array section 12 are also connected. The timing generator (TG) 11 supplies timing signals to the arithmetic circuit block 19 of the test logic unit 14, the analog-digital converter (A / D) 13 and the pixel array unit 12 based on the external clock signal (SCLK). Output, arithmetic circuit block 1
9. The analog-digital converter (A / D) 13 and the pixel array section 12 are operated in synchronization, and the signals (analog voltage) output from each pixel of the pixel array section 12 are sequentially converted into the analog-digital converter ( A / D) 13
The analog-to-digital conversion is performed by and output to the arithmetic circuit block 19.

In the program memory (ROM) 20, a fail bit map for judging pass / fail based on the operation processing result for each pixel data executed by the operation circuit block 19 and storing the pass / fail judgment result. 1
The flow until 8c is created is stored.

The result of the arithmetic processing by the arithmetic circuit block 19 is the data storage memory 18 and the flag register 17.
Is output to. The flag register 17 stores the category of the imaging test performed in the self-diagnosis test mode for verifying the operation state of each pixel of the pixel array unit 12. The data storage memory 18 includes a bitmap 18 corresponding to the coordinates of each pixel of the pixel array unit 12.
a, a work memory 18b for temporarily storing the arithmetic processing result by the arithmetic circuit block 19, and a fail bit map 18c for storing the pass / fail judgment result of the test are provided. The data storage memory 18 is connected to the interface (I / F) 16, and a pass / fail judgment result of a self-diagnosis test for verifying an operation state of each pixel of the pixel array section 12 and a fail bit in the data storage memory 18 are provided. Data of the map 18c and the like are output to an external device via the interface (I / F) 16. Further, the flag register 17 also has an interface (I
/ F) 16 and outputs the result of the self-diagnosis test to an external device via the interface (I / F) 16.

Flag register 1 of test logic unit 14
Reference numeral 7 denotes a control terminal 1 to which an active (HIGH level) signal is applied when shifting to a self-diagnostic test mode for verifying the operation state of each pixel of the pixel array section 12.
5 is connected.

In the bit map 18a in the data storage memory 18, the light detected by each pixel of the pixel array section 12 is converted into an analog voltage of an electric signal, and the analog voltage is converted into an analog-digital converter (A / D) 13
The analog-to-digital converted digital value is stored in correspondence with the coordinates of each pixel, and the digital value calculated by the arithmetic circuit block 19 is stored.

The work memory 18b is a pixel (picture element).
The data processed by the arithmetic processing for the purpose of screening is temporarily stored.

The fail bit map 18c stores a pass / fail result in which the data of each pixel analog-digital converted into a digital value by the analog-digital converter (A / D) 13 is tested.

Next, the operation of the test logic section 14 will be described. The test logic unit 14 includes the pixel array unit 12
When an active signal is input from the control terminal 15 in order to shift to the self-diagnosis test mode for verifying the operation state of each pixel of, the arithmetic circuit block 19 stores the program stored in the program memory (ROM) 20. Pixel array unit 12 converted into a digital value based on
The calculation process of the data of each pixel is started. First, the data in which the optical signal detected by each pixel of the pixel array unit 12 is converted into a digital value is written in the area of the bitmap 18a of the data storage memory 18, and the calculation based on the category of the imaging test is performed. Operation circuit block 1 read from program memory (ROM) 20
9 and writes the calculation result in the area of the work memory 18b of the data storage memory 18. The program memory (ROM) 20 stores test specifications, and it is determined whether or not the operation result of the operation circuit block 19 passes (passes) the specifications. The pass / fail judgment result for each pixel is written in the area of the fail bit map 18c of the data storage memory 18. Furthermore, in the imaging test for the above categories, the entire pixel array section 12 has finally passed (passed) or failed (unsuitable).
It is written in the flag register 17 for each category. The self-diagnosis result of the pixel array unit 12 written in the flag register 17 is output to an external tester via the interface (I / F) 16, and the tester outputs the self-diagnosis result of the pixel array unit 12 based on the data. To judge.

The data storage memory 18 in the test logic unit 14 has an interface (I / F) 16
An address bus 18d is provided between the data storage memory 18 and the address bus 18d, so that the tester can directly access the data storage memory 18 through the interface (I / F) 16 and the bit map 18a in the data storage memory 18 can be stored. The details of the self-diagnosis result for each pixel can be read by reading the data of the area and the area of the fail bit map 18c.

FIG. 2 is a diagram showing a flow chart of a white flaw test in a dark state as an example of the category of the image pickup test. The white scratches in the dark state are the output value detected in each pixel of the effective pixel area of the pixel array unit 12 in the light-shielded state and the OB (Optical Bl).
The difference from the output value detected at each pixel in the ack area is measured, and if the difference deviates from the value specified in the test specifications, it is regarded as a white flaw. Pixels regarded as white defects are stored in the fail bit map 18c of the data storage memory 18.

Regarding the contents of the imaging test, there are various specifications and test means depending on the specifications of each device in the CMOS image sensor. In the present embodiment, as an example thereof, how each functional block operates will be described while showing a flowchart of a white defect test in a dark state.

First, the light receiving surface of the pixel array section 12 is shielded from light (step S1). Then, in order to shift from the normal operation mode to the self-diagnosis mode, the control terminal 15 is
The HIGH level is set to "H" (here, "H" represents the active state) (step S2). As a result, the test logic unit 14 determines that the self-diagnosis mode has been selected, and the program memory (ROM) 20
The arithmetic circuit block 19 reads the test flow for white scratches in the dark state stored in, and performs arithmetic processing based on the program.

The optical signal sequentially detected by each pixel of the pixel array section 12 is sent to the analog-digital converter (A / D) 13 based on the timing clock (timing signal) output from the timing generator 11. It is output (step S3). The analog voltage output from each pixel of the pixel array unit 12 is converted into digital data by the analog-digital converter (A / D) 13 (step S4). Analog-digital converter (A
The digital data obtained by the / D) 13 is not processed (processed) at all by the arithmetic circuit block 19 and is written in the bitmap area of the data storage memory 18 (step S5).

In this way, the optical signals detected by all the pixels of the pixel array section 12 are converted into digital data and written in the area of the bitmap 18a. Then, in each pixel of the OB area. The arithmetic circuit block 19 obtains the average value of the digital data corresponding to the detected optical signal (step S6).

Next, the digital data obtained by the arithmetic circuit block 19 for each pixel in the effective pixel area of the pixel array section 12 written in the bit map area of the data storage memory 18 and the OB previously obtained. The average value of the digital data of the area is subtracted, and the subtracted digital data is stored in the data storage memory 1 as white defect data.
8 is written in the work area (step S7).

Next, the value of the test spec stored in the program memory (ROM) 20 is compared with the previously obtained white defect data to determine whether each pixel in the effective pixel area is pass or fail. The pass / fail judgment result is written in the fail bit map area of the data storage memory 18 (step S8). Here, the failed (unsuitable) pixel (pixel) is written as "1", and the passed (passed) pixel is written as "0" in the fail bitmap area of the data storage memory 18.

Next, the number of fail bits written in the fail bit map is stored in the program memory (ROM) 2
For the test spec stored in 0, it is judged whether it is within the allowable range, and as a test category of white scratches in the dark state, whether it finally passed (passed) or failed (unsuitable), The pass / fail result is written in the flag register 17 (step S9). Where fail (unsuitable)
Is "1" and the pass (pass) is "0".

The final self-diagnosis result in the CMOS image sensor is output from the interface (I / F) 16 to a tester which is an external device. Further, the data of the bit map 18 a and the data of the fail bit map 18 c of the data storage memory 18 are also output to the tester via the interface (I / F) 16. In addition, the data storage memory 18 and the interface (I / F) 1
6 is provided with an address bus, so that the tester designates the memory 18 for storing data so that the data of the arbitrary bitmap 18a and the data of the arbitrary bitmap 18a can be transmitted via the interface (I / F) 16. The data of the fail bit map 18c can be read.

FIG. 3 is a conceptual diagram showing an example of the configuration of the flag register 17. The flag register 17 is a register that stores a pass / fail result for each category of the imaging test and a self-diagnosis end flag. Here, if the pass / fail result is fail (unsuitable), it is '1', if the pass / fail result is pass (pass), it is set to '0'. 1 '. The number of bits of the flag register 17 depends on the number of categories of the imaging test. In the flag register 17 shown in FIG.
As an example, the number of categories is set to 7 (7 bits), and 1 bit of the self-diagnosis end flag is inserted to represent the flag register 17 of 8 bits.

The data output terminals of the bit map 18a and the fail bit map 18c in the data storage memory 18, the address terminals of the bit map 18a and the fail bit map 18c, and the control terminal 15 of the CMOS image sensor 15 are described. May be shared with the terminal used by the CMOS image sensor in the normal operation mode.

In this case, when the active signal of "H" is applied to the control terminal 15 to shift from the normal operation mode to the self-diagnosis mode, the terminal used in the normal operation mode is the multiplexer (selector block). ), The bitmap 18a and the fail bitmap 1
The data output terminal 8c and the address terminals of the bit map 18a and the fail bit map 18c are switched. The data output terminal and the address terminal are connected to the interface (I / I
F) 16 is connected.

FIG. 4 is a diagram showing a flow chart when a device test is performed on the CMOS image sensor of the present invention by a tester.

The CMOS image sensor of the present invention has the test logic unit 12, and as shown in FIG. 4, while the tester is executing the peripheral logic unit test after the continuity test, the CMOS image sensor When the self-diagnosis mode is set, the peripheral logic section test and the pixel array section 12 imaging test are executed in parallel, and the test time can be shortened compared to the conventional CMOS image sensor test.

As shown in FIG. 4, when the test of the peripheral logic portion of the tester is finished, the test work of the tester can be finished only by reading the result of the imaging test self-diagnosed by the CMOS image sensor.

In this case, as shown in FIG. 3, in the flag register 17, in addition to the information of the pass / fail judgment result of the self-diagnosis of the CMOS image sensor of the present invention, the self-diagnosis completion of whether the self-diagnosis is completed or not is completed. Flag signal (bit0)
Is provided, and the tester can judge that the self-diagnosis test is completed by the terminal of bit0. For example, the value of the self-diagnosis end flag signal is "1" when the self-diagnosis of the CMOS image sensor is completed, and the value of the self-diagnosis end flag signal is "1" if the self-diagnosis is still in progress.
When set to 0 ', the tester monitors the terminal of bit0 outputting the self-diagnosis end flag signal of the flag register 17, and if the value output from the terminal of bit0 is'1', the result of the above-mentioned imaging test is The bit map data and the fail bit map data in the written flag register 17 and the data storage memory 18 are read out. On the other hand, if the value of the self-diagnosis end flag signal is “0”, the tester is in a hold state of waiting until the value of the self-diagnosis end flag signal becomes “1”.

In this way, the tester side can determine whether the CMOS image sensor has completed the self-diagnosis when the tester completes the test of the peripheral logic section.

As described above, the CMOS of the present invention
Since the image sensor is provided with the test logic unit 14 capable of performing the self-diagnosis of the pixel array unit 12, the self-diagnosis for verifying the operation state of each pixel of the pixel array unit 12 is possible, and the peripheral logic by the tester is enabled. The test time of the device test of the CMOS image sensor including the circuit can be shortened.

Further, the tester does not require the bit map memory, the work memory and the fail bit map memory provided on the tester side, and the CMO is used.
A test program for the S image sensor is also unnecessary.
As a result, the tester can simplify the circuit configuration and reduce the capacity of the test program.

[0056]

According to the CMOS image sensor of the present invention, an analog signal output from a plurality of pixels is converted into a digital signal by an analog-to-digital conversion means, and each analog-to-digital converted digital signal is used. Since the self-diagnosis executing means for verifying whether or not the operation state of the pixel is normal is provided, the operation state of each pixel of the pixel array section can be verified, and the CM
The device test of the OS image sensor is also simplified and the test time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a CMOS image sensor of the present invention.

FIG. 2 is a diagram showing a flowchart of a white defect test in a dark state, which is an example of an imaging test.

FIG. 3 is a conceptual diagram showing an example of a configuration of a flag register.

FIG. 4 is a diagram showing a flowchart of an imaging test of the CMOS image sensor of the present invention.

FIG. 5 is a circuit diagram showing an example of a pixel configuration.

FIG. 6 is a block diagram showing a configuration of a conventional CMOS image sensor.

FIG. 7 is a diagram showing a flowchart of an imaging test of a conventional CMOS image sensor.

[Explanation of symbols]

11 Timing generator 12 pixel array section 13 Analog-digital converter (A / D) 14 Test logic section 15 Control terminal 16 interface (I / F) 17 Flag register 18 Data storage memory 18a bitmap 18b work memory 18c fail bitmap 19 Arithmetic circuit block 20 Program memory (ROM) 21 photodiode 22 Transfer transistor 23 Reset transistor 24 selection transistor 51 Control and external interface 52 Pixel array section 53 Analog-to-digital converter 54 Diagnostic logic section 55 Lamp voltage generator 56 comparator 57 double buffer

Claims (7)

[Claims] 1. A CMOS image sensor having a plurality of pixels that output an analog signal corresponding to incident light and an analog-digital conversion unit that converts an analog signal output from each pixel into a digital signal. , Self-diagnosis execution means for verifying the operation state of each pixel using the digital signal output from each pixel and analog-digital converted by the analog-digital conversion means is provided. And CMOS image sensor. 2. The self-diagnosis executing means is provided with a control terminal, and the self-diagnosis executing means switches between a normal operation mode and a self-diagnosis mode by a signal input to the control terminal. CMOS according to claim 1
Image sensor. 3. The signal input to the control terminal is H
The CMO according to claim 2, which is an IGH (H) level signal.
S image sensor. 4. The self-diagnosis executing means, an arithmetic circuit block for arithmetically operating a digital signal output from the analog-digital converting means, and a program memory in which a program for arithmetic processing by the arithmetic circuit block is stored.
The CMOS image sensor according to claim 1, further comprising a data storage memory that stores a calculation processing result by the calculation circuit block, and a flag register that stores an end flag of the self-diagnosis mode. 5. The data storage memory stores a bit map for storing a digital signal output from the analog-digital conversion means, a work memory for storing a calculation processing result by the calculation circuit block, and a pixel for each pixel. The CMOS image sensor according to claim 4, further comprising a fail bit map that stores a self-diagnosis result. 6. The CMOS image sensor according to claim 4, wherein the self-diagnosis executing means is connected to an interface for outputting the data of the flag register to an external device. 7. The self-diagnosis executing means has a switching means for switching the data storage memory and the interface between a connected state and a disconnected state, and the data storage memory has a terminal for external input / output. The CMOS image sensor according to claim 6, which is provided.