JPH0136975B2 - - Google Patents
Info
- Publication number
- JPH0136975B2 JPH0136975B2 JP58212438A JP21243883A JPH0136975B2 JP H0136975 B2 JPH0136975 B2 JP H0136975B2 JP 58212438 A JP58212438 A JP 58212438A JP 21243883 A JP21243883 A JP 21243883A JP H0136975 B2 JPH0136975 B2 JP H0136975B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal film
- semiconductor
- electron beam
- crystal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010408 film Substances 0.000 claims description 70
- 239000004065 semiconductor Substances 0.000 claims description 34
- 239000013078 crystal Substances 0.000 claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 229910052710 silicon Inorganic materials 0.000 claims description 23
- 239000010703 silicon Substances 0.000 claims description 23
- 238000010894 electron beam technology Methods 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 14
- 239000010409 thin film Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 11
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 10
- 229910052721 tungsten Inorganic materials 0.000 description 10
- 239000010937 tungsten Substances 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 230000005457 Black-body radiation Effects 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02598—Microstructure monocrystalline
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02691—Scanning of a beam
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体薄膜結晶層の製造方法に係わ
り、特に絶縁基体上の半導体薄膜を電子ビーム照
射により溶融再結晶化する半導体薄膜結晶層の製
造方法に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor thin film crystal layer, and particularly to a method for manufacturing a semiconductor thin film crystal layer in which a semiconductor thin film on an insulating substrate is melted and recrystallized by electron beam irradiation. Regarding the method.
周知の如く、従来の２次元半導体装置の素子を
微細化してこれを高集積化・高速化するには限界
があり、これを越える手段として多層に素子を形
成する、所謂３次元半導体装置が提案されてい
る。３次元半導体装置を実現するには絶縁層上に
良質の半導体薄膜結晶層を形成する必要がある。
このため、絶縁基体上の多結晶若しくは非晶質の
半導体膜に高エネルギビームを照射しながら走査
して、租大粒の多結晶若しくは単結晶の半導体層
を形成する方法が種々提案されている。これらの
うち、大面積の単結晶領域を形成することは難し
いことから、素子を形成できる程度の幅或いは面
積の単結晶領域を形成することが試みられてい
る。
As is well known, there is a limit to miniaturizing the elements of conventional two-dimensional semiconductor devices to increase their integration and speed, and as a means to overcome this, so-called three-dimensional semiconductor devices, in which elements are formed in multiple layers, have been proposed. has been done. In order to realize a three-dimensional semiconductor device, it is necessary to form a high quality semiconductor thin film crystal layer on an insulating layer.
For this reason, various methods have been proposed in which a polycrystalline or amorphous semiconductor film on an insulating substrate is scanned while being irradiated with a high-energy beam to form a large-grain polycrystalline or single-crystalline semiconductor layer. Among these, since it is difficult to form a single crystal region with a large area, attempts have been made to form a single crystal region with a width or area large enough to form an element.
従来の方法で良く用いられているものを第１図
及び第２図に示す。第１図に示すのは、シリコン
基板１１上に堆積されたSiO2膜１２に溝を形成
し、この溝内に非晶質シリコン１３を埋め込み、
その上にSiO2膜１４を被着したのち、高エネル
ギの電子ビームを照射しながら走査し、シリコン
１３を溶融再結晶化して単結晶に形成する方法で
ある。また、第２図は同様にシリコン基板２１上
にSiO2膜２２上にシリコン層２３を形成し、こ
れを島状のシリコンに分離し、他の部分をSiO2
膜にしてその上にSiO2膜２４を被着し、その後
高エネルギの電子ビームを照射しながら走査し
て、シリコン層２３を溶融再結晶化して単結晶に
形成する方法である。 A commonly used conventional method is shown in FIGS. 1 and 2. As shown in FIG. 1, a groove is formed in a SiO 2 film 12 deposited on a silicon substrate 11, and amorphous silicon 13 is buried in the groove.
After a SiO 2 film 14 is deposited thereon, a high-energy electron beam is irradiated and scanned to melt and recrystallize the silicon 13 to form a single crystal. In addition, in FIG. 2, a silicon layer 23 is similarly formed on a SiO 2 film 22 on a silicon substrate 21, this is separated into island-shaped silicon, and the other parts are covered with SiO 2
In this method, a SiO 2 film 24 is deposited on the SiO 2 film, and then a high-energy electron beam is irradiated and scanned to melt and recrystallize the silicon layer 23 to form a single crystal.
これらの方法の特徴は、溶融すべきシリコンの
幅や面積が小さいため比較的容易に単結晶化し易
い点にあるが、シリコンの溶融再結晶化を十分に
制御していないので、分離した全てのシリコンが
一様に単結晶化するまでには至らない。しかも、
入射された電子ビームの電子の逃げ道がないの
で、ビーム損傷を避けることはできない。また、
ヒートシンク構造を持つていないので、３層以上
の多層構造に適用することは困難であつた。 These methods are characterized by the fact that the width and area of the silicon to be melted is small, making it relatively easy to single-crystallize the silicon, but since the melting and recrystallization of the silicon is not sufficiently controlled, Silicon does not reach the point where it becomes uniformly single crystal. Moreover,
Since there is no escape route for the electrons of the incident electron beam, beam damage cannot be avoided. Also,
Since it does not have a heat sink structure, it is difficult to apply it to a multilayer structure of three or more layers.
本発明の目的は、絶縁層上に均一で良質の半導
体結晶層を形成することができ、かつビーム損傷
を極めて少なくすることができ、３次元半導体装
置の実現に好適する半導体薄膜結晶層の製造方法
を提供することにある。
An object of the present invention is to manufacture a semiconductor thin film crystal layer that can form a uniform, high-quality semiconductor crystal layer on an insulating layer, minimize beam damage, and is suitable for realizing a three-dimensional semiconductor device. The purpose is to provide a method.
本発明の骨子は、溶融再結晶化すべき半導体膜
上の絶縁膜上に金属膜を被着し、この金属膜の存
在により半導体膜の結晶化過程を制御すると共
に、ビーム損傷を防止することにある。
The gist of the present invention is to deposit a metal film on an insulating film on a semiconductor film to be melted and recrystallized, and to use the presence of this metal film to control the crystallization process of the semiconductor film and to prevent beam damage. be.
すなわち本発明は、半導体薄膜結晶層の製造方
法において、絶縁基体上に多結晶若しくは非結晶
質の半導体膜を形成し、次いでこの半導体膜上に
絶縁膜を介して金属膜を被着し、かつこの金属膜
にストライプ状の凹部を形成してこの凹部で膜厚
を薄くし、しかるのち高エネルギの電子ビームを
照射し上記半導体膜を溶融再結晶化せしめるよう
にした方法である。 That is, the present invention provides a method for manufacturing a semiconductor thin film crystal layer, in which a polycrystalline or amorphous semiconductor film is formed on an insulating substrate, a metal film is then deposited on the semiconductor film via an insulating film, and In this method, striped recesses are formed in the metal film, the film thickness is reduced by the recesses, and then a high-energy electron beam is irradiated to melt and recrystallize the semiconductor film.
本発明によれば、ストライプ状に凹部を形成し
た金属膜の存在、具体的には凹部とこの凹部両側
の金属膜の膜厚差により、電子ビーム照射により
半導体膜に吸収される熱量と金属膜に拡散される
熱量とを制御することができる。しかも、入射さ
れた電子ビームが金属膜を流れるので、ビーム損
傷を防止することができる。このため、均一で良
質な単結晶層を容易に実現することができ、その
有用性は極めて大きい。また、金属膜がヒートシ
ンク構造として作用するので、３層以上の多層構
造にも十分適用することができる。
According to the present invention, the amount of heat absorbed by the semiconductor film due to electron beam irradiation is reduced by the presence of a metal film having striped recesses, specifically, the difference in thickness between the recess and the metal film on both sides of the recess. It is possible to control the amount of heat diffused into the Moreover, since the incident electron beam flows through the metal film, damage to the beam can be prevented. Therefore, a uniform and high-quality single crystal layer can be easily realized, and its usefulness is extremely large. Furthermore, since the metal film acts as a heat sink structure, it can be sufficiently applied to a multilayer structure of three or more layers.
第３図ａ〜ｄは本発明の一実施例に係わる半導
体薄膜結晶層製造工程を示す断面図である。ま
ず、第３図ａに示す如くＰ型（100）面方位の単
結晶シリコン基板３１上に、絶縁膜として約１
〔μm〕のSiO2膜３２を形成した。ここで、シリ
コン基板３１には既に所望の素子が周知の工程に
より形成されているものとする。次いで、第３図
ｂに示す如くSiO2膜３２上に0.5〔μm〕の非晶質
シリコン膜３３を被着した。続いて、第３図ｃに
示す如くシリコン膜３３上に0.2〔μm〕の保護用
SiO2膜３４を被着し、さらにその上に１〔μm〕
のタングステン膜（金属膜）３５を被着した。
FIGS. 3a to 3d are cross-sectional views showing the manufacturing process of a semiconductor thin film crystal layer according to an embodiment of the present invention. First, as shown in FIG.
A SiO 2 film 32 of [μm] was formed. Here, it is assumed that desired elements have already been formed on the silicon substrate 31 by a well-known process. Next, as shown in FIG. 3b, an amorphous silicon film 33 of 0.5 [μm] was deposited on the SiO 2 film 32. Next, as shown in FIG.
A SiO 2 film 34 is deposited, and a layer of 1 [μm]
A tungsten film (metal film) 35 was deposited.
次に、所望の素子を形成するに十分の大きさの
領域、例えば100〔μm〕×500〔μm〕の面積部分の
みタングステン膜３５にテーパを付けながらエツ
チングして凹部を形成し、第３図ｄに示す如くこ
の領域のタングステン膜３５の膜厚を0.2〔μm〕
と薄くした。次いで、連続電子ビームをビーム源
として用い、電子ビームの加速電圧を10〔KeV〕、
シリコン基板３１に到達するビーム電流を５
〔mA〕とする200〔μm〕×40〔μm〕の線状電子ビ
ームを用い、第４図に示す如く100〔μm〕×500
〔μm〕の領域４１の長手方向に沿つて電子ビーム
４２を垂直な方向に向けて５〔mm／sec〕の速度で
走査した。このとき、電子ビームアニール中の熱
の拡散を防ぐために、シリコン基板３１の温度を
500〔℃〕まで上げておいた。その結果、100〔μm〕
×500〔μm〕の領域において、略完全な単結晶シ
リコン層が得られた。 Next, a recess is formed by etching the tungsten film 35 while tapering only a region large enough to form a desired element, for example, an area of 100 [μm] x 500 [μm], as shown in FIG. As shown in d, the thickness of the tungsten film 35 in this region is 0.2 [μm].
I thinned it out. Next, using a continuous electron beam as a beam source, the acceleration voltage of the electron beam was set to 10 [KeV],
The beam current reaching the silicon substrate 31 is
Using a 200 [μm] x 40 [μm] linear electron beam with [mA], 100 [μm] x 500
The electron beam 42 was scanned in the vertical direction along the longitudinal direction of a region 41 of [μm] at a speed of 5 [mm/sec]. At this time, the temperature of the silicon substrate 31 is adjusted to prevent heat diffusion during electron beam annealing.
The temperature was raised to 500 [℃]. As a result, 100 [μm]
A substantially complete single crystal silicon layer was obtained in a region of ×500 [μm].
ここで、本発明における重要な点は、金属膜の
膜厚の差により熱の吸収と拡散とを制御すること
にある。すなわち、前記実施例においてタングス
テン膜３５の膜厚の厚い部分（1μm）に入射した
電子ビームは、その下のシリコン膜３３までは殆
ど達しない。そして、タングステン膜３５に入射
した電子は速やかに拡散されるため、タングステ
ン膜３５の膜厚の厚い部分の下のシリコン膜３３
の温度はあまり高くならない。これに対し、膜厚
の薄い部分（0.2μm）に入射した電子ビームは下
のシリコン膜３３まで達してその温度を上昇させ
る。このため、まずタングステン膜３５の膜厚の
薄い部分の下のシリコン膜から溶融が始まる。ま
た、タングステン膜３５の膜厚が薄い部分では、
溶融したシリコンからの熱伝導による熱拡散より
も黒体輻射による熱拡散が大きいため、溶融した
シリコンの中心部分から再結晶化が起こり、結晶
粒界を発生することなく略完全な単結晶が実現さ
れるのである。 Here, the important point in the present invention is to control the absorption and diffusion of heat by the difference in the thickness of the metal film. That is, in the embodiment described above, the electron beam incident on the thick portion (1 μm) of the tungsten film 35 hardly reaches the silicon film 33 below. Since the electrons incident on the tungsten film 35 are quickly diffused, the silicon film 33 under the thick part of the tungsten film 35
temperature does not rise very high. On the other hand, the electron beam incident on the thin part (0.2 μm) reaches the underlying silicon film 33 and raises its temperature. Therefore, the silicon film under the thinner portion of the tungsten film 35 begins to melt. In addition, in the thin part of the tungsten film 35,
Because heat diffusion due to black body radiation is greater than heat diffusion due to heat conduction from molten silicon, recrystallization occurs from the center of the molten silicon, creating an almost perfect single crystal without generating grain boundaries. It will be done.
なお、本発明は上述した実施例に限定されるも
のではない。実施例では線状電子ビームを用いて
長方形の領域を単結晶化したが、幅の狭い溝に埋
め込まれたシリコンならばスポツト状電子ビーム
を照射走査すれば、均一な単結晶領域が得られ
る。また、金属膜はタングステンに限るものでは
なく、モリブデン、その他融点の高いものであれ
ばよい。さらに、金属膜に形成する凹部の大きさ
形状等は、仕様に応じて適宜定めればよい。ま
た、再結晶化すべき半導体膜として、多結晶シリ
コンを用いてもよいのは勿論のことである。その
他、本発明の要旨を逸脱しない範囲で、種々変形
して実施することができる。 Note that the present invention is not limited to the embodiments described above. In the embodiment, a rectangular region was made into a single crystal by using a linear electron beam, but if silicon is buried in a narrow groove, a uniform single crystal region can be obtained by scanning the silicon with a spot-shaped electron beam. Further, the metal film is not limited to tungsten, but may be molybdenum or any other material having a high melting point. Further, the size and shape of the recess formed in the metal film may be determined as appropriate depending on the specifications. Furthermore, it goes without saying that polycrystalline silicon may be used as the semiconductor film to be recrystallized. In addition, various modifications can be made without departing from the gist of the present invention.
第１図及び第２図はそれぞれ従来の半導体薄膜
結晶層の製造方法を説明するための断面図、第３
図ａ〜ｄは本発明の一実施例に係わる半導体薄膜
結晶層製造工程を示す断面図、第４図は上記実施
例におけるビームアニール方法を説明するための
斜視図である。
３１…シリコン基板、３２…SiO2膜、３３…
非晶質シリコン膜（半導体膜）、３４…保護用
SiO2膜（絶縁膜）、３５…タングステン膜（金属
膜）。
1 and 2 are cross-sectional views for explaining the conventional method of manufacturing a semiconductor thin film crystal layer, respectively.
Figures a to d are cross-sectional views showing the manufacturing process of a semiconductor thin film crystal layer according to an embodiment of the present invention, and Fig. 4 is a perspective view for explaining the beam annealing method in the above embodiment. 31... Silicon substrate, 32... SiO 2 film, 33...
Amorphous silicon film (semiconductor film), 34...for protection
SiO 2 film (insulating film), 35...tungsten film (metal film).
Claims (1)
膜を形成する工程と、上記半導体膜上に絶縁膜を
介して金属膜を被着し、かつ該金属膜にストライ
プ状の凹部を形成して該凹部で膜厚を薄くする工
程と、次いで、上記金属膜の上から前記半導体膜
に高エネルギの電子ビームを、該ビームの周縁部
が上記凹部の両側の厚い金属膜に位置するように
して該凹部に沿つて移動させ、これにより金属膜
上から前記半導体膜に高エネルギの電子ビームを
照射し該半導体膜を溶融再結晶化せしめる工程と
を具備したことを特徴とする半導体薄膜結晶層の
製造方法。 ２ 前記金属膜にストライプ状の凹部を周期的、
かつ平行に形成し、前記電子ビーム照射により金
属膜下に周期的にストライプ単結晶領域を形成す
るようにしたことを特徴とする特許請求の範囲第
１項記載の半導体薄膜結晶層の製造方法。 ３ 前記金属膜にストライプ状の凹部を島状に形
成し、前記電子ビーム照射により金属膜下に島状
のストライプ単結晶領域を形成するようにしたこ
とを特徴とする特許請求の範囲第１項記載の半導
体薄膜結晶層の製造方法。 ４ 前記絶縁基体として、シリコン基板上にシリ
コン酸化膜を形成したものを用いることを特徴と
する特許請求の範囲第１項記載の半導体薄膜結晶
層の製造方法。[Claims] 1. A step of forming a polycrystalline or amorphous semiconductor film on an insulating substrate, depositing a metal film on the semiconductor film via an insulating film, and forming a stripe-like pattern on the metal film. A step of forming a recess and reducing the film thickness in the recess, and then applying a high-energy electron beam to the semiconductor film from above the metal film so that the peripheral edge of the beam touches the thick metal film on both sides of the recess. The semiconductor film is moved along the recess so that the metal film is positioned, and the semiconductor film is irradiated with a high-energy electron beam from above the metal film to melt and recrystallize the semiconductor film. A method for manufacturing a semiconductor thin film crystal layer. 2 Periodically form striped recesses in the metal film.
2. The method of manufacturing a semiconductor thin film crystal layer according to claim 1, wherein striped single crystal regions are formed in parallel and periodically under the metal film by the electron beam irradiation. 3. Striped recesses are formed in the metal film in the form of islands, and island-like striped single crystal regions are formed under the metal film by the electron beam irradiation. The method for manufacturing the semiconductor thin film crystal layer described above. 4. The method of manufacturing a semiconductor thin film crystal layer according to claim 1, wherein the insulating substrate is a silicon oxide film formed on a silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58212438A JPS60105219A (en) | 1983-11-14 | 1983-11-14 | Manufacture of semiconductor thin film crystal layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58212438A JPS60105219A (en) | 1983-11-14 | 1983-11-14 | Manufacture of semiconductor thin film crystal layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60105219A JPS60105219A (en) | 1985-06-10 |
| JPH0136975B2 true JPH0136975B2 (en) | 1989-08-03 |
Family
ID=16622602
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58212438A Granted JPS60105219A (en) | 1983-11-14 | 1983-11-14 | Manufacture of semiconductor thin film crystal layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60105219A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5895687A (en) * | 1981-11-30 | 1983-06-07 | Nec Corp | Growth of crystal granule of thin film |
-
1983
- 1983-11-14 JP JP58212438A patent/JPS60105219A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5895687A (en) * | 1981-11-30 | 1983-06-07 | Nec Corp | Growth of crystal granule of thin film |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60105219A (en) | 1985-06-10 |
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