JPH0136133B2 - - Google Patents

Info

Publication number
JPH0136133B2
JPH0136133B2 JP58127569A JP12756983A JPH0136133B2 JP H0136133 B2 JPH0136133 B2 JP H0136133B2 JP 58127569 A JP58127569 A JP 58127569A JP 12756983 A JP12756983 A JP 12756983A JP H0136133 B2 JPH0136133 B2 JP H0136133B2
Authority
JP
Japan
Prior art keywords
cache memory
data
cache
address
processing device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58127569A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6020254A (ja
Inventor
Yoshiharu Oono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP58127569A priority Critical patent/JPS6020254A/ja
Publication of JPS6020254A publication Critical patent/JPS6020254A/ja
Publication of JPH0136133B2 publication Critical patent/JPH0136133B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP58127569A 1983-07-15 1983-07-15 デ−タ処理装置 Granted JPS6020254A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58127569A JPS6020254A (ja) 1983-07-15 1983-07-15 デ−タ処理装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58127569A JPS6020254A (ja) 1983-07-15 1983-07-15 デ−タ処理装置

Publications (2)

Publication Number Publication Date
JPS6020254A JPS6020254A (ja) 1985-02-01
JPH0136133B2 true JPH0136133B2 (enrdf_load_html_response) 1989-07-28

Family

ID=14963284

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58127569A Granted JPS6020254A (ja) 1983-07-15 1983-07-15 デ−タ処理装置

Country Status (1)

Country Link
JP (1) JPS6020254A (enrdf_load_html_response)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61193245A (ja) * 1985-02-21 1986-08-27 Hitachi Ltd 記憶制御方式
JPS61267149A (ja) * 1985-05-21 1986-11-26 Nec Corp デ−タ処理装置

Also Published As

Publication number Publication date
JPS6020254A (ja) 1985-02-01

Similar Documents

Publication Publication Date Title
US4648034A (en) Busy signal interface between master and slave processors in a computer system
JPH0425579B2 (enrdf_load_html_response)
JPH0526212B2 (enrdf_load_html_response)
US5226132A (en) Multiple virtual addressing using/comparing translation pairs of addresses comprising a space address and an origin address (sto) while using space registers as storage devices for a data processing system
US4618926A (en) Buffer storage control system
US5287483A (en) Prefetched operand storing system for an information processor
JP3088303B2 (ja) キャッシュ・メモリ・バンク制御装置
KR19990037571A (ko) 단일 주기 내에 간접 어드레싱 모드 어드레스를 출력하는 데이터 포인터 및 그 제공방법
JPH0136133B2 (enrdf_load_html_response)
JP3005626B2 (ja) データ処理システムおよびデータ転送方法
JPH0233182B2 (enrdf_load_html_response)
JPH0516061B2 (enrdf_load_html_response)
US4853889A (en) Arrangement and method for speeding the operation of branch instructions
JP3284508B2 (ja) データ先読み制御装置
JPH01177145A (ja) 情報処理装置
JP2581298B2 (ja) メモリアクセス権情報供給機構
JP2864548B2 (ja) 命令キャッシュ装置
JPS6031646A (ja) デ−タ処理装置
JPH035620B2 (enrdf_load_html_response)
JPH01255933A (ja) 掃出し制御方式
JPH1055303A (ja) メモリシステム
JPS6027966A (ja) データ処理装置
JPS63311548A (ja) キャッシュメモリ制御回路
JPH0447344B2 (enrdf_load_html_response)
JPH03237538A (ja) 緩衝記憶装置