JPH0135303B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a signal storage device that stores input signals in a storage circuit in response to a clock signal.

[Background of the invention]

Signal storage devices include waveform storage devices (also known as transient digitizers, transient recorders, waveform digitizers, or digital oscilloscopes) and logic analyzers. The waveform storage device converts an analog input signal into a digital signal by an analog-to-digital (A/D) converter,
This digital signal is stored in a digital storage circuit (memory) in synchronization with a clock signal, and the stored digital signal is converted into an analog signal by a digital-to-analog (D/A) converter. Note that there is also a type of waveform storage device that stores an analog input signal in an analog memory such as a CCD in synchronization with a clock signal. In addition, a logic analyzer stores logic (digital) signals in digital memory in synchronization with a clock signal.
It is similar in principle to a waveform storage device, except for the A/D converter and D/A converter. These signal storage devices also store input signals before the trigger signal is generated.
In other words, it is very convenient because it can be measured.

By the way, while measuring the entire input signal using these signal storage devices, there are cases where it is desired to measure in detail a portion of interest where a trigger signal occurs (for example, a portion where a transient occurs). In this case, by lowering the clock frequency, the entire input signal can be stored in a memory with limited storage capacity, but the portion of interest cannot be measured in detail. Also, if you increase the clock frequency, you can measure the part of interest in detail, but
Measuring the entire waveform requires a very large storage capacity.

[Prior art and its problems]

The conventional technology for solving such problems is
It is disclosed in JP-A-57-33363 or JP-A-58-224498. If the signal storage device is a waveform storage device, this prior art stores the input signal in a first memory in response to a low frequency clock signal, and stores the input signal in a second memory in response to a high frequency clock signal. Then, the trigger circuit counts a predetermined number of clocks from the trigger point detected in accordance with the part of interest (transient) of the input signal, stops the write mode of the first and second memories, and stores the entire input signal in the first memory. is stored roughly, and the transient of the input signal is stored in detail in the second memory. Therefore, not only the entire input signal can be measured, but also the transients of the input signal can be measured in detail.

Incidentally, there are cases where it is desired to continuously store a plurality of intermittently occurring parts of interest using a signal storage device. Even in such a case, it would be very convenient to be able to measure a plurality of parts of interest as a whole and also to be able to measure each part of interest in detail. However, with the above-mentioned conventional technology, only one part of interest of the input signal can be stored, and the timing relationship between the contents stored in the first memory and the second memory cannot be accurately known. Therefore, with this conventional technique, it is not possible to measure each of a plurality of intermittently occurring portions of interest of an input signal in detail, and to roughly measure the entire input signal.

The same problem arises when the prior art described above is applied to a logic analyzer instead of a waveform storage device.

[Purpose of the invention]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to roughly store the entire input signal including a plurality of parts of interest;
To provide a signal storage device that stores each part of interest in detail.

[Summary of the invention]

According to the signal storage device of the present invention, a predetermined amount of input signals after the trigger signal is generated are stored in the main memory area in accordance with the low frequency clock signal, and input signals near and after the trigger signal are generated. The input signals around the time when each trigger signal is generated are stored in each of the plurality of sub-memory areas in accordance with the high frequency clock signal. Thus, the main memory area roughly stores the entire input signal including a plurality of parts of interest, and each of the sub memory areas stores each part of interest in detail. In addition, since the addresses of the main memory area and sub memory area at the time of each trigger signal generation are latched, input signals stored in the main memory area and sub memory area can be selectively read out according to these latched addresses. The input signal can be played back continuously.

[Embodiments of the invention]

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram of a preferred embodiment of the present invention, in which the signal storage device is a waveform storage device. An analog input signal at an input terminal 10 is supplied to an A/D converter 12, and this analog input signal is supplied to a trigger circuit 14 to generate a trigger signal. As shown in FIG. 2, this trigger circuit 14 includes a comparator 18 that compares the input signal from the input terminal 10 and the trigger level from the potentiometer 16, and a comparator 18 that shapes the output signal of this comparator 18 into a waveform. The waveform shaping circuit 20 is a one-shot multivibrator.
Therefore, the trigger circuit 14 is configured such that the input signal triggers the trigger circuit 14.
When the level is exceeded, a positive pulse (trigger signal) is generated.

The clock generator 22 is, for example, a reference clock generator 24 which is a crystal oscillator as shown in FIG.
, a frequency divider 26 that divides the output signal of this generator 24 to generate a plurality of divided outputs, and this frequency divider 2
6, multiplexers (MUX) 28 and 30 each select one from a plurality of output signals. Note that the MUXs 28 and 30 may be controlled by external control signals, or mechanical switches may be used instead of the MUXs. The output end of MUX28 is terminal H, and the output end of MUX30 is terminal L.
, the frequency of the clock signal at terminal H is equal to the frequency of the clock signal at terminal L.
Be sure to set it higher than the clock signal.

The A/D converter 12 converts the analog input signal from the terminal 10 into a digital signal according to the high frequency clock signal from the clock generator 22, and transfers this digital signal to the first memory 32, second memory 34, and third memory. 36 and a fourth memory 38. The first memory 32 becomes the main memory area, and the second to fourth
Memories 34 to 38 serve as sub-memory areas. These memories 32-38 are, for example, random access memories (RAM). Memory control circuit 4
0 receives the trigger signal from the trigger circuit 14 and the low frequency clock signal and high frequency clock signal from the clock generator 22, generates address signals etc. for the memories 32 to 38, and outputs address signals for the memories 32 to 38.
38 write and read operations.
The MUX 42 outputs one of the read output signals of the memories 32 to 38 in response to a control signal from the memory control circuit 40.
One is selected and supplied to the D/A converter 44. This D/A converter 44 returns the digitized input signal to an analog signal, for example, a cathode ray tube (CRT).
to the vertical deflection means of the display 46. On the other hand, the D/A converter 48 converts the horizontal address signal synchronized with the read address from the memory control circuit 40 into a staircase wave signal, and converts the horizontal address signal synchronized with the read address from the memory control circuit 40 into a staircase wave signal,
horizontal deflection means.

Next, the operation of FIG. 1 will be explained with reference to the waveform diagram of FIG. 4. In a write operation, memory control circuit 40 places memories 32-38 in a write mode and enables the chip select (C/S) terminal of each memory. Also, the control circuit 40
generates address signals for the first memory 32 in response to the low frequency clock signal L from the clock generator 22, and generates address signals for the second to fourth memories 34 to 38 in response to the high frequency clock signal H. Occur. Note that these address signals are circular address signals depending on the storage capacity of the memory, and the address signals for the memories 34 to 38 may be common. As mentioned above, the A/D converter 12 converts the analog input signal from the input terminal 10 into a digital signal in response to the high frequency clock signal H. Further, since the low frequency clock signal L is synchronized with the high frequency clock signal H, the first memory 32 sequentially stores the digital signals at the time when the low frequency clock signal L is generated. On the other hand, the second to fourth memories 34 to 38 store digital signals at the time when the high frequency clock signal H is generated. The address signal is a circular signal, so when a digital signal is stored at all addresses in the memory,
The oldest (first stored) digital signal is sequentially updated to a newer digital signal.

When the trigger circuit 14 generates the first trigger signal at time T2, the memory control circuit 40 starts counting the high frequency clock signal H. When the control circuit 40 finishes counting a predetermined number of high frequency clock signals H at time T3, it stops enabling the chip select terminal of the second memory 34, that is, stops the write operation of the second memory 34. Therefore, the second memory 34 stores this counting operation and the memory 3.
The digital value of the input signal between time points T1 and T3 determined by the relationship with the storage capacity of 4 is stored. Similarly,
When the trigger circuit 14 generates a second trigger signal at time T5, the memory control circuit 40
At T6, the write operation of the third memory 36 is stopped. Therefore, the third memory 36 stores time points T4 and T6.
Stores the digital value of the input signal between. Furthermore, when the trigger circuit 14 generates a third trigger signal at time T8, the memory control circuit 40 generates a third trigger signal at time T9.
At this point, the write operation of the fourth memory 38 is stopped. The fourth memory 38 thus stores the digital value of the input signal between times T7 and T9.

On the other hand, the memory control circuit 40 starts counting the low frequency clock signal L in response to the trigger signal at time T2. When the control circuit 40 finishes counting a predetermined number of low frequency clock signals L at time T10, it stops enabling the chip select terminal of the first memory 32, that is, stops the write operation. Therefore, the first memory 32 performs the counting operation at the time T0 determined by the relationship between this counting operation and the storage capacity of the memory 32.
and stores the digital value of the input signal between T10 and T10.
Therefore, the first memory 32 roughly stores the entire input signal including a plurality of parts of interest (transients), and each of the second to fourth memories 34 to 38 stores each part of interest in detail. Note that the control circuit 40
are the addresses of the first memory 32 and the second to fourth memories 34 to 3 at the trigger times T2, T5 and T8.
8 address is memorized.

In the read operation, the entire input signal is displayed on the display 4.
6, the MUX 42 selects the first memory 32 in response to a control signal from the memory control circuit 40. The control circuit 40 also controls the first memory 32
is in a read mode, and a read address signal is generated and supplied to the first memory in response to a predetermined read clock signal. This read address signal is applied to the first memory 3 at the first level of the above-mentioned time axis (horizontal) signal.
Read the oldest memory contents of 2. Therefore, the entire rough input signal is displayed on the display 46. Note that the time axis signal is synchronized with the read operation of the memory. In addition, if you want to display only a specific part of interest in detail, the MUX 42 selects the desired one from the second to fourth memories 34 to 38 and reads out the stored contents of the selected memory in the same way as described above. good.

By the way, according to the present invention, it is possible to simultaneously measure the entire stored input signal roughly and the portion of interest in detail. To do this, the memo control circuit 40 first checks the address of the first memory 32 and the memory 3 at each trigger time.
Time points T1, T3, T4, T6, from storage capacity of 4 to 38
Calculate the addresses of the first memory 32 corresponding to T7 and T9. The control circuit 40 generates the time axis signal T from the portion corresponding to time T0, and also outputs the MUX
42 selects the first memory 32. MUX 42 selects second memory 34 when corresponding to time T1, selects first memory 32 when corresponding to time T3, selects third memory 36 when corresponding to time T4, and selects first memory 32 when corresponding to time T6. , the fourth memory 38 is selected when it corresponds to time T7, and the first memory 32 is selected when it corresponds to time T9. Then, when corresponding to time T10, the time axis signal T ends, and the above-described operation is repeated again from time T0. That is, between time T0 and T1, time T3 and
between T4, between time points T6 and T7, and between time points T9 and
The digital value of the input signal between T10 is stored in the first memory 32.
The digital value of the input signal between time points T1 and T3 is read from the second memory 34, and the digital value of the input signal between time points T4 and T6 is read from the third memory 34.
6 and the digital value of the input signal between times T7 and T9 is read from the fourth memory 38. Then,
The entire input signal can be roughly measured, and only the portion of interest within it can be measured in detail.

Next, as described above, the memories 32 to 38 and MUX
An example of the memory control circuit 40 that controls 42 will be described. FIG. 5 is a block diagram of the write control section of the control circuit 40, and FIG. 6 is a block diagram mainly centered on the read control section. The entire writing and reading operations are carried out by the arithmetic control unit 50 shown in FIG.
Controlled by This device 50 consists of a microprocessor, a read-only memory that stores programs for the microprocessor, a random access memory that operates as a temporary storage device, and a keyboard that allows various settings to be made. and is connected to bus 52.

When the start of the write mode is input from the keyboard of the arithmetic and control unit 50, the D-type flip-flops 54-64 of FIG. 5 are reset by the device 50 (control lines for resetting are not shown). Also, the MUX 66 is controlled by the control signal from the device 50.
selects address counter 68 and MUX 70
selects address counter 72. Additionally, the device 50 places the memories 32-38 in a write mode;
A predetermined number is set in delay counters 74 and 76 (control lines are not shown).

Since delay counter 74 is not enabled and its output is at a "high" level before the trigger signal is generated, address counter 68 is enabled to count the low frequency clock signal L from clock generator 22 and generate an address signal. do. This address signal is supplied to the address terminal of the first memory 32 via the MUX 66. On the other hand, address counter 7
2 counts the high frequency clock signal H from the clock generator 22 to generate an address signal, and MUX 7
0 to the memories 34-38.
Supplied to the address terminal of Since the memories 34-38 have the same capacity, a common address signal can be used. Note that the address signals from counters 68 and 72 are circular signals. By the way, the "high" level output from the OR gates 77 to 82 is output from the memory 3.
Since each of the chip select terminals 2-38 is supplied, the memories 32-38 are operating in a write mode.

When the trigger circuit 14 generates the first trigger signal at time T2, the flip-flop 54
The Q output of is at the "high" level, and the delay counter 7
6 is reset and starts counting from the beginning.
Meanwhile, at time T2, the latch circuit 84 latches the address signal for the first memory 32, and the latch circuit 86 latches the address signal for the second to fourth memories 34-38. The Q output of flip-flop 54 also enables delay counter 74 to begin operating low frequency clock signal L, and AND gate 88 is enabled. At time T3, when delay counter 76 has counted a predetermined number of clock pulses, the output signal of counter 76 is flipped through AND gate 88.
Clock flop 60. Therefore, the output of flip-flop 60 goes low, stopping operation of second memory 34 via OR gate 78. Therefore, the second memory 34
stores the digital value of the input signal between time points T1 and T3, which is determined by its storage capacity and the count value of the counter 76, for example.

Similarly, at time T5, the trigger circuit 14
Upon generation of the second trigger signal, the Q output of flip-flop 56 goes high, enabling AND gate 90. Also, the counter 76 is reset again and starts a new count,
Latches 84 and 86 each latch a corresponding address signal. At time T6, counter 76
After counting a predetermined number of clock pulses, its output signal clocks flip-flop 62 through AND gate 90. Therefore, the output of flip-flop 62 is passed through OR gate 80 to stop the operation of third memory 36. Therefore, the third memory 36 stores the time T4 and
Stores the digital value of the input signal between T6.

At time T8, when the trigger circuit 14 generates a third trigger signal, the flip-flop 5
The Q output of 8 enables AND gate 92 and resets counter 76 to make a new count. On the other hand, latch circuits 84 and 86 latch their respective address signals. At time T9, when counter 76 has counted a predetermined number of clock pulses, flip-flop 64 is clocked by the output of AND gate 92 and, via OR gate 82, stops operation of fourth memory 38. The fourth memory 38 thus stores the input signals between times T7 and T9. On the other hand, time point T10
Once the delay counter 74 has counted a predetermined number of clock pulses, its output goes low, stopping the operation of the first memory 32 via the OR gate 77. Therefore, the first memory 3
2 stores the input signal between time points T0 and T10.

Next, referring mainly to FIG.
The read operation will be explained. Arithmetic control unit 50 places memories 32-38 in read mode and enables the chip select terminals of each memory via OR gates 77-82. Additionally, MUX 66 and 70 are also switched. A clock generator 94 generates a read clock signal and a counter 96 counts the read clock signals. This count output (address signal) causes the D/A converter 48 to output the time axis signal T.
, the minimum count value and maximum count value correspond to the left and right edges of the screen of the display 46, respectively. Note that the point in time to which the address signal from the counter 96 corresponds is different from the address of each memory corresponding to this point in time, and in order to make these addresses correspond to each other, an offset corresponding to the address of each memory at the end of the write operation is required. Please note that this is necessary. Therefore, the arithmetic and control unit 50 calculates the values of the address counters 68 and 72 at each trigger instant latched by the latch circuits 84 and 86;
Based on the storage capacity of the memories 32 to 38, etc.
While calculating the addresses from the counter 96 corresponding to T1, T3, T4, T6, T7 and T9,
The addresses from the counter 68 (addresses for the first memory 32) corresponding to T3, T6, and T9 are calculated.

When the address of the counter 96 corresponds to time T0, the arithmetic and control unit 50 loads the address of the first memory 32 corresponding to the time T0 into the address counter 98, and loads the address of the counter 96 corresponding to the time T1.
Load the address of 6 into register 100. Also, since D-type flip-flops 102 and 104 have been reset, AND gate 106
is enabled and AND gate 108 is not enabled. Therefore, address counter 9
8 begins counting the clock signals from clock generator 94 that have passed through AND gate 106.
Note that since the MUX 42 selects the first memory 32 at this time, the digital values of the corresponding input signals after time T0 are sequentially supplied from the first memory to the D/A converter 44. Further, the arithmetic control unit 50 loads the address of the second memory corresponding to time T1 into the address counter 110, and loads the address of the counter 96 corresponding to time T3 into the register 110.
Load into.

When the digital comparator 114 compares the output signals of the counter 96 and the register 100 and detects that the address of the counter 96 corresponds to time T1,
Comparator 114 connects flip-flops 102 and 1
04 and the MUX 42 clocks the second memory 34.
be selected. flip flop 10
Since the output of 2 becomes "low" level, and
Gate 106 is closed and counter 98 stops counting. Also, the Q of flip-flop 104
When the output goes to "high" level, AND gate 1
08 is opened and the address counter 110 starts counting from the address of the second memory 34 at time T1. On the other hand, the arithmetic control unit 50 loads the address of the first memory 32 corresponding to time T3 into the counter 98, and loads the address of the counter 96 corresponding to time T4 into the register 100. Digital comparator 116 includes counter 96 and register 112.
When the address of counter 96 corresponding to time T3 is detected, flip-flops 102 and 104 are reset, and the flip-flops 102 and 104 are reset.
Clocks flops 118-122. Thus, the AND gate 106 is opened, the address counter 98 generates the address of the first memory 32 after time T3, and the AND gate 108 is closed;
Address counter 110 stops counting. Meanwhile, the Q output of flip-flop 118 changes and MUX 42 selects first memory 32. Therefore, the digital value of the input signal after time T3 is supplied from the first memory 32 to the D/A converter 44. The arithmetic and control unit 50 then loads the address of the third memory 36 corresponding to the time T4 into the address counter 110, and loads the address of the counter 96 corresponding to the time T6 into the register 112.

Similar operations are performed thereafter, and at time T4,
In response to the output signal of the comparator 114, the counter 110
The address signal from the MUX 42 is applied to the third memory 36, and the MUX 42 selects the third memory 36. Then, the address of the first memory 32 corresponding to time T6 is loaded into the counter 98, and the address of the counter 96 corresponding to time T7 is loaded into the register 100. At time T6, comparator 116 produces an output signal, counter 98 begins counting, and the change in the Q output of flip-flop 120 causes MUX 42 to select first memory 32. Furthermore, the address of the fourth memory corresponding to time T7 is loaded into counter 110, and the address of counter 96 corresponding to time T9 is loaded into register 112. Therefore, at time T7, address counter 110 starts counting and MUX 42 starts counting.
Select memory 38. Next, the address of the first memory 32 corresponding to time T9 is loaded into the counter 98. At time T9, address counter 98 starts counting and MUX 42
Select 2. When the arithmetic and control unit 50 detects the address of the counter 96 corresponding to time T10, it returns to the state of the above-mentioned time T0 and repeats the above-described operation.
Note that since the oscillation frequency of the clock generator 94 is low, there is no problem with the above-described loading operation.

Although the foregoing describes only preferred embodiments of the invention, those skilled in the art will appreciate that various modifications can be made without departing from the spirit of the invention. For example, although the signal storage circuit in the above embodiment is a waveform storage circuit, it may also be applied to a logic analyzer. In this case, the A/D converter and the D/A converter may be removed and the trigger circuit may be a word recognizer (detects a predetermined digital word from the input digital signal). Further, an external trigger signal and an external clock signal may be used, or a shift register may be used in the storage circuit. Further, the number of the plurality of sub-memory areas may be any desired number, and each sub-memory area may not be used as each memory element.
Multiple sub-memory areas may be provided within a single memory device. In this case, the addresses of the memory elements may be divided into a plurality of groups, each group designated by the upper bits of the address signal, and the addresses within each group designated by the lower bits of the address signal.
For this purpose, it is convenient for the write operation to prepare an upper bit counter that counts the trigger signal as a clock and a lower bit counter that counts the high frequency clock signal. Also, in the read operation, the upper bits and lower bits of the address signal may be generated separately.

〔Effect of the invention〕

As described above, according to the present invention, the entire input signal including a plurality of portions of interest can be roughly stored in the main memory area, and each of the portions of interest can be stored in detail in a plurality of sub-memory areas. It is also possible to roughly reproduce the entire input signal in the main memory area, and replace only the portion of interest with a signal finely reproduced in the sub memory area. Further, a latch circuit latches the main memory area address signal and the sub memory area address signal at the time of each successive trigger signal generation. Therefore, according to these latched address signals, input signals stored in the main memory area and the sub memory area are selectively read out, preferentially using the sub memory area, and the input signals are continuously reproduced in the order in which they were stored. can.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a preferred embodiment of the present invention, FIG. 2 is a block diagram showing an example of a trigger circuit used in FIG. 1, and FIG. 3 is an example of a clock generator used in FIG. 1. 4 are waveform diagrams for explaining the operation of the present invention, and FIGS. 5 and 6 are block diagrams showing an example of the memory control circuit of FIG. 1. In the figure, 22 is a clock generator, 32 is a main memory area, 34 to 38 are sub memory areas, 40 is a memory control circuit, 68 and 72 are address counters, and 84 and 86 are latch circuits.

Claims (1)

[Scope of Claims] 1. A clock generator that generates a high-frequency clock signal and a low-frequency clock signal, a main memory area, a plurality of sub-memory areas, and a memory control that controls the main memory area and the plurality of memory areas. a first address counter that counts the low frequency clock signal to generate an address signal for the main memory area; and a first address counter that counts the low frequency clock signal and generates an address signal for the main memory area; a second address counter that generates an address signal for the area; a first latch circuit that latches the address signal from the first address counter at the time when the trigger signal is generated successively; 2 addresses/
It has a second latch circuit that latches the address signal from the counter, and in a write operation, the input signal after the first trigger signal is generated by a predetermined amount according to the address signal from the first address counter. In addition to storing the input signal in the main memory area, a predetermined amount of the input signal near the time point at which each of the continuously generated trigger signals is generated is stored in each of the plurality of sub memory areas in accordance with the address signal from the second address counter. When the input signals are sequentially stored in the main memory area and the sub-memory area in accordance with the address signals latched in the first and second latch circuits, the input signals are stored in the sub-memory area. A signal storage device characterized in that a portion of the input signal other than the input signal is read from the main memory area.