JPH0131744B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an encoding method for simultaneously transmitting secondary information in class partial response code transmission. Secondary information in the simultaneous transmission system as described above generally includes low-speed status information such as warnings, various game commands, and management information. When transmitting data using codes with such redundancy,
We have already discussed how to transmit the above secondary information by intentionally violating this encoding rule.
An example of transmitting control information using a violation in AMI (Alternate Mark Inversion) encoding is known. Now, the class partial response code is 2
Since the AMI codes of the series are interleaved, it is possible to transmit secondary information through the above violation. On the other hand, code errors during data transmission can be constantly monitored using the redundancy of class partial response codes, but this method uses a method to detect violations of coding rules caused by transmission errors. It will be done. Therefore, it has conventionally been thought that transmission of secondary information due to violation of encoding rules and monitoring of code errors are incompatible. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method that enables transmission of secondary information while constantly monitoring code errors in class partial response code transmission. In order to achieve the above object, the present invention focuses on the fact that in the case of normal transmission path errors, when the error rate is not so large, two or more consecutive violations almost never occur. By performing an operation that causes two consecutive violations, it is possible to simultaneously transmit secondary information and monitor code errors. According to the present invention, in the encoding method of class partial response code transmission, on the transmitting side, the output of the precoder is taken every other bit, and the length 4 is
When the bit code pattern matches either 0X1X0X0 or 1X0X1X1 in the order of occurrence,
The corresponding encoder output pattern, 1X−1, is −
It has a violation operation function that converts to 1X-1 and -1X1 to 1X1 and outputs them, and the receiving side is equipped with a violation detector with a coding rule based on summation. If a single violation is obtained in the output of the transmitter, it is considered to be a transmission path code error, and if two consecutive violations occur with one bit in between, it is considered to be a violation performed on the transmitting side. An encoding system is obtained that is characterized by having a function for determining operations. Next, a detailed description will be given with reference to the drawings. FIG. 1 is a diagram for explaining a class partial response code. In Figure 1, 4
5 represents a mod 2 adder (+), 5 represents a subtracter (Σ), and 6 represents a 1-bit delay element (T), respectively. And between the input binary code system example a _o , the intermediate binary code sequence b _o , and the output ternary code sequence c _o , b _o = a _o + b _o-2 (mod2) c _o = b _o −b _o-2 …(1) There is a relationship where a _o and b _o take two values of 0 or c _o
It is well known that the value takes three values: -1, 0, or 1. FIG. 2 is a diagram for explaining violation detection in the receiving section. In FIG. 2, 7 is an adder, 8 is a modulo-2 discriminator, and 9 is a violation detector. This violation detector outputs 1 as the output v _o when it detects a violation, and outputs 1 as the output v _o when it does not detect a violation.
In addition to this, it also has a function to correct the cumulative _sum so to 1 or 0 according to an algorithm. Input c _o ' indicates that the output of FIG. 1 was erroneously transmitted by c _o . this
c _o ′ is combined with a o ′ by the modulo-2 discriminator 8 as follows: a _o ′=c _o ′ ₍ 2). On the other hand, the cumulative sum s _o is expressed as s _o = s _o ′ _-2 + c _o ′ …(3). Here, the output of the violation detector 9, s _o ', is determined as follows. In other words, when s _o is 0 or 1, there is no violation (v _o = 0), so it remains as s _o ' without any modification, and when s _o is greater than 1 or less than 0, there is no violation. Therefore, the modified form becomes s _o ′. To put the above more specifically, when s _o is 0 or 1: s _o ′ = s _{o ′} When s _o is greater than 1: s _o ′ = 1 When s _o is less than 0: s _o ′ =0...(4) FIG. 3 is a diagram showing an example in which the functions of the encoder and violation detector described above are performed in a conventional manner. In the example of FIG. 3, three independent errors are detected with v _o =1. However, it is not always possible to obtain v _o =1 at the time an error occurs, and there may be some delay. The example in FIG. 3 is a case of a central error. A detailed explanation of this figure will be omitted, but it will be easily understood from the explanation of FIG. 5 later. Now, in the case of normal transmission path errors, if the error rate is not so large, most of the errors occur randomly at adjacent levels (0→±1, 1→0, -1→0). In other words, it can be said that there are almost no cases where _vo becomes 1 two or more times in a row. Here, "twice in succession" means that since the class partial response code is essentially an interleaving of two sequences, v _k = 1 and v _{k +2} = 1 occur. It is. No such code error is shown in FIG. Focusing on the above points, the present invention intentionally adds a characteristic violation in the transmitting section so that the violation detector in the receiving section detects "two consecutive" violations. , it is possible to transmit secondary information while monitoring single code errors on the transmission path. The characteristic point of the present invention is that the encoder
A violation that reverses the polarity of c _o-4 when b _o is one of b _o-6 b o- ₄ b _o-2 b _o (i) 0X1X0X0 (ii) 1X0X1X1 ...(5) It is to perform an operation (hereinafter referred to as VIOL operation). Note that X is the other interleaved series, and is the same as the above series b _o .
Not related to VIOL operation. to c _o-4 of output series c _o
If the output after VIOL operation is c _o ^* , and Y is a value of 0 or 1, then c _o and the output after operation c _o ^* correspond to the above series b _o , and b _o : 0X1X0X0 1X0X1X1 c _o :YX1X−1X0 YX−1X1X0 ↓VIOL operation ↓VIOL operation c _o ^* :YX−1X−1X0 YX1X1X0 Represented. That is, the class partial
The response encoder output 1X−1X0 is −1X−1X0
Also, -1X1X0 characteristically adds violation to 1X1X0. In this way, 1→-1,
If a violation occurs from -1 to 1, no code error occurs, and the violation detector (9 in Figure 2) using the cumulative sum described above detects ``two consecutive'' violations. Since this is detected, it is possible to distinguish this from a transmission error and know the intention of the transmitter, that is, it becomes possible to transmit secondary information at a low speed. In addition, in the above, the other series X is the series b _o
Although it was stated that it is unrelated to the VIOL operation, in series X, VIOL can be performed independently. FIG. 4 is a block diagram illustrating a method for performing VIOL operation according to the present invention. In FIG. 4, 11 and 12 are pattern detectors, 13 is a logic circuit, and 14 is a polarity inverter. The pattern detector 11 has its inputs 21, 22, 23 and 2
Output 2 when 4 are 0, 1, 0 and 0 respectively
5 becomes 1, and the pattern detector 12 reads 1, 0,
With inputs of 1 and 1, the output is 26 and 1. The outputs 25 and 26 pass through the OR circuit 13 and become 27. When the output 27 is 1, the polarity inverter 14 is driven, and when c _o ' _-4 is 1, it becomes -1, and -1. In this case, 1 is output to the output line 28, and the VIOL operation is performed. FIG. 5 is a diagram for explaining the encoding and violation detection operations in the present invention. Fifth
In the figure, the arc (dotted line) of a set of three digits shown in the column b _o has both ends and the four digit codes indicated by the connecting part, which are the characteristics of the present invention. 0100 or 1011 shown in the relationship (5)
It shows that it is the target of VIOL operation. Note that two sets of arcs are written at the top and two sets at the bottom, indicating that the lower set is based on another interleaved series. in this way
The codes 1 and -1 of c _o corresponding to the second code 1 or 0 of each set subject to VIOL operation are converted to -1 and 1, respectively, as indicated by VIOL operation in the figure. , are circled in the c _o ^* column.
And this c _o ^* is transmitted and upon receiving this
c _o ' (from FIG. 1 to FIG. 2), but there is only one code error during this period, as shown by . Then c _o ′ is
According to the relationship in equation (2), it becomes a _o ′, and according to the relationship in equation (3), it becomes s _o .
Therefore, from the relationship (4), the violation detection output _vo is set to 1 at the signs of -1 and 2. If we look at the above violation detection output v _o in more detail, we can see that for the VIOL operation applied at the transmitter,

As shown in [Formula], v _k and v _k+2 are detected as 1 "twice in a row", but if a single error occurs in the transmission path, it is an error to the adjacent level, so □1
This is detected as a stand-up violation as shown in . Therefore, by distinguishing the characteristic violation that occurs "twice in succession" from the stand-up violation, it is possible to detect an intentional violation operation for transmitting secondary information at the transmitter. FIG. 6 is a diagram for explaining a method for performing the above-mentioned transmission error monitoring and secondary information detection according to the present invention. In FIG. 6, the input v _o is the violation output detected by the violation detector 9 in FIG. 2, 31 is an AND circuit, 32 and 33 are both exclusive OR circuits, and 34 is a It is a threshold detector. In this circuit, “2” based on VIOL operation
"Consecutive" violations are detected at output 35, and consecutive violations due to transmission errors are output at 36. Threshold detector 34 outputs 3
When the detection frequency of "two consecutive" violations appearing in 5 exceeds a certain value, the transmitter determines that a violation is being performed and outputs secondary information to 37. The output 36 can be used for monitoring as a transmission line error (but only a single adjacent level error). Note that the threshold value detector 34 may be of a type that outputs an output to the output 113 when the number of violations appearing at the output 35 within a certain time exceeds a certain value. FIG. 7 shows a specific embodiment of an encoder for applying violation operations according to the present invention. In FIG. 7, 41, 42, 43 are exclusive OR circuits, 44, 45, 46 are AND circuits, 4
7 is an OR circuit, and the many circuits indicated by SR are 1-bit shift registers. The input data is a _o , and the output is c _o-4 ^*-4 , which takes three values, and is expressed as a 2-bit two's complement number, with the polarity bit being 48 and the first
The bit is 49. As described above, according to the present invention, in class partial response coded transmission, transmission path code errors are constantly monitored without generating code errors, and secondary information (status information) is transmitted. Means are provided to allow simultaneous transmission.

[Brief explanation of drawings]

Figure 1 is a diagram for explaining class partial response encoding, Figure 2 is a diagram for explaining a system for detecting violations due to transmission errors in the encoded transmission/reception section, and Figure 3 is a diagram for explaining class partial response encoding. A diagram showing an example of conventional encoding and violation detection operations, FIG. 4 is a diagram for explaining the method of performing violation operation according to the present invention, and FIG. FIG. 6 is a diagram illustrating a method for monitoring transmission errors and detecting secondary information according to the present invention, and FIG. 7 is a specific embodiment of the encoder according to the present invention. FIG. Explanation of symbols: 3 is a mod2 adder, 4 is a subtracter, 5 is a 1-bit delay element (T), 8 is a modulo 2 discriminator, 9 is a violation detector, 11 and 1
2 is a pattern detector, 13 is a logic circuit, 14 is a polarity inverter, 31 is an AND circuit, 32 and 33 are exclusive OR circuits, 34 is a threshold value judger, S is a 1-bit delay element (same as 5) , SR represent shift registers, respectively.

Claims (1)

[Claims] 1. In the encoding system for class partial response code transmission, on the transmitting side, a code pattern of length 4 bits obtained by taking every other bit of the output of a precoder is coded in the order of occurrence as 0X1X0X0, 1X0X1X1, It has a violation operation function that converts and outputs the corresponding encoder output pattern, 1X-1 to -1X-1, and -1X1 to 1X1, when it matches either one of the following. , The receiving side is equipped with a violation detector that uses a cumulative sum encoding rule, and when a single violation is obtained in the output of the detector, it is regarded as a transmission line code error, and one bit is 1. An encoding system characterized by having a function of determining that when two consecutive violations occur in the above, it is a violation operation performed on the transmitting side.