JPH01317017A - Oscillation circuit - Google Patents

Abstract

PURPOSE:To reduce the occupied area of an integrated chip and to attain the oscillation at a comparatively lower and wider frequency by controlling the charge/discharge of a capacitor intermittently. CONSTITUTION:A clock with a high frequency obtained comparatively easily is used in an oscillation circuit oscillated through the provision of an input delay means 2 between the input and output of an inverse amplification means 1 and a control means 3 applies charge/discharge of a capacitor C2 of an input delay means 2 intermittently by controlling the turning on/off of switch means S1-S4. The delay between the input and output deciding the oscillating frequency is increased and the oscillation at a low frequency is attained. Thus, the oscillation output with a comparatively lower frequency is obtained and the oscillation circuit with a small occupied area on the chip and facilitating the circuit integration is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an oscillation circuit with a relatively low frequency, and particularly to an oscillation circuit that can be easily integrated into an integrated circuit.

[Prior Art] In integrated circuits, IMHz to 0. Conventionally, when an oscillation output with a relatively low frequency of about IMHz is required, the following means have been used.

(1) Assemble an oscillation circuit discretely outside the integrated circuit.

(2) Integrating an oscillation circuit using a crystal oscillator on an integrated circuit chip.

(3) Integrating extremely multi-stage ring oscillators on an integrated circuit chip.

[Problem to be solved by the invention] However, in the oscillation circuit in the above conventional technology,
Each had the following problems.

(1) Discretely assembled r! An oscillation circuit occupies a large amount of mounting space on a board, printed circuit board, etc. on which the circuit is mounted, reducing mounting efficiency and requiring an increase in board area.

(2) When integrating an oscillation circuit using a crystal oscillator, the manufacturing process of the integrated circuit becomes complicated.

(3) When integrating a ring oscillator, the ring oscillator alone occupies a large amount of chip area.

The present invention was created in order to solve the above problems, and its purpose is to provide an oscillation circuit that can obtain a relatively low frequency oscillation output, is easy to integrate, and occupies a small area on a chip. do.

[Means for Solving the Problems] The configuration of the oscillation circuit of the present invention for achieving the above object includes: an amplification means whose output is inverted with respect to the input; The present invention is characterized in that it comprises an input delay means including a capacitor given as: and a control means connected to the output and intermittently charging and discharging the capacitor by means of a switch means turned on/off by a high frequency clock.

[Function] The present invention provides an oscillation circuit that provides input delay means between the input and output of an inverting amplification means to perform oscillation, and uses a relatively easily obtained high frequency clock to control on/off of a switch means. By doing so, the control means intermittently charges and discharges the capacitor of the input delay means, thereby increasing the amount of delay between input and output that determines the frequency of the oscillation,
oscillate at a low frequency.

[Example] Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 1 is a circuit diagram of an oscillation circuit showing one embodiment of the present invention. This embodiment includes an inverting amplifier circuit 1 and an inverting amplifier circuit l.
an input delay circuit 2 consisting of a capacitor C1 connected to the input side of the inverting amplifier circuit 1; and a high frequency two-phase clock φ connected to the output side of the inverting amplifier circuit 1.

The control means 3 includes a control means 3 that intermittently charges and discharges the input delay circuit 2 using a clock φ1, and a clock oscillation circuit 4 that oscillates a high frequency two-phase clock φ1°φ.

The inverting amplifier circuit l includes an odd number (three on the school side) of inverters 11, 12, . . . which perform inverting amplification. ta are connected in series, and the inverter 11 is connected to the input side.

The inverter 13 is on the output side. It is preferable that the input side of the inverting amplifier circuit l includes at least one inverting amplifier (for example, a Schmitt trigger circuit) having a history of transfer function. shall be included. Inverting amplifier circuit! The low frequency oscillation output obtained by, for example, branches the output of this shift trigger circuit (inverter) 11,
It is taken out via the inverter 5.

A capacitor C3 constituting the input delay circuit 2 is connected between the input of the inverter l'l and the ground G.

The control circuit 3 includes a capacitor CI and four switches s,
s,,s,,s,, each switch sl.

S t, S s, and S 4 are formed of transistors.

The value of capacitor C3 is a desired ratio smaller than that of capacitor C1. One terminal A of capacitor C8 is
It is connected to the output side of the inverting amplifier circuit l (output of the inverter 13) via the switch S, and is connected to the ground G via the switch S.

The other terminal B of the capacitor C3 is connected to the input side terminal (input of the inverter 11) of the inverting amplifier circuit l of the capacitor C3 via the switch S3, and is connected to the terminal of the capacitor C3 on the input side (input of the inverter 11)
Connect to ground G via 4.

The on/off of the switches Sl and S is controlled by the clock φ, and the on/off of the switch 5tas- is controlled by the clock φ.

The clock oscillation circuit 4 can be easily constructed by connecting an odd number (seven in the figure) of inverters 41 to 47 in series to form a loop. Two-phase clock φ5. φ1 is branched from the output of inverter 43 and inverter 47 and taken out via inverters 48 and 49, each including a Schmitt trigger circuit. 2-phase clock φeiφ,
It is important that there is no overlap in the relationship.

The operation of the embodiment configured as above will be described.

FIG. 2 is a waveform diagram of each part for explaining the operation of this embodiment. First, in a state where the capacitor C2 is not charged, the output of the inverting amplifier circuit l becomes a high level (hereinafter referred to as H). In the control circuit 3, the switches S,, S, are turned on during the period when the clock φ, is H, the capacitor C1 is slightly charged by the H output of the inverting amplifier circuit I through the capacitor CL, and the switches St, Ss are turned off. Then, the charged potential is held. While the switches Sl and S3 are off, the clock φ becomes H, and the capacitor C1 becomes the ground potential and is discharged. By repeating this cycle, intermittent charging is performed on capacitor C2, and the charging potential is changed to capacitor C1 and C2.
It gradually increases toward the value determined by the capacity division of 3 (
. During the rise of the charging potential, when the Schmitt trigger circuit 11 reaches the rising threshold level VTI (1), the output of the inverting amplifier circuit 1 becomes a low level (described below). .

Next, in the above final state, the control circuit 3 turns on the switches S, , S, by the clock φ, and switches S2, .,S, by the clock φ. During the period when S4 is turned off,
The capacitor C8 is discharged by the L output of the inverting amplifier circuit 1. Discharging in this case is also performed intermittently as in the case of charging, and the potential of capacitor C2 is changed between capacitors C3 and C3.
The potential is decreased by the amount determined by the capacitance division. In this way, the charging potential also gradually decreases towards the ground potential,
During the downward movement, the downward threshold level Vrn' (V?) of the Schmitt trigger circuit 11 is reached.
HL<VTH'), the output of the inverting amplifier circuit 1 becomes H again, and the above steps are repeated, causing the inverting amplifier circuit 1 to oscillate.

The oscillation period of the clock oscillation circuit 4 is T', and the power supply voltage is VO.
If it is O, it is an inverting amplifier circuit! The period T of the oscillation output obtained by is expressed as follows. As is clear from this equation, the oscillation period T
is determined not by the absolute values of capacitors Ct and Cm but by their ratio, which is suitable for CMOS process. In this embodiment, the delay amount of the capacitor C9 that determines the oscillation period is increased by intermittent charging and discharging, and a small capacitance is
An oscillation output with a low frequency of about MHz to 0 and 1 MHz is obtained. That is, in this embodiment, oscillation with a period several tens to hundreds of times lower than that in the case where intermittent charging and discharging is not performed is possible.

Since the clock oscillation circuit 4 described above is a high-frequency oscillation circuit, it can be easily integrated using any known clock oscillation circuit, occupies a small area on a chip, and is compatible with other circuits of this embodiment. The number of elements is small, the overall integration is easy, and the area occupied on the chip can be reduced.

Note that the number of stages of the inverting amplifier circuit 1 is not limited, and may be one stage in the extreme. In addition, each capacitor C+, C
t can also be formed by connecting a plurality of elements in parallel or in series.

Further, the control circuit 3 connects the capacitor C1 to the inverting amplifier circuit I
It is sufficient if the battery can be charged and discharged intermittently with the output of , and charging and discharging may be performed using a high resistance circuit.

It goes without saying that the present invention can be applied not only to CMOS processes but also to various semiconductor manufacturing processes. As described above, the present invention can be applied in various ways and can take various embodiments in accordance with its gist.

[Effects of the Invention] As is clear from the above description, the oscillation circuit of the present invention provides the following effects.

(1) Integration becomes easier.

(2) When integrated, the area occupied on the chip is very small.

(3) Relatively low wide frequency (for example, P4 IOMHz ~ 0
．． 1MHz).

(4) Can be manufactured using only the CMOS process;
Suitable for S process.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an oscillation circuit showing one embodiment of the present invention, and FIG. 2 is a waveform diagram of each part for explaining the operation of this embodiment. l...inverting amplifier circuit, 2...input delay circuit, 3...
・Control circuit, 4... Clock oscillation circuit, CI, Ct・
・Capacitor.

Claims (1)

[Claims] (1) an amplifying means whose output is inverted with respect to the input; an input delay means connected to the input and including a capacitor that provides a charge/discharge potential as the input; and an input delay means connected to the output and turned on/off by a high frequency clock. An oscillation circuit comprising: control means for intermittently charging and discharging the capacitor by means of a switch means for turning off the capacitor.