JPH01314022A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit corresponding to the 16-bit mode and the 12-bit mode with a comparatively small scale by using a shift register required also for the 16-bit mode in common with the expansion of the 12-bit mode. CONSTITUTION:The circuit consists of a shift register 5 converting serially a 1-word 16-bit parallel data and a shift control circuit 4 controlling the shift clock of the shift register 5. In case of the 16-bit mode, tie data of the shift register 5 is outputted as it is and in case of the 12-bit mode, the number of times of shifting is decided from the high-order 4-bit in the 12-bit data, the remaining 8-bit and a fixed 8-bit are loaded to the shift register 5, the shift register 5 is shifted by number of times to generate and output the 16-bit data. Thus, a circuit corresponding to both the 16-bit and 12-bit modes is obtained with a comparatively small circuit scale.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is applied to rotary head type digital audio tape recorders (hereinafter referred to as DAT), etc.
The present invention relates to a digital signal processing circuit configured to realize both a 16-bit mode and a 12-bit mode.

[Conventional technology]

- Conventionally, in a general DAT, when inputting the output from the memory to a digital-to-analog conversion circuit (hereinafter referred to as a D/A conversion circuit), 8-bit parallel data is
Converts to bit serial data. FIG. 4 shows a circuit for converting this 8-bit parallel data into 16-bit serial data (hereinafter referred to as a D/A interface circuit), in which 1 is a data bus connected to the memory, 21. 22 is an 8-bit D-type launch (
5 is a parallel manual/serial output 16-bit shift register (hereinafter referred to as shift register).

Next, the operation will be explained. The 8-bit parallel data output from the memory is transferred to latches 21 and 2, 8 bits at a time.
2, then load all 16 bits into the shift register 5 and output them serially.

[Problem to be solved by the invention]

As described above, the conventional circuit supports only the 16-bit mode, but not the 12-bit mode.

Therefore, the present invention has been made to solve the above-mentioned problems, and is a digital signal processing circuit that is compatible with both 16-bit mode and 12-bit mode and that can share circuits. The purpose is to obtain a D/A interface circuit.

[Means to solve the problem]

The digital signal processing circuit according to the present invention has 16 words per word.
It is equipped with a shift register that converts bit parallel data into serial data and a shift control circuit that controls the shift clock of the shift register.When in 16-bit mode, the shift register data is output as is, and when in 12-bit mode, it outputs the 12-bit data. The number of shifts is determined from the upper 4 bits of the 12-bit data, the lower 8 bits of the 12-bit data and the fixed 8 bits are loaded into the shift register, and the shift register is shifted the above number of times to generate and output 16-bit data. This is how it was done.

[Effect]

Since the digital signal processing circuit of the present invention doubles as a shift register necessary for 16-bit mode as well as 12-bit decompression, it is possible to realize a circuit compatible with 16-bit mode and 12-bit mode with a relatively small circuit scale.

〔Example〕

Here, the rules for compressing 16-bit data into 12 bits and the rules for converting 12-bit audio data words (hereinafter referred to as words) into 8-bit audio data symbols (hereinafter referred to as symbols) are standardized by DAT. I will explain about it.

First, the rules for compressing 16-bit data to 12 bits are shown in Figure 5, and an explanatory diagram especially for positive polarity is shown in Figure 6.The compression rules will now be explained along Figure 6. . In Figure 6, '0'' and 'l'' represent the data of each bit, and the round numbers indicate the bit positions of 16-bit data, and the least significant bit (hereinafter referred to as LSB) is expressed as ■. Yes, the value is “O” in both cases.
” or “1”, the compression rule starts with the upper 8 bits of 16-bit data, and then divides the data into 12 bits depending on the number of consecutive MSBs.
The upper 4 bits of the bit data are the 8 bits from the next bit whose polarity is inverted from the uniquely determined 0th MSB, and these are taken as the lower 8 bits of the 12-bit data. In this way, 16 bit data is compressed to 12 bits.

Next, the rules for converting 12-bit words into 8-bit symbols will be explained. The above rules are shown in FIG. 7. In FIG. 7, one of the first two channel words is set to At and the other is Bi, three symbols are created from the two channel words, and each word The upper 8 bits of Aiu are taken as one symbol,
Btu) The lower 4 bits of each word are combined and
One symbol (AB i f) is generated.

From the above, when compressed 12-bit data is expanded to 16 bits, the number of consecutive MSHs is determined from the upper 4 bits of the 12-bit data, and after the MSB is consecutive, the bit whose polarity has been reversed is 1 bit. After that, the lower 8 bits of the 12-bit data are added, and if there is a shortage of 16 bits, add "0" to the lower part. create.

Hereinafter, one embodiment of the present invention will be described based on the drawings.

In FIG. 1, 1 is a data bus connected to memory;
21 and 22 are 8-bit latches, 31 is a selector, and A
Switch between ch and Bch. 32 is a selector for switching between 16-bit mode and 12-bit mode. 5 is a shift register, and 4 is a shift control circuit, the details of which are shown in FIG. 3, and which control the shifting of the shift register 5.

Further, FIG. 2 shows a timing chart of a clock for operating this circuit. CHCK is a channel clock, "0°" represents the A channel, and "1" represents the B channel.

Next, the shift control circuit is shown in FIG. This shift control circuit 4 has a counter 41, 3 manual power N0R42°0R43, A
It consists of an ND44 and three EXNOR45s.

Next, the operation of the circuit having the above configuration will be explained.

In the case of 16-bit mode, select A with selector 32,
1. ．． 1. 8-bit parallel data from data bus 1 is stored in latches 21 and 22 at t.

Load the 16-bit data into shift register 5 with C
Outputs serially using LK1.

In addition, in the case of 12-bin mode, select B with the selector 32. First of all, t+? The upper 8 bits of the A channel are stored in the latch 21, and the lower 4 bits of each of the A channel and the B channel are stored in the latch 22 at t2. and t
, the upper 4 bits of the A channel are loaded into the counter 41 to determine the number of consecutive MSBs. At the same time, the selector 31 selects the lower 4 bits of the A channel on the A side (d7 to d).
4), and selects 1. Load it into shift register 5. Then, at the same time as the shift register 5 is shifted by 5FCK, the counter 41 is down-counted, and when the output of the counter becomes all "0", that is, when the output of the gate 42 becomes "L", the gate 43
0 stops the output of 5FCK, no clock is supplied to the shift register 5, and the shift operation is stopped.
For example, if the 2-bit data is data 111 as shown in FIG. 0th order, the expanded 16-bit data in the shift register 5 is serially outputted by CLK1.

Next, at t4, the upper 8 bits of the B channel are stored in the latch 21, and at t, the upper 4 bits of the B channel are loaded into the counter 41, as in the case of the A channel. 4 bits (d3
~40) is loaded into the shift register 5 by the selector 32 along with 8 bits of dll~d8 and ground potential, and after performing a shift operation in the same way as the A channel, the 16 bit data expanded by CLK1 is loaded. output serially.

In the shift control circuit 4 of the above embodiment, the counter 41 is counted down, but the input/output is inverted (4
(Use 3 manual AND for 2 and EOR for 45) and count the amps.

〔Effect of the invention〕

As described above, the present invention includes a shift register that converts one word of 16-bit parallel data into serial data, and a shift control circuit that controls the shift clock of the 8-bit shift register. Output the data as is, and in the 12-bit mode, determine the number of shifts from the upper 4 bits of the 12-bit data, load the remaining 8 bits and the fixed 8 bits into the shift register, shift the shift register the above number of times, and then
Since bit data is generated and output, it is possible to realize a circuit compatible with both the 16 bit mode and the 12 bit mode with a relatively small circuit scale.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a D/A interface circuit according to an embodiment of the present invention, Fig. 2 is a timing chart of a clock that operates the circuit of Fig. 1, and Fig. β shows details of a shift control circuit. Figure 4 is a block diagram of a conventional circuit, Figure 5 is a diagram showing the data compression rules standardized in DAT, Figure 6 is an explanatory diagram of the data compression rules, and Figure 7 is a symbol for words. FIG. In the figure, 5 is a shift register, 4 is a shift control circuit, 31.32 is a selector, 21.22 is a latch, and 1 is a data bus. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a digital signal processing circuit that receives m (m is a positive integer) bit data or p (p is a positive integer where p<m) bit data obtained by compressing m bits as input and outputs m bit data, m-bit length shift register means having a parallel/serial conversion function for storing input data, and when in a mode in which m-bit data is input, the m-bit length is input to the shift register means as parallel input data.
bit data, and when in a mode in which p bit data is input, the lower order (p-l) of the input p bit data is input as parallel input data to the shift register means.
selector means for giving bits as upper bits and a predetermined fixed value of (m-p+l) bits as lower bits;
In the bit data input mode, shifting of the shift register means is prohibited, and in the p-bit data input mode, the upper l of input p-bit data (l is a positive integer such that l<p)
1. A digital signal processing circuit comprising: shift control means for inputting bits and shifting said shift register means in the direction of lower bits by a number of times corresponding to the value of said l bit.