JPH01312672A - Picture processor - Google Patents

Abstract

PURPOSE:To equalize the loads of processors by dispersing variance among blocks by a feedback system using a multistage switch even though there is the variance among the blocks in connection with the processing quantity of picture data inputted by a common bus. CONSTITUTION:The title processor is provided with one input bus 20, one output bus 30, plural processors 1-8 to perform picture processing, the multistage switching circuits 41a-41d, 42a-42d, 43a-43d and a passing means to connect the intermediate processed result of each of plural processors to other processor through the multistage switching circuit 40. Thus, each of plural processors 1-8 can perform dynamic load dispersion through the multistage switching circuit 40 by the passing means, and each processor can be made to operate effectively, and whole processing capacity can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device, and in particular, when image processing is performed using a plurality of processors, it is possible to dynamically reduce the processing load of image processing of each processor. The present invention relates to image processing devices distributed throughout the world.

[Conventional technology]

Conventionally, for example, an image processing apparatus that performs image processing of a moving image must perform image processing for one screen within one frame time of one image. Therefore, when the processing capacity is insufficient, the image processing apparatus is configured with a multiprocessor configuration including a plurality of processors. An example of such a multiprocessor image processing device having a multiprocessor configuration is as follows.
It is shown in FIG. The multiprocessor image processing device shown in FIG. 8 has a configuration in which a plurality of processors 11 to 13 are commonly connected to an input bus 20 and an output bus 30. Each of the plurality of processors 11 to 13 has an image area fixedly determined in advance for each image to be processed, and each processor takes in only the area image data assigned to it from the input bus 20 and processes it. The processing results are sent to the output bus 30 in the same order as when they were sent.

That is, in such a configuration, each of the plurality of processors is the first area processor 11 . Second region processor 12.
. . . It is divided by the n-th area processor 13 and the image area of the image data to be processed, and the processor for a certain area is...

Image data in other areas is not processed.

[Problem to be solved by the invention]

However, in such an image processing apparatus, in the case of encoding processing such as vector quantization.

Normally, as a primary process, validity/invalidity is determined based on the difference with the image data of the previous frame, and vector quantization is performed only on valid pixels as a secondary process. In this case, the ratio of effective pixels included in the area shared by each processor is 0%.
However, in the case of video conference images, etc., the overall amount is about 30% at most. Therefore, an image processing device with a multiprocessor configuration as shown in FIG. 8 must be designed on the assumption that 100% of effective pixels always exist, and usually about two-thirds of its processing power is wasted. There was a problem.

The present invention has been made to solve the above problems.

SUMMARY OF THE INVENTION An object of the present invention is to provide dynamic processing so that the amount of processing is equalized even when the amount of processing for image data taken in via an input bus is extremely different between the processors in an image processing device configured with a plurality of processors. An object of the present invention is to provide an image processing device that performs load distribution and improves overall processing capacity.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

In order to achieve the above object, one aspect of the present invention is as follows.

The image processing device includes one input bus, one output bus, a plurality of processors connected to the input bus and the output bus to perform image processing, and a multistage switch circuit including a plurality of 2×2 switches; The present invention is characterized by comprising path means for connecting intermediate processing results of each of the plurality of processors to each of the other processors via the multistage switch circuit.

[Effect]

According to the above means, the two image processing devices include one input bus, one output bus, a plurality of processors that perform image processing, a multistage switch circuit, and the intermediate processing results of each of the plurality of processors. and bus means for connecting to each of the other processors via a multi-stage switch circuit. Each of the plurality of processors that perform image processing can perform dynamic load distribution via a multi-stage switch circuit by a path means.
Each processor can be used effectively, and the overall processing capacity can be improved.

That is, a multi-stage switch circuit is provided, and, for example, an input/output port is provided that serves as a path means for connecting each processor and the multi-stage switch circuit. Thereby, by using the multi-stage switch circuit and the bus means, the intermediate processing results of the image processing of each processor can be supplied to any other processor, and dynamic load distribution can be performed appropriately.

The image data supplied to each processor that performs image processing is distributed from the input bus to each processor, and then
Primary processing is performed by distributed processors. As a result of the primary processing 1. As it becomes clear that there are variations in the load related to the secondary processing among individual processors, the image data of the intermediate processing result after the primary processing is now distributed to the processors with a smaller load using a multi-stage switch circuit. . After the secondary processing is completed in the processor to which the image data has been distributed, the multistage switch circuit again routes the image data to the processor that has been assigned the secondary processing. This makes it possible to dynamically distribute the load, and to output all processed image data in the same order as when it was input.

In this way, even if the image data input via a common input bus varies in the processing amount of each processor, it can be distributed by feedback using the multi-stage switch circuit, and the load among the processors can be evenly distributed. can be converted into Therefore, the processing power of the processor is
The processing amount can be reduced to about the average processing amount for the entire image data.

〔Example〕

An embodiment of the present invention will be specifically described below with reference to the drawings.

In addition, in all the times for explaining the example.

Identical elements are given the same reference numerals, and repeated explanations will be omitted.

FIG. 1 is a block diagram showing the configuration of main parts of an image processing apparatus according to a first embodiment of the present invention.

In FIG. 1, reference numerals 1 to 8 indicate processor elements (hereinafter abbreviated as PE) of each processor that performs image processing. 20 is an input bus, 30 is an output path, and 40 is a multistage switch circuit. 41a to 41d, 42a to 42d,
43a to 43d are switch circuits of elements constituting the multistage switch circuit 40, and are 2×2 unit switches. P
Image data is input to and output from EI to PE8 via an input bus 20 and an output bus 30. Each PE has an input bus 20. It is connected to a multistage switch circuit 40 by an input/output port different from the output path 30.

FIG. 2 is a time chart illustrating the operation of the image processing apparatus shown in FIG. As shown in the time chart, one frame of image processing data is formed from n blocks of data and a vertical blanking interval. Also, one block of data is assigned to one PE and input to each PE via the input bus 20. For example, a processor's PEI takes in block 1, then 1
Perform the next processing. The primary processing divides one block into several subblocks, calculates the difference between each subblock and the pixel value of the previous frame, and if that value is smaller than a certain threshold, it is determined to be invalid. If so, it is determined to be valid. For invalid sub-blocks, subsequent secondary processing is not necessary, and the data is used when creating a video frame within the PE. For valid subblocks,
It is given the number of the PE (R1+1 in this case) and sent to the multistage switch circuit. In a multi-stage switch circuit, for valid sub-blocks for which only the primary processing has been completed,
It is autonomously controlled to route to an appropriate PE.

For example, in each 2×2 unit switch of the elements of the multi-stage switch circuit, one of the two output ports is selected at random, and the valid sub-block that has undergone only the primary processing is sent to the selected output port. With such control, a PE that has received a valid subblock for which only primary processing has been completed will perform secondary processing. This secondary processing is, for example, encoding processing such as vector quantization, and normally requires an extremely large amount of processing. Upon receiving the sub-block requested for secondary processing via the multi-stage switch circuit, the PE that has performed the secondary processing attaches a flag indicating this state to the sub-block when the secondary processing is completed, and performs the multi-stage processing again. Send to switch circuit. In this case, in the multi-stage switch circuit, the P
According to the E number, it is routed to the PE in charge of the primary processing. As a result, the PE that has received the valid subblock for which the secondary processing has been completed (in this case, the PE number is "1"),
A video frame is assembled using the sub-blocks and output to the output bus 3.

In this way, the multi-stage switch circuit operates so that the secondary processing is performed by another processor, so for example,
In the case of image data such as a video conference, the effective sub-blocks are about 30% of the total, but when looking at each block, there are many variations ranging from almost 0% to close to 100%. Therefore, if dynamic load distribution using a multi-stage switch circuit is not performed, all PEs need to have the ability to process 100% of the sub-blocks. However, 1
In this embodiment, since the above-mentioned operation is performed, only valid sub-blocks are distributed to PEs, so each I'E only needs to have a processing capacity corresponding to the effective rate of the sub-block, and each The processing power required by the PE can be reduced.

FIG. 3 is a block diagram showing the configuration of essential parts of an image processing apparatus according to a second embodiment of the present invention.

In FIG. 3, 1 to 8 are processor elements (PE) of each processor that performs image processing, 20 is an input bus, 30 is an output bus, and 40 is a multistage switch circuit. 4
1a ~ 41d, 42a ~ 42d, 43a
43d is a switch circuit of an element constituting the multi-stage switch circuit 40, and is a 2×2 unit switch. P.E.I.
Input and output of image data to and from PE8 are performed via input bus 20 and output bus 30.

Each PE has an input bus 20. It is connected to a multistage switch circuit 40 through an input/output port different from the output bus 30. These elements are similar to those in the image processing device of the first embodiment. Here, a processor control circuit 50 is further provided. This processor control circuit 50 is
Controls load distribution for each processor element.

In this way, the image processing apparatus of the second embodiment.

Furthermore, with respect to the image processing device of the first embodiment (FIG. 1),
The configuration includes a processor control circuit 50 that centrally controls each processor element.

FIG. 4 is a time chart illustrating the operation of the image processing apparatus of the second embodiment.

As shown in this time chart, in the image processing apparatus of the second embodiment, the image processing of each processor element is performed up to the primary processing.

The image processing apparatus operates in the same manner as the image processing apparatus of the first embodiment.

After that, if a certain sub-block is valid as a result of the primary processing in each PEI to PE8, the processor control circuit 50 receives the minimum load PE number sent from the processor control circuit 50, and receives its own PE number and the minimum load PE number. A number is assigned to the subblock and sent to the multistage switch circuit 40. In this case, each PE1 to PE8 always notifies the processor control circuit 50 of the amount of load, and the processor control circuit 50 sends out the PE number with the minimum load based on this result.

On the other hand, when the multi-stage switch circuit 40 receives a valid sub-block for which the primary processing has been completed, the multi-stage switch circuit 40 routes the sub-block in accordance with the PE number of the minimum load.

The PE that receives the sub-block performs secondary processing,
Thereafter, the secondary-processed subblock data is sent to the multistage switch circuit 40 in the same manner as in the first embodiment. The subsequent processing is the same as in the first embodiment, and 2
The sub-block that has completed its next processing is routed to the PE that was in charge of its primary processing. When the secondary processing data is obtained, the PE performs the process of creating a video frame and outputs the result to the output bus 30. As a result, the output bus outputs the image data that has undergone image processing. be done. In this second embodiment, the processor control circuit 50 ensures that the effective sub-block is always set to P with the minimum load.
Since the data is routed to E, the overall load is balanced. Therefore, the required processing power in each PE is as follows.

It may be further reduced.

FIG. 5 is a block diagram showing an example of a unit switch circuit used as a unit switch of a multi-stage switch circuit. In FIG. 5, the configuration of the first stage unit switch circuit is shown in - boat fishing. In FIG. 5, 61 is an input buffer on the port 1 side, 62 is an input buffer on the port 2 side, and 63 is an input buffer on the port 2 side.
is a 2X2 switch.

64 is an output circuit on the port 1 side, and 65 is an output circuit on the port 2 side. 66 is an output control circuit, 67 is a comparator, 51
is the 1st stage group load information memory, 52 is the (i+1) stage switch load information memory on the port 1 side, and 53 is the port 1 side
(i+1) stage switch load information memory on the side; 54 is a selector; 55 is a latch circuit on the port 1 side.

56 is a latch circuit on the port 2 side.

FIG. 6 is a diagram illustrating the operating principle of a multistage switch circuit using the unit switch circuit shown in FIG. 5. In FIG. 6, 70a to 70h are 0th stage unit switch circuits, 71a to 71h are 1st stage unit switch circuits, and 72a
~72h is the second stage priority switch circuit, 73a~73h
is the third stage unit switch circuit. These unit switch circuits are the unit switch circuits shown in FIG.

In FIG. 6, the unit switch circuit 7 in the third stage is
Q, the load of 3a to 73h. ,Q□1. ...,Q,
7, the routing control of this multistage switch circuit calculates the load Q30+Q3L of the third stage unit switch circuits 73a to 73h based on the load information of each unit switch.
l ””r Q3? but.

Try to make them as equal as possible.

The concrete explanation of this control operation is as follows.6
The i-th stage unit switch circuit shown in FIG. Information [This (i+1
) Stage load information] is maintained and updated for each output port. For example, in FIG. 6, the first-stage m-position switch circuit 71f is connected to the third-stage unit switch circuits 73e and 73f as subordinate connection switches that can be routed.

It has 73g and 73h. In addition, as load information of the connection switch connected to output port 1 and output port 2 of this unit switch circuit 71f, that is, 2nd stage load information, 3.
and 4. This second stage load information is stored in the (i+1) stage switch load information memories 52 and 53 in the unit switch circuit of FIG. In the unit switch circuit, the comparator 67 controls the selector and stores the smaller value among the values in the (i+1) stage switch load information memories 52 and 53 in the 1st stage group load information memory 51. Then, the stored value is sent out from the first stage group load information memory 51 as the load difference information of the first stage switch. Further, the output control circuit 66 compares the values of the (i+1) stage switch load information memory 52.53 and outputs the 2×2 switch 63.
control and route to the direction with smaller load. Therefore, the primary processed image block data held in the input buffer 61 or the input buffer 62 is outputted to the one with the smaller load via the output circuit 64 or the output circuit 65.

At this time, the latch circuits 55 and 56 simultaneously send new load difference information to the routed unit switch circuit. Thereby, the increase in load can be notified to the routed unit switch circuit in the next stage.

When the unit switch circuit receives an image block for which secondary processing has been completed, the routing is performed by
The processing is performed according to the PE number of the next process, and the load difference information is transferred in the same manner as described above.

Through such control, image blocks that have undergone primary processing are routed to the PE with the least load, thereby achieving overall load distribution.

FIG. 7 is a block diagram showing another example of a unit switch circuit used as a unit switch of a multi-stage switch circuit. In FIG. 7, the configuration of the first stage unit switch circuit is shown in the case of boat fishing. In Fig. 7, 63 is a 2X2 switch, 64 is an output circuit on the port 1 side, and 65 is a port 2 switch.
This is the side output circuit.

66a is an input/output control circuit, 67 is a comparator, 51 is a 1-stage group load information memory, and 52 is (i+1) on the port 1 side.
Stage switch load information memory 53 is (i+
1) Stage switch load information memory, 54 is a selector, 55
56 is a latch circuit on the port 1 side, and 56 is a latch circuit on the port 2 side. These structures are similar to the unit switch circuit shown in FIG. This configuration differs from the unit switch circuit of FIG. 5 in that there is no input buffer. Another point is that an input/output control circuit 66a is provided instead of the output control circuit. The input/output control circuit 66a connects request lines (REG, R
EG') has an acknowledgment line (ACK, ACK'). The multi-stage switch circuit has two modes: a mode for transferring image blocks and a mode for making routing settings.If any PE among PEI to PE8 wants to send an image block, the corresponding PE will use the request line. R
Request using EQ' to enter routing setup mode. In each unit switch circuit, upon receiving a request from the request line REQ, the (i+1) stage switch load information memory 5
2.53 and comparator 67, the 2×2 switch 63
Unless the output port is in use, set the routing to the output port with the lower load. When the routing setting is performed in the final stage unit switch circuit, an acknowledgment BACQ' is sent.
is used to transfer the confirmation signal to the 0th stage. Only when the confirmation signal from the access line ACQ' reaches the sending processor that sent the request does it enter the mode of transferring image blocks. Even in this case, the first stage group load information memory 51, the (i+1) stage switch load information memory 52.
53. Since the load information is transferred using the latch circuits 55 and 56, the routing setting with the minimum load is performed, and the overall load is distributed.

Although the present invention has been specifically explained above based on the examples, 9
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As described above, according to the present invention, even if there is variation among blocks regarding the processing amount of image data input through a common bus, it can be distributed through feedback using multistage switches, and Load can be equalized. Therefore, the processing power of the processor is 1
There is an advantage that the processing amount can be reduced to about the average processing amount for the entire image data.

[Brief explanation of the drawing]

1 is a block diagram showing the configuration of main parts of an image processing apparatus according to a first embodiment of the present invention; FIG. 2 is a time chart explaining the operation of the image processing apparatus shown in FIG. 1; 1 is a block diagram showing the configuration of main parts of an image processing apparatus according to a second embodiment of the present invention; FIG. 4 is a time chart illustrating the operation of the image processing apparatus according to the second embodiment; The figure is a block diagram showing an example of a unit switch circuit used as a unit switch of a multi-stage switch circuit, and FIG. 6 is a diagram explaining the operating principle of a multi-stage switch circuit using the unit switch circuit shown in FIG. FIG. 7 is a block diagram showing another example of a unit switch circuit used as a unit switch of a multi-stage switch circuit. FIG. 8 is an explanatory diagram showing an example of a multiprocessor image processing apparatus having a plurality of processors. In the figure, 1 to 8... processor elements, 11.1
2゜13...Processor, 20...Input bus, 30
...output bus. 40-...Multi-stage switch circuit, 41a to 41d
, 42a-42d. 43a to 43d... Unit switch circuit, 50... Processor control circuit, 61... Input buffer on port 1 side, 62... Input buffer on port 2 side, 63...
2x2 switch. 64...Port 1 output circuit, 65...Port 2
Side output circuit, 66... Output control circuit, 66a...
Input/output control circuit, 67... Comparator, 51... 1-stage group load information memory, 52... Port 1 side (i+
1) Stage switch load information memory, 53...(i+1) stage switch load information memory on the port 2 side, 54...Selector, 55...Latch circuit on the port 1 side, 56...
・Latch circuit on port 2 side. 70a to 70h... 0th stage unit switch circuit, 71
a~71h...first stage unit switch circuit, 72a~
72h...Second stage unit switch circuit, 73a to 73
h...Third stage unit switch circuit.

Claims (4)

[Claims] (1) A multi-stage switch circuit consisting of one input bus, one output bus, a plurality of processors connected to the input bus and the output bus and performing image processing, and a plurality of 2×2 switches; An image processing apparatus comprising: path means for connecting intermediate processing results of each processor to each other processor via the multistage switch circuit. (2) Each of the plurality of processors that performs image processing is provided with a means for receiving image data from an input bus and sending out processed image data to an output bus, and is also provided with a means for transmitting processed image data to an output bus, and to an intermediate point in the middle of processing in the first stage of the multistage switch circuit. The image processing apparatus according to claim 1, further comprising means for transmitting image data as a result of processing and receiving image data in the middle of processing from the final stage of the multistage switch circuit. (3) In the image processing apparatus according to claim 1, after each processor performs primary processing on the image data received from the bus input port connected to the input bus, the self-processor The address is assigned and the primary processed image data is output to the multistage switch circuit via the switch output port connected to the multistage switch circuit, and the multistage switch circuit routes the primary processed image data to an arbitrary processor. The processor receives the primary processed image data through the switch input port.
After performing the secondary processing, it is output to a multi-stage switch circuit, and the multi-stage switch circuit routes the secondary-processed image data to the processor that performed the primary processing according to the above address, and the processor then outputs the secondary-processed image data. A method for controlling an image processing device, the method comprising: transmitting the image to an output bus via a bus output port. (4) The image processing apparatus according to claim 1, further comprising a processor control circuit that detects the processing load state of each of the plurality of processors and selects a processor, and the processor control circuit controls the multistage switch. An image processing device characterized in that a circuit controls primary processed image data to be routed to a processor with the least load.