JPH01310475A - Element arranging automatic preparing method at the time of circuit diagram - Google Patents

Abstract

PURPOSE:To eliminate a useless idle area and to increase the accommodation rate of elements by taking into consideration not only a wiring area in the later direction of the element but also that in the longitudinal direction when the elements are arranged. CONSTITUTION:When position relation in the lateral direction of the element is deter mined, for the element having no input terminals, the number of logical stages are set at 1, and the level connected to the element is set at 2. A number L of the logical stages of the elements, whose signal levels connected to the input terminal are all determined, is made into the maximum of the level. By successively determining the number L of the logical stages of the elements and the signal level, the numbers of the logical stages of the all elements are obtained. The number of the logical stages to be a standard is determined based on a prescribed rule, and the position relation in the longitudinal direction of the elements in the same number of the logical stages is determined based on the prescribed rule. When elements (a) to (d) cross, the arrange ment of the element is altered so as not to cross by the position of the number of the terminals of the elements in the all stages. The elements connected to the elements in the number of the reference logical stages are arranged (sorted) so that signal lines may not cross.

Description

[Detailed description of the invention] [R required] Paper of a certain size (
For example, regarding the method of arranging elements in J3 when automatically drawing a circuit diagram on △2 version or A3 version 8), the purpose is to eliminate unnecessary empty space and increase the element accommodation rate. Input the element graphic information and connection information, and determine the horizontal position of the element according to the flow of signal lines. Determine the i relationship, determine the vertical positional relationship of the elements so that the signal lines do not intersect for each logic stage number of the element, and when the vertical and horizontal positional relationships of the elements are determined, start from the top. The configuration is such that the elements are arranged while maintaining the wiring area.

[Industrial Application Field] The present invention is useful for automatically drawing circuit diagrams on paper of a certain size (for example, A2 size, △3 size, etc.) based on element shapes and connection information. This relates to a method for arranging elements during automatic creation.

In recent years, systems that automatically create circuit diagrams have been in the spotlight. In this case, the arrangement of the element J3 in the circuit diagram is
It is necessary to place it in the position that is considered to be the best depending on the connection relationship between the elements, and the wiring area I to draw the best signal line.
4 things need to be taken into account.

[Prior Art] FIG. 11 is a flowchart showing an example of a conventional method for arranging elements when automatically drawing a circuit diagram. First, input the graphic information and connection information of the element. Step 1) If the entire circuit cannot fit on one sheet of paper, divide it into pieces that fit on the sheet (Step 2). Next, the locations for arranging the elements are determined based on the connections between the elements. If it does not fit on the paper, divide the circuit further and place the elements (Step 3)
.

Next, step/1. connect the wiring between the elements. )
, create a circuit diagram (step 4). In addition, step 3
5 shows processing for each circuit diagram.

Conventionally, in order to secure the wiring area, as shown in FIG.
J, a wiring area was secured around the uni element 1. In the figure, the mesh area is the vertical wiring area 2b, and the hatched area is the horizontal wiring area 2a.

1a and 1b are connection terminals of the element 1, respectively.

In this manner, in the conventional method, areas 2a for wiring are secured in the direction of the terminals connected to each element according to the number of terminals. Also, there is a certain area 2 even in the direction where there is no terminal.
b was secured, and other elements were not placed in that area.

The reason why the wiring area 2b is secured also in the vertical direction is that, as shown in FIG. 13, there is a case where the wiring is routed from the first stage to the second stage and then to the third stage. Among the wirings from element ■, wiring c1. The wire c2 is connected to the element (2), and the wire c3 is wired to the element (2).This wire C3 skips the second stage and is directly connected to the third stage. Therefore, it is necessary to secure a wiring area in the vertical direction such as the interval a and the interval C as shown in the figure.

FIG. 14 is a flowchart showing the conventional processing procedure for element arrangement. First, a region for wiring each element is determined (step 1), and the lateral positional relationship of the elements is determined based on the flow of signal lines (step 2). This order corresponds to the number of logic stages, and the leftmost element is the element with the number of logic stages of 1.

Next, the vertical positional relationship of the elements is determined so that the signal lines do not intersect for each logic stage number (step 3). Once the arrangement between the elements has been decided, arrange the elements in the vertical and horizontal sort (arrangement) order starting from the top of the paper while maintaining the wiring area (
Step 4).

[Problems to be Solved by the Invention] As described above, an element has a wiring area not only in the horizontal direction but also in the vertical direction. However, when the elements are connected as shown in FIG. is wasted. Moreover, for this reason, the element (■) exceeds the paper storage range (Δ). In this way, when the number of elements exceeds the storage range of the paper, there is a problem that the paper must be divided into a plurality of sheets.

The present invention has been made in view of the above-mentioned problems, and provides a method for arranging one cable when automatically creating a circuit diagram, which can eliminate unnecessary empty areas and increase the element accommodating rate.
, is intended to cover the following.

[Means for Solving the Problems] FIG. 1 does not show the principle of the method of the present invention, but is a flow chart. The present invention requires the following steps: step 1) to input the graphical information and connection information of the elements; step 2) to determine the horizontal positional relationship of the elements according to the flow of signal lines; The vertical positional relationship of the elements was determined (step 3), and once the vertical and horizontal positional relationships of the elements were determined, the elements were placed from above while maintaining the wiring area (step 4). It is characterized by

[Operation] The vertical positional relationship of the elements is determined so that the signal lines do not intersect for each logic stage number of the elements. In other words, when the wiring area 2b in FIG. 12 is required, the elements are
As shown in FIG.
Next, the vertical inner region 2b is not set as a wiring area for all elements, but is set as a wiring area only when connecting elements as described above. As a result, the wiring area in the vertical direction of the element can be minimized, and wasteful empty space can be eliminated, thereby increasing the element accommodating rate.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

The case shown in FIG. 15 will be explained as an example.

(1) First, the wiring area of each element is determined. The wiring area is set in accordance with the number of terminals in the direction in which the element is drawn out. FIG. 2 is a diagram showing the wiring area (horizontal direction) of each element. The area indicated by the broken line in the figure is the area occupied by the element, and the area indicated by the diagonal line is the wiring area. The width of this wiring area is proportional to the number of terminals.

(2) Determine the lateral positional relationship of the elements. As shown in FIG. 3, an element without an input terminal has a logic level of 1, and the level of No. 13 connected to this element is 2. The maximum level value is equal to the number of logic stages of the elements in which all the levels of the signals connected to the input terminals are determined. For example, the second stage
In this case, all inputs are level 2, and the number of logic stages is 2.

On the other hand, in the case of element (2), a signal of level 2 and a signal of level 3 are included, and its logic stage @L takes the larger of 2 and 3, that is, 3, and has a logic stage number of 3. in this way,
The number of logic stages of all elements is determined by sequentially determining the number of logic stages of the elements and the signal level. FIG. 4 is a diagram showing the number of logic stages of each element determined in this manner.

(3) The number of logic stages that is equal to the reference is determined based on a predetermined rule, and the vertical positional relationship of elements having the same number of logic stages is determined based on the predetermined rule. Here, the reference logic stage number is set to 1, and the elements ①, ②, ② are arranged in this order. An example of rules for determining the vertical positional relationship is shown in FIG. element a
- When d intersects as shown in (a), (b)
In order to accommodate this, the arrangement of the elements is changed so that they do not intersect depending on the number of terminals of the elements in all stages.

(4) Arrange (sort) the elements connected to the elements of the reference logic stage number so that the signal lines do not intersect. FIG. 6 is a diagram that does not show examples of the arrangement (b) where the signal @ lines intersect and the arrangement where they do not intersect.

(5) Determine the order in which elements are arranged starting from the top of the paper according to a predetermined rule. Here, the elements are arranged in the order of ■■■■■■■ (see FIG. 2) (6) The elements are arranged in accordance with the above order. Since the element ■ is an element with a logical stage number of 1, the leftmost already arranged m]! i! Step r1.
Place it just below the 1st chord ■.

Since the wiring C3 is connected to an element with three logical stages, the wiring area is secured so that signal lines can be drawn out from the terminals as precisely as possible. Next, when placing and covering the element (1), avoid the wiring area (shaded area) and place it from below (FIG. 7). Finally, the arrangement results as shown in FIG. 8.

FIG. 9 is a diagram showing the effect of the present invention. It can be seen that the conventional arrangement as shown in (a) has been changed to the arrangement as shown in (b), and that there is more room in the downward direction. Therefore, the element accommodating rate also increases.

FIG. 1o is a diagram showing an example of a system configuration for implementing the present invention. In the figure, 1 is a CPU that performs various controls for generating circuit diagrams, 2 is a main memory connected to the CPU 1, 3 is a secondary 1fi device in which created circuit diagram information, etc. is stored; 7 is an output device for outputting the created circuit diagram, and 8 is a bus that connects these components. As the secondary Ie1 device 3, for example, a magnetic disk device is used, and as the output device 6, for example, a printer is used.

[Effects of the Invention] As described in detail above, according to the present invention, by considering not only the horizontal direction of the device but also the vertical wiring area when arranging the device, wasted free space can be eliminated. J when automatically creating a circuit diagram that can increase the element accommodation rate
3. A method for arranging a G-shaped cord can be provided.

[Brief explanation of the drawing]

Figure 1 is a flowchart showing the principle of the method of the present invention, Figure 2 is a diagram showing the arrangement area of each element, Figure 3 is a diagram showing the method for determining the number of logic stages, and Figure 4 is the number of logic stages of each element. FIG. 5 is a diagram showing an example of a rule for determining the vertical position i relationship. FIG. 6 is a diagram showing an example of an arrangement in which the signal @ lines intersect and an arrangement in which they do not intersect. 8 is a diagram showing the wiring state between elements, FIG. 9 is a diagram showing the effects of the present invention, and FIG. 10 is a diagram showing an example of a system implementing the present invention. FIG. 11 is a flowchart showing an example of a conventional device arrangement method, FIG. 12 is a diagram showing the wiring area set for the element, FIG. 13 is an explanatory diagram of providing the wiring area in the vertical direction, and FIG. 14 is a flowchart t showing the conventional processing procedure for element arrangement.
・-FIG. 15 is a diagram showing the arrangement of conventional elements. In Figure 10, 1 is cpul, 2 is memory, 3 is secondary storage, and 7 is output! 8 is the bus. Patent Applicant Fujitsu Ltd. Ceremony Attorney Patent Attorney Fuji Ijima (1 person) The present invention ■ Flowchart showing the principle Figure 1 Figure 4 (a) (b) Rules for determining the trend Φ position relationship Prison island 5 showing
Figure (a) Example of an arrangement where the signal lines intersect and an arrangement where the signal lines do not intersect. Figure 7 shows the arrangement sequence of 0 elements. Figure 8 shows the effect of the present invention. Fig. 9 Fig. 10 Conventional snoring ■ Arrangement method ■ - Flowchart showing elevation j Kakuyu 11 Fig. 12 Adhering to the tertiary domain also in the trend Flowchart No. 14 showing the Enru procedure
Figure 15

Claims (1)

[Claims] Input the graphic information and connection information of the element (step 1), and determine the horizontal positional relationship of the element based on the flow of signal lines (
Step 2), determine the vertical positional relationship of the elements so that the signal lines do not intersect for each logic stage of the element (step 3), and when the vertical and horizontal positional relationships of the elements are determined, A method for arranging elements when automatically creating a circuit diagram, characterized in that the elements are arranged while maintaining the wiring area from the side (step 4).