JPH01309566A - Picture processor - Google Patents

Abstract

PURPOSE:To respectively and separately execute color conversion for all the parts of picture data except an outline part and that for the outline part by equipping the title device with a converting means to convert the color of an input picture into a designated color according to the combination of the detected result of a first detecting means and that of a second detecting means. CONSTITUTION:A CPU100 stores data necessary at the time of color decision and the color conversion through an I/O port 103 into the plural registers of a color deciding and color converting circuit 105 according to a control program stored in a ROM101. Further, an area generating circuit 104 generates an area signal 111 based on a coordinate value inputted from a digitizer 106 and outputs the generated area signal 111 to the color deciding and color converting circuit 105. Namely, the prescribed color part of the input picture is detected, the outline part of the prescribed color part is detected, and the color of the input picture is converted into the designated color according to the combination of these detected results. Thus, the color conversion for the outline part of the picture data, the color conversion for all the parts of the picture data except the outline part, further, the color conversion for an area, for which prescribed color conversion is to be executed, etc., can be executed separately.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device that can detect the outline of input image data and perform specified color conversion.

[Prior Art] In recent years, digital color copying has become popular, in which color originals are digitally separated into colors and read, desired processing is applied to the read digital image signals, and color copies are recorded based on the obtained digital color image signals. The device is becoming more and more popular. This type of device is shown in FIG.
The image signal read by the CD is converted into a digital signal by an A/D converter, and the digitized image data is processed such as color masking, undercolor removal, and 1-gradation correction.
Efforts have been made to reproduce the colors and level of detail that are faithful to the manuscript. Furthermore, recently, digital color image copying apparatuses have been proposed that are equipped with simple image editing functions such as color image cropping and moving composition. On the other hand, along with such high-definition and multifunctionalization, in addition to the above-mentioned color image editing, there is also an increasing demand for a color conversion function that replaces image data in a specific color area of a document with another color.

[Problem to be solved by the invention] However, when color conversion is performed using the methods and devices proposed so far, the color of the character part of the document with the black character "A" as shown in FIG. 13 is changed to black. Even if an attempt is made to change the color to red and the outline portion 1450 to yellow as shown in FIG. 14, the color of the outline portion 1450 will also be changed to red. Therefore, if it is desired to convert the character portion 1440 to red and the outline portion 1450 to yellow as shown in FIG. 14, the only way is for the operator to draw the outline portion 1450 with a yellow colored pen or the like.

The present invention has been made in view of the above-mentioned conventional example, and it is an object of the present invention to provide an image processing device that can detect the contour line portion of image data and independently perform color conversion on the portion other than the contour line and the contour line portion. purpose.

[Means for Solving the Problems] In order to achieve the above object, an image processing apparatus of the present invention has the following configuration. That is, a first detection means for detecting a predetermined color portion of an input image, a second detection means for detecting an outline of the input image, and a detection method according to a combination of the detection results of the first and second detection means. and converting means for converting the input image into a specified color.

Further, the predetermined color is specified from the outside.

[Operations] In the above configuration, the first detection means detects a predetermined color portion of the input image, and the second detection means detects the outline of the input image. Thus, these first and second
The input image is converted into a designated color according to the combination of the detection results of the detection means.

Further, the invention described in the other claims operates such that the predetermined color is specified from the outside.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Description of Image Processing Apparatus (FIG. 1)] FIG. 1 is a block diagram showing a schematic configuration of an image processing apparatus according to an embodiment.

In the figure, 100 is a CPU that controls the entire device, 101 is a ROM that stores cputoo's control program and various data, and 102 is used as a work area for cPUloo as well as temporary storage of image data and various data. This is a RAM that performs 103 is area generation circuit 1
04, color judgment/color conversion circuit 105, etc., on the system bus 11.
This is an I10 port that connects to 0. A digitizer 106 specifies the position and area of image data, and is connected to the bus 110 via a serial interface section 107. 104 and 108 are respectively a contour generation circuit and a contour extraction section which will be described later, 100' is input image data, and 101' is output image data.

The CPU 100 follows the control program shown in the flowchart of FIG. 15 stored in the ROM10I.
Data necessary for color judgment and color conversion is stored in I10 boat 1.
03 to multiple registers of circuit 105 (described later).
Store it in Further, the area generation circuit 104 generates an area signal 111 based on the coordinate values input from the digitizer 106.
is created and output to the color judgment/color conversion circuit 105.

[Description of Area Signal Generating Circuit (FIG. 2) FIG. 2 is a diagram for explaining the operation of the area generating circuit 104.

The area referred to here is, for example, the shaded area 20 in FIG. 2(E).
This refers to the ARE timing chart shown in the timing chart of Figure 2 (E) for each line in the sub-scanning direction, or in other words, for each horizontal synchronization signal (H3YNC).
It is distinguished from other areas by a signal like A. Note that such an area is designated by the digitizer 106.

FIGS. 2(A) to 2(D) show a configuration in which the generation position of the area signal, the length of one section, and the number of sections are programmable by the CPU 100 and can be obtained in large numbers. In this configuration, one tree area signal is constituted by one bit of RAM that can be accessed by the CPU 100. For example, in order to obtain n tree area signals AREA1 to AREAn, as shown in FIG.
As shown in D), each RAM2 has an n-bit configuration.
1.22.

Now, the area signal AREAI as shown in FIG. 2(B)
.about.AREAn, the addresses χ1. Set bit 0 of χ3 to “1°°,” and set all bits 0 of the remaining addresses to “o.” - On the other hand, set bit (n-1) of address 1.χ1°χ2.χ4 of RAM21 and 22 to 1. '' and set all bits (n-1) of other addresses to "°0".
”.

When the data in RAMs 21 and 22 is read out sequentially in synchronization with a constant clock using the HSYNC signal 27 as a reference, for example, as shown in FIG. 7(C), at addresses χ1 and χ3, Data ゛1”
° is read. This read data is shown in Figure 2 (
D) It is inputted to both terminals of the n number of J- shown by 28-1 to 28-n to J of the flip-flop. Therefore, the output of each flip-flop has a toggle operation, i.e., RA
When 1" is read from M21 (22) and VCLK is input, the outputs of these flip-flops become "0°" →
``1'', changes from ``1'' to ``o'', and as shown in Figure 2 (C
) is generated. Furthermore, if the data is set to 0° across all addresses in the RAMs 21 and 22, no area section will occur and no area will be set.

In addition, in order to switch the area section at high speed, for example, RA
While data is being read line by line from the MA21, the CPU 100 performs a memory write operation to set a different area in the RAM22.
21 and 22 alternately to output the area signal and C
Switch memory writing from PU100.

Therefore, if you specify the shaded area shown in Figure 2 CF),
RAM (A) 21 and RAM like A-B → A → B-A
(B) 22 is switched, which means that in FIG. 2 (D), if (C3, C4, C3) = (0, 1, O),
The output of address counter 30 counted by VCLK is given to RAM 21 through selector 31 as address 25 of RAM 21 .

Also, at this time, the gate 32 is open and the gate 33 is closed, and n-bit data is read from the RAM 21.
The n J- signals are input to flip-flops 28-1 to 28-n. In this way, AREAI depending on the set value
~AREAn interval signals are generated.

Also, writing from the CPU 100 to the RAM 22 during this period is performed via the address bus A-BUS and the data bus B.
-BUS and access signal R/W 34.

Conversely, when generating a section signal based on the data set in the RAM 22, (C,,c4°Cs)" (
1,0,1), the gate 33 is opened and R
The output of the address counter 30 is input to the address 26 of the AM 22, and the n-bit data read from the RAM 22h) is sent to n flip-flops 28-1 to 28-n.
Output to. In this way, the flip-flop can be inverted by VCLK and a region signal can be output as in the case of the RAM 21. Also, at this time, A-Bus and B-B
Data can be written from the CPU 100 to the RAM 21 via the US.

[Description of the contour extraction section 108 (FIGS. 3 and 4)] FIG. 3 is a block diagram showing a schematic configuration of the contour extraction section 108 shown in FIG. 1.

This figure shows a contour extraction circuit 36 for color separation data R (red data), a contour extraction circuit 37 for color separation data G (green data), and a contour extraction circuit 3 for color separation data B (blue data).
8, an OR gate 39 which takes the logical sum of RGB contour information 44-46, and timing adjustment circuits 40-43.

Here, the color separation data of the three colors is delayed by passing through timing adjustment circuits 41 to 43 in order to synchronize with a delay occurring in a color detection circuit, which will be described later. Actually, since the timing is delayed by one line here, these timing adjustment circuits 41 to 43 can be easily realized with a FIFO memory or the like having a memory capacity for one line. Next, the output delayed by one line is input to contour extraction circuits 36-38.

The configuration of these contour extraction circuits 36 to 38 is shown in FIG.

In FIG. 4(A), numerals 50 and 51 each indicate a FIFO memory that delays the input image data by one line, and sequentially inputs the image data 49 and returns the write and read positions to the initial positions by the H5YNC signal. Among these outputs, 52 is image data of the line of interest, 53 is image data of the line immediately before the line of interest, and 49 is image data of the line after the line of interest. 54 is an inverter circuit;
55 is an adder, and 56 is a D type flip-flop. A multiplier 59 multiplies each of the image data 52 of the line of interest by four and inputs the result to the adder 55. 57 is C
A register 58 stores a threshold value which is a reference value for determining whether it is a contour based on PUIQO, and a register 58 compares the value of the register 57 with the output value of the adder 55 at the final stage, and outputs a signal (44) indicating that it is an area. ~46).

Write clock (WCK) for FIFO memories 50 and 51
and the lead clock (RCK) are the timing adjustment circuit 4.
The same clock as that used in 1 to 43 is used, and the write set signal (WRST) and read reset signal (RR3T) are the horizontal synchronization signal H3YNC.
Use the inverted signal of . As a result, as mentioned above, 52
．． 53 are image signals delayed by one line each.

FIG. 4(B) is a diagram showing calculation of the filter realized by the circuit of FIG. 4(A), and contour information is extracted by comparing the calculation result with a set threshold value.

61 in Figure 4 (A) is the numerical value ゛4 shown in Figure 4 (B).
62 indicates the image data multiplied by ``゛■
) shows image data that has been subjected to the calculation of ■+■. Furthermore, data 52 indicates the data calculated by ■ in FIG. 4(B), and 63 indicates the result of calculation by ■ in FIG. 4(B). Adding. As a result, the calculation using the filter shown in FIG. 4(B) is executed, and the fourth
The comparator 58 is the multiplication result by the filter in Figure (B).
It is compared with the value of the register 57 to determine whether it is a contour, and if it is a contour, 1° is output.

Note that the plurality of flip-flops 56 in FIG.
The timing is adjusted by delaying the pixel data, and the inverter circuit 54 performs the multiplication by '-i'.

Returning to FIG. 3 again, to explain the configuration of the contour extraction section 108, the outputs 44 to 108 of the contour extraction circuits 36 to 38 are
46 is input to the OR circuit 39. And here R
, G, and B signals are determined to be contours, O
The output of the R circuit 39 becomes "1", and it is determined that the pixel of interest is a contour portion. It should be noted that the timing adjustment circuit 40 is also used to adjust delays occurring in the color detection circuit described later, similar to the timing adjustment circuits 41 to 43 described above. This is composed of, for example, a D type flip-flop, and actually provides a delay of about 10 clocks.

[Description of Color Judgment/Color Conversion Circuit 105 (FIGS. 5 to 11)] Next, the color judgment/color conversion circuit 105 will be explained with reference to FIGS. 5 to 11.

First, to explain the outline of the color judgment algorithm, for the same color (certain hue), for example, there is a red (R) signal, a green (G) signal, and a blue (B) signal (hereinafter referred to as R, , G, , B).
, are known to have the same ratio. Therefore, the data MC of one of the colors to be converted (hereinafter referred to as the maximum value color, hereinafter referred to as the principal color) is selected, and the ratio between it and the data of the other two colors is determined. For example, when the main color is R, G+
Find /MC, B, /MC. and input data RI,
For Gl and B+, R1×(G, /MC)xα, ≦GI ≦RI X (G, /MC)Xa2 R+ X (B+ /MC)xβ1≦Bt≦R+
(B+ /MC)xβ2 A≦MC≦B However, here α1. β1≦1, α2. β2≧1, O≦A
A pixel for which ≦B≦255 is satisfied is defined as a pixel to be color-converted.

FIG. 5 is a block diagram showing a schematic configuration of the color determination section of the color determination/color conversion circuit 105, which detects pixels to be color converted.

In this figure, 66 are 8-bit R, G,
A smoothing section 67 inputs the B data and smoothes each data. A selector 67 selects one of the outputs (principal color) of the smoothing section 66. 6'8 is a selector that selects either the output value of the selector 67 or the fixed value R8, and 69 is the output value of the selector 67 and the fixed value G.
0, and 70 is the output value of the selector 67 and the fixed value B. This is a selector that selects one of the following.

71 is a decoder that determines which of R, G, and B is the primary color; 72
74 are OR circuits, and 76 to 81 are multipliers for calculating the respective upper and lower limit values. 82 to 84 are upper limit ratio registers, and 85 to 87 are lower limit ratio registers, in which numerical values are set by the CPU 100 via the bus 110.

90 to 92 are window comparators, 94 is a converted pixel detection section, and 95 is a block processing section.

The operation in the above configuration will be explained.

One of the 8-bit data R'G' and B' data obtained by smoothing the R, G, and B data by the smoothing section 66 is selected by the selector 67 and output by the 2-bit select signal 96 set by the CPU 100. do. In this way, the main color data is selected. Here, OR
Circuits 72-74 create select signals for selectors 68-70, respectively.

Here, Ro, Go, and Bo are selected when they are the main colors in conventional color conversion (fixed color conversion) and gradation color conversion, and the main color data that is the output of the selector 67 is the main color in gradation color conversion. Selected when the color is other than . The operator can freely set this selection from an operation section (not shown). In addition, the CP
It is also possible to change under the control of U100.

R', G', and B are determined by the outputs of these selectors 68 to 70, upper limit ratio registers 82 to 84, and lower limit ratio registers 85 to 87 set by CPUl00, respectively.
' are calculated by the respective multipliers 76 to 81, and the respective window comparators 9
Set between 0 and 92.

In the window comparators 90 to 92, R'
, G', and B' are within a certain ratio, that is, whether the data of the main color is within a predetermined range.If it is within the range, 1°° is output. Based on the outputs of these comparators 90 to 92, the converted pixel detection 1i94
It is determined whether the pixel is a color conversion pixel or not. This converted pixel detection section 94 is basically composed of an AND circuit, and when the outputs of the comparators 90 to 92 are all 1, data "1" is output to the block processing section 95. Finally, in the block processing unit 95, if even one pixel is detected as a color conversion pixel within a 3×3 block centered on the pixel of interest, processing is performed to consider the pixel of interest as a color conversion pixel.

FIG. 6 is a block diagram showing the configuration of the smoothing section 66.

In this figure, 120 and 121 each delay image data by one line; FIFO 1122 is a flip-flop that delays data by one clock; 123 is an adder that inputs and adds the output values of each flip-flop 122;
124 is a multiplication unit that multiplies the output value of the addition unit 123 by 1×9. Here, the write clock WCK of FIFO 120, 121 and the clock RC are common to other clocks, write reset WR3T and read reset RR3.
T is performed using an inverted signal of the horizontal synchronizing signal H3YNC.

This smoothing section 66 performs 3x3 smoothing on each of the input data R1G and B, and outputs R1G and B.
', G', and B' are output.

Specifically, (d, +d2+d3+d4+d5+d6+
The calculation d7+d8÷69+)x(t/9) is performed, where d and -d indicate the values of each pixel in the 3x3 pixel matrix. Note that 125 is image data of one line ahead, 126 is image data of the line of interest, and 127 is image data of one line before. Further, d5 is pixel data of interest.

FIG. 7 is a diagram showing the circuit configuration of the converted pixel detection section 94.

In FIG. 7, 130 to 132 are exclusive OR circuits;
134 is a selector, 135 to 137.139 are AND gates, and 140 to 142.144 are OR gates.

With the above configuration, each of the outputs 94-1 to 94-3 of the window comparators 90 to 92 of the color determination section in FIG. Output through circuit 144. In other words, it is a circuit that outputs 0.degree. when the R:G:B ratio is in a certain ratio and the primary color data is within a certain value, and 0.degree. when not.

The operation of this converted pixel detection section 94 will be explained in detail below.

To explain in the case of the EXOR circuit 130, cp[110
Mode signal 146 and EXOR circuit 13 set to 0
0 serves to invert or not invert signal 94-1. That is, when the mode signal 146 is 0, the signal 94-1 is output as is, and when the mode signal 146 is 1, the signal 94-1 is inverted and output. Similarly, the mode signals 147 to 1 set by the CPU 100
48 and EXOR circuits 131 to 132 also function similarly.

The area signal 111 is selected as the select signal 1 by the selector 134.
55, it is converted into either high active or low active to become area signal 150. This area signal 150 is sent to AND circuits 135-137.

In this way, the area signal 150 is used here to make use of or kill the output of the previous stage. In other words, this circuit performs color conversion when specifying an area, and sets whether to convert the color within the specified area or output the original color as is.

Next, to explain the role of the OR circuit 140, the CPU 10
The inhibit signal 151 output from 0 via the bus and the OR circuit 140 determine whether or not to output the signal output from the AND circuit 135 to the next stage. in particular,
When the inhibit signal 151 is 1°, the output of the OR circuit 140 is 1° regardless of the output of the AND circuit 135. Similarly, prohibition signals 152 to 1 set by the CPU 100
53 and OR circuits 141 to 142 are also OR circuit 1.
It works in the same way as 40.

Further, the OR circuit 144 is a circuit for detecting colors other than a certain color within the area. Selector 145 and select signal 1
56 selects either the AND circuit 139 or the OR circuit 144 and outputs it as a converted pixel detection signal 157.

These mainly make it possible to detect the following parts.

(1) Detecting a certain color in the entire area.

For example, when detecting red letters "A" and "E" in Fig. 8, all mode signals and mode signals 146 to 148 should be set to "0'°.
Make it.

The prohibition signal and prohibition signals 151 to 153 are all set to "0°".

The area signal 150 is Pa1'' in all sections.

Selector 145 selects the output of AND circuit 139.

At this time, the red letter "A" and "AND in the 81 part"
The output of the circuit 139 becomes 1°, and the selector 145 outputs 1°.

(2) Detecting colors other than a certain color in the entire area.

For example, in FIG. 8, characters other than red characters "A" and "E" are detected.

All mode signals and mode signals 146 to 148" 1
”

Prohibition signal - All prohibition signals 151 to 153 are "o"
Make it.

The area signal 150 is 1° in all sections.

The output of the selector 145 selects the output of the OR circuit 144.

(3) Detecting a certain color by specifying an area. For example, the 8th
Detect the red letter "A" within the rectangle indicated by the dotted line in the figure.

Area signal 150: Set to 1° within the rectangle, and set to "o" in other areas.

mode signals 146 to 148, prohibition signals 151 to 153,
Selection by the selector 145 is made in the same manner as in case (1).

(4) Detecting colors other than a certain color by specifying an area.

For example, the red letter r in the rectangle indicated by the dotted line in Figure 8
Detect other than AJ.

The area signal 150 is set to 1'' within the rectangle, and set to ``1'' in other areas.
0".' Mode signals 146 to 148, prohibition signals 151 to 153,
The selection by the selector 145 is the same as in case (2).

(5) Detecting a certain color by specifying outside the area.

For example, a red character "E" outside the rectangle indicated by a dotted line in FIG. 8 is detected.

The area signal 150 is set to 1° outside the rectangle and is set to 0'° outside the rectangle.

mode signals 146 to 148, prohibition signals 151 to 153,
The selection by the selector 145 is the same as in case (1).

(6) In FIG. 8, designate outside the area and detect anything other than the red letter "E" outside the rectangle indicated by the dotted line.

The area signal 150 is set to "1°" outside the rectangle, and set to 0° in other areas.

mode signals 146 to 148, prohibition signals 151 to 153,
The selection by the selector 145 is the same as in case (2).

(7) Selecting funds within the area.

Set the upper and lower limit values of the window comparator to 0° each.
', so that it becomes "255", RoG.

Set Bo and the upper limit of each value.

The area signal 150 is set to 1° within the rectangle and 0'° in other areas. .

Mode signal: All mode signals 146 to 148" o
”

Prohibition signal: Prohibition signals 151 to 153 are both set to 0''.

(8) Select everything outside the area.

The region signal 150 is set to 0° within the rectangle indicated by the dotted line, and set to "1" in the other regions.

The value of the window comparator, mode signal, and prohibition signal are the same as in case (7).

In this way, many types of color signals can be detected, allowing a wide range of image processing (e.g. amorphous masking, etc.)
can be done.

FIG. 9(A) is a block diagram showing the configuration of the block processing section 95.

In this figure, 160 and 161 are FIFos that each delay the image data by one line, and 162 are flip-flops provided in the circuit that each delay the data by one clock. Here, the control method for FIFOs 160 and 161 is as shown in FIG.
20 and 121, their explanation will be omitted.

This block processing unit 95 inputs the converted pixel signal 157, and when even one pixel in a 3×3 pixel block is determined to be a color converted pixel, it processes the pixel of interest in that block as a color converted pixel. □There is. Specifically, Figure 9 (B)
As shown in , the data from one line before is converted to al-1+
al, al+1 + notable line data bH-1
, b(,t)1+1, Cr-
+ + + + C1++ binding, when the pixel of interest is bl, al-1+ al + a l+l 1b
l-+ + bl w 1) I+I + Cl-1+
If even one pixel among CI + cl++ is determined to be a color conversion pixel portion, that pixel of interest b1 is set as a color conversion pixel. In other words, when the pixel of interest b1 is determined to be a color conversion section, processing is performed in which everything within a 3x3 block centered on the pixel of interest is regarded as a color conversion section.

FIG. 10 is a block diagram showing the configuration of the color conversion circuit of the color determination/color conversion circuit 105.

For this portion, a color-converted signal or an original signal is selected according to the output 98 of the color determination section and the output Sc of the contour extraction section 108.

In this figure, 170 is a timing adjustment circuit, 171
-173 are selectors; 174-176 are registers that store color separation data of converted colors of pixels that are color detection colors and are not contour areas; 177-179 are registers that store color separation data of converted colors of pixels that are color detection colors and are not contour areas; This is a register that stores color separation data.

The timing adjustment circuit 170 delays the 8-bit color separation data R, G, and B signals by the number of lines delayed by the smoothing section 66 and block processing section 95 of the color determination section. Specifically, each of the R, G, and B signals is delayed by two lines and more than ten clocks using a FIFO having a capacity for one line.

Either through data or color conversion data is selected by the selectors 171 to 173. Next, the selection signal 180 will be explained. This is created by a circuit as shown in FIG.

In FIG. 11, 181 to 183 are selectors, and selectors 182 and 183 are 8 when the selection input 188 is 1".
When the input is "O", select the A input. Next, the output signals 185 and 186 in each mode and the output signals 171-1 to 173-1 shown in FIG. 10 will be described. There are three main modes as shown below. In addition, 1
85 is MS81 of the select signal 180 shown in FIG.
186 is the LSB of the select signal 180.

■A mode in which color conversion is performed for pixels that are a detected color and are not an outline, and pixels that are a detected color and are an outline.

Register 184 → “00” (A input selection) Selector 1
81 output 188 → “°0 path selector 182 output 18
5→A input (SR) Output 186 of selector 183→A input (So) Here, SB is the output of the block processing section 95, S
c is the output of the contour extraction unit 108.

As a result, the selectors 171 to 173 in FIG.
Pixels whose value 76 is the detection color and which is the outline are selected by the values in registers 177 to 179, and for others, the through data of A and 8 inputs are selected and output, and expressed in that color.

■A mote that performs color conversion only on pixels that are detected colors and are not on outlines.

Register 184 → '01'' (B input selection) Selector 1
Output 188 of 81→B input selector 182 and 183 output is "°'oo" when both SR and S are °1°, otherwise output of selector 182 is S81 selector 18
The output of 3 becomes Sc.

As a result, pixels of colors detected by selectors 171 to 173 in FIG. 10 that are not contour parts are expressed by values in registers 174 to 176, and other pixels are expressed by through data.

■A method that converts only the pixels that are detected colors and outlines.

Register 184 → “10” (C input selection) selector 18
1 output → C input selector 182.183 output is Sc when SB is “1”
is 0”, 00°゛, otherwise selector 18
2 outputs SB, and selector 183 outputs Sc.

As a result, selectors 171 to 173 in FIG.
Pixels that are detected colors and outlines are stored in registers 177 to 179.
, and other values are expressed as through data.

As described above, the operator can freely select one of the three modes.

[Explanation of CPU control operation (Fig. 15)] Fig. 15 is a flowchart showing various data setting operations of the CPU 100 of the embodiment, and the control program that executes this processing is R.
Stored in OMl0I.

First, in step S1, gradation color determination/fixed color determination and gradation color conversion/fixed color conversion are selected, and here the selector signal S
2 (fixed color → 1, gradation → 0) is determined. In step S2, a threshold value for determining the contour portion is set in the register 57 (FIG. 4(A)) of the contour extraction section 108. Then, in step S3, when the color data before conversion is inputted by a digitizer or the like, in the case of gradation color determination, the process proceeds from step S4 to step S5, in which the main color (maximum value color) determination and the Color data number (C+, co is red (R) is the main color → 00, G is the main color → 01, B is the main color →
10) is set in the decoder 71 (FIG. 5). As a result, the decoder 71 selects the selector 68 corresponding to each color.
-70 selection signals 72R, 73G, and 74B are created.

Once the primary color is determined, the ratio between the primary color and the other two colors is calculated in step S6, and primary color data is further set in R, G, B, in step S7. In step S9, the ratios of the primary color data and the other two color data that have already been determined are each multiplied by a certain constant, and the calculation results are set in the respective upper limit ratio and lower limit ratio registers 82-84 and 85-87. Note that the value of the main color data is set in the main color data register so that it falls within an appropriate range. For example, when R is the main color, Ro, the upper limit ratio, and the lower limit ratio are set so that the lower limit value and upper limit value of the window comparator 90 are "'20" and "255°," respectively.

An example of the values set in each register when R is the main color is as follows.

γ2→Register 82 γ1→Register 85 G Sada/MC・α2→Register 83 GI/MC・α1→Register 86 B+/MC・β2→Register 84 B,/MC・β1→Register 87 In this way, in step S10, the digitizer etc. The converted color data is input. In step S11, color data (R, G, B) which is the contour part and the conversion part is set,
In step S12, the color data (R, G, B
) settings. In this way, in step 513, mode signals 146 to 148, prohibition signals 151 to 153, and selection signal 156 are set, and data setting to all selectors and registers is completed.

[Embodiment 2] In the above-mentioned embodiment, R, G, and B were input in parallel, but next, an embodiment will be described in which R, G, and B are input in serial.

FIG. 17 is a diagram regarding main signals in the serial system. AVE is a signal indicating that the video signal of the entire section is valid, VE is a video signal valid signal of one line, and HS is a signal output on a new line (the beginning of the IH section). VCLK is video clock, C5ELI, C5ELO
are signals obtained by dividing the video clock VCLK by two and four, respectively. VD is a video signal selected by C3ELI and C3ELO, R, G, B, X (X is
For example, the brightness information obtained by (R+G+B)/3) is read in color sequentially.

FIG. 16 is a block diagram of color conversion processing in a serial system according to the second embodiment.

In FIG. 16, 191 is serial image data 190
192 is a 1-line delay section that delays the center image data that is not smoothed by 1 line. 194 is an outline extraction circuit, and 193 is a color determination/color conversion circuit that performs color determination and color conversion. Reference numeral 196 denotes a buffer memory necessary for, when a central pixel is detected to be a color conversion pixel as shown in FIG. 9, all 3×3 blocks centered on that pixel to be used as a color conversion section.

Next, each component will be explained, but most of the parts are the same as those of the previous embodiment. Therefore, we will mainly explain the differences, that is, the parts related to the processing of serial image data.

FIG. 18 is a block diagram showing a specific example of the contour extraction circuit 194.

In the figure, 200 is a contour processing circuit, 201 is a D type flip-flop, and 202 is a timing adjustment circuit. This contour extraction circuit 194 corresponds to the contour extraction section 108 shown in FIG. 3 of the above-described embodiment, and the difference from FIG. 3 is that four flip-flops 201 for converting serial data into parallel data It is at the point where it is set up.

The contour processing circuit 200 also has the same configuration as the contour extraction circuits 36 to 38 shown in FIG. 4(A).

Here, it is determined whether or not the pixel of interest is an outline portion.

19 and 20 are block diagrams showing the configuration of the color determination section of the color determination/color conversion circuit 193.

210 are D-type flip-flops, which are serially connected to input four types of data to the selector 211.
Parallel conversion is performed and a delay is applied to ensure synchronization. 211 is a selector, 212 is a register in which the CPU sets a fixed value via a lotus, and 220 is a comparator that notifies the timing at which the main color data is sent.

213 is a selector for selecting fixed color or primary color data; 21
4 is a register for setting four types of upper limit ratios, 215
2 is a register for setting a lower limit value, and 216 and 217 are multipliers that perform multiplication to determine an upper limit value or a lower limit value using the primary color and the above register, respectively. Comparators 218 and 219 check whether each signal is within the upper limit value and lower limit value, respectively. Comparators 218 and 21
The output of 9 is input to the subsequent logic circuit, and various color portions are detected by various multiplications (corresponding to FIG. 4 in the above embodiment).

FIG. 20 shows the latter part of the color determination section into which the output results of FIG. 19 are input.

Here, 230 is a D flip-flop that inputs VCLK and performs serial/parallel conversion to check whether each of the four types of data falls within a certain range.
1 is a judgment invalidation selection signal that determines whether to use or kill each result. 232 is an AND circuit that outputs a signal indicating whether the pixel is a color conversion pixel or not. Furthermore, if the central pixel is a color conversion section, FIF0234, 235.9 D flip-flops 2 perform block processing (see Figure 9) in which all 3x3 blocks centered on that pixel are treated as color conversion pixels.
It has 36 and 9 OR circuits 237. Then, based on the data 238, it is finally determined whether the pixel is a color conversion pixel.

The difference from the first embodiment described above lies in the presence of a serial-parallel converter, and in this embodiment,
Flip-flop 210 and selector 211 (Figure 19)
, flip-flop 230, OR circuit, AND circuit 23
The difference is that a second flip-flop 233 (FIG. 20) is added.

A flip-flop 210 and a selector 211 convert four types of serial signals into parallel signals, and a select signal 221 selects a main color from among these four types of signals.

Furthermore, in order to check whether each of the four types of serial signals falls within a set range, each of the four types of serial signals is converted from serial to parallel using a flip-flop 230, etc., and it is determined whether the pixel of interest is a color conversion pixel or not. .

FIG. 21 is a block diagram of the color conversion section.

250.251 corresponds to 185.186 in Figure 11,
This controls the output of the selector 252. Further, in the registers 253 and 254, one register is selected from among the data stored in the four registers by a clock 255 obtained by dividing the frequency of VCLK. This data is controlled so that the same type as the image data is selected and input to the selector 252. The other parts are the same as those in the first embodiment described above, so their description will be omitted.

The advantage of such a serial system is that when it is made into hardware, it requires fewer gates than a parallel system.
Most processing systems use the image clock (VCLK here)
For example, it is slower.

C3ELO', C3EL in Figures 18 to 21
I'', C3ELO°', C3ELI'''
, csELO'", C3ELI°", C3E
LO” ”, C3ELI ′”', C3ELO°
``'' and C3ELI゛'°° have the same frequency as C3ELO1C3ELI shown in FIG. 14, but are out of phase.

[Example 3] In the above-mentioned example, detection was performed based on the color (principal color) having the maximum value among the color separation data of the detected color, but a color detection method based on the sum of color separation data as a reference This can also be achieved using . In this case, the basic block diagram is exactly the same as that in FIG. 1, and it is only necessary to replace FIG. 5 with FIG. 22.

FIG. 22 is a block diagram of a color judgment detection section that functions as described above.

In the figure, 260 is a smoothing unit, 261 is a ratio calculation circuit, 262 to 264 are registers for setting the upper limit ratio of color separation data R, G, and B, and 265 to 267 are registers for setting the lower limit ratio. CPU
set via the bus. 268 to 270 are window comparators, 271 is a converted pixel detection unit, 271
is a block processing section. - The color separation data R, G, and B are first smoothed by the smoothing section 260 shown in FIG. 9, respectively. And these output results R', G', B'
Next, the ratio calculation circuit 261 performs the following three calculations. Specifically, a circuit configuration as shown in FIG. 20 is adopted.

R'R"r=X256R' + G' + B' p 'R' + G' + B' where R' + G' + B' is the output value 284 of the adder 283.

The calculations in the division/multipliers 280 to 282 are performed using, for example, R
This can be realized by using OM. Ratio R,”,Gr
", Br" is the next stage three window comparators 2
In steps 68 to 270, it is determined whether the following three conditions are satisfied.

Rr-≦R, "≦Rr+ Gr-≦Gr"≦Gr+ Br-≦B, "≦B r+ Conversion pixel detection is performed only when the above conditions are satisfied and the area signal 111 is °°1" The output of the unit 271 becomes °″1°°.Finally, the block processing unit 272 (same as in FIG. 9) performs processing to perform detection up to the boundary with other colors, and the detection result SB is converted into a color. Selector control section (11th
Figure).

As explained above, according to this embodiment, if there is a document as shown in FIG. 3(A), the outline of a certain color,
Image data as shown in FIG. 3(B) can be obtained by color-converting each portion independently, such as a portion excluding the outline of a certain color. As a result, color〇HP
It is particularly effective when applied to text areas, such as creating and emphasizing titles. Furthermore, since the mode can be selected independently for each area, it can be widely applied to minute calculations such as graphic design.

[Effects of the Invention] As described above, according to the present invention, there is an effect that color conversion can be performed independently on the outline portion of image data, the portion other than the outline portion, and furthermore, the area where a predetermined color conversion is performed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the schematic configuration of the image processing device of the first embodiment, Fig. 2 (A) to (F) are diagrams for explaining the operation of the area generation circuit, and Fig. 3 is contour extraction. FIG. 4(A) is a circuit diagram of an outline extraction circuit, FIG. 4(B) is a diagram showing an example of a filter, and FIG. 5 is a block diagram showing a schematic configuration of the color determining section of the first embodiment. 6 is a circuit diagram of the smoothing section, FIG. 7 is a circuit diagram of the converted pixel detection section, FIG. 8 is a diagram for explaining the color detection mode, and FIG. 9 (
A) is a block diagram showing the configuration of block processing, FIG. 9(B) is a diagram showing the relationship between the pixel of interest and peripheral pixels, FIG. 10 is a block diagram showing the configuration of the color conversion circuit of the embodiment, and FIG. 10 is a diagram showing an example of a circuit that generates a select signal that controls the selector of the color conversion circuit shown in FIG. 10. FIG. 12 is a diagram showing an example of image processing in a conventional digital color copying apparatus. FIGS. 13 and 14 15 is a flowchart showing the operation of the CPU in the first embodiment, and FIG. 16 is a block diagram showing a schematic configuration of the image processing device in the second embodiment. , FIG. 17 is a timing diagram showing the operation of main signals in the second embodiment, FIG. 18 is a block diagram showing the schematic configuration of the contour extraction circuit in the second embodiment, and FIG. 19 is a timing diagram showing the operation of the main signals in the second embodiment. FIG. 20 is a block diagram showing the configuration of the first half of the color determination section in the second embodiment; FIG. 21 is a block diagram showing the configuration of the second half of the color determination section in the second embodiment; FIG. 21 is the color conversion in the second embodiment. FIG. 22 is a block diagram showing a schematic configuration of the color determining section in the third embodiment, and FIG. 23 is a block diagram showing a schematic configuration of the color determining section in the third embodiment. FIG. 2 is a block diagram illustrating the configuration. In the figure, 40-43...timing adjustment circuit, 36-3
8... Contour extraction circuit, 66... Smoothing section, 6
7-70...Selector, 90-92...Window comparator, 94...Conversion pixel detection section, 95...
Block processing unit, 100・CPU, 101・ROM, 1
02...RAM, 103...bow 10 boats, 104...
...area generation circuit, 105...color judgment/color conversion circuit,
106... Digitizer, 107... Serial I/F
, 10B...contour extraction unit, 109...memory, 11
1... Area signal, 170... Timing adjustment circuit,
191...Smoothing unit, 193...Color judgment/color conversion circuit, 194...Contour extraction circuit, 196...Memory, 200...Contour processing circuit. Patent Applicant Canon Co., Ltd. Agent Patent Attorney Yasunori Inuzuka (and 1 other person) 1 sentence'

Claims (2)

[Claims] (1) A first detection means for detecting a predetermined color portion of an input image, a second detection means for detecting an outline of the input image, and a combination of detection results of the first and second detection means. An image processing apparatus comprising: conversion means for converting the input image into a specified color according to the input image. (2) The image processing apparatus according to claim 1, wherein the predetermined color of the input image is a color specified from an external source.