JPH01308066A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To suppress the instability of a threshold value voltage due to the compensation of an impurity by completely controlling the formation of N<+> type and P<+> type gates by a single impurity. CONSTITUTION:An SiO2 layer 1F is formed on an element isolation region on an n-type Si substrate 1. Then, an SiO2 layer is formed on the whole substrate, and an undoped polysilicon layer 3 to become a gate and a PSG layer 9 to become an implantation mask are grown thereon. The layers 3 and 9 are patterned, and a laminated pattern of a gate 3P and the layer 9P and a laminated pattern of a gate 3N and the layer 9N are formed on the gate forming section of each FET. A resist pattern 10 opened with a P<+> type gate FET forming region is formed, with it as a mask it is etched to remove by etching the layer 9P on the laminated pattern and an SiO2 layer 2 of the exposed part. Then, a resist pattern 10 is removed. An SiO2 layer 2A is formed on the whole substrate, and with the laminated pattern of the gate 3P, the gate 3N and the layer 9N as a mask R<+> for forming source, drain regions is implanted to the n-type substrate through the layer. An interlayer insulating layer PSG layer 6 is grown on the whole substrate. Then, it is heat treated, and phosphorus is diffused from the layer 9N to the gate 3N.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Fig. 4) Problems to be Solved by the Invention Examples of Means and Effects for Solving the Problems (1) (Fig. 1) ) Embodiment (2) (Fig. 2) Embodiment (3) (Fig. 3) Effects of the invention [(Already required) Method of using an inter-S integrated circuit having gates made of n-type and p-type semiconductors!! Regarding.

The purpose of this invention is to suppress the instability of the threshold voltages of n° type and p' gate FETs, reduce their variations, and obtain a highly accurate reference voltage generation circuit.

A step of sequentially growing a gate insulating layer, a gate layer including at least an undoped semiconductor layer, and an injection blocking layer containing a -4 conductivity type impurity on a semiconductor substrate of one conductivity type, and patterning the gate layer and the injection blocking layer, -Conductivity type gate I'
f! A step of forming a laminated pattern of a gate and an injection blocking layer in each gate formation region of T and opposite conductivity type gate FET, and removing the injection blocking layer on the gate of one opposite conductivity type gate FET.

using the injection blocking layer on the gate of the 1-conductivity type gate FIET as an implantation mask, applying impurities of opposite conductivity type to the gate and the substrate of the 1-inverse 4-conductivity type gate FET to form source and drain regions of each FET; , and a step of diffusing one conductivity type impurity from the injection blocking layer to the gate of the one conductivity type gate PUT by heat treatment.

[Industrial application field]

Does the present invention have gates made of n-type and p-type semiconductors? The present invention relates to a method of manufacturing a jO3 integrated circuit.

MOS with a gate made of n-type and ρ-type semiconductors
FETs are used in reference voltage generation circuits such as analog integrated circuits (ICs).

This uses the difference between the threshold voltages of two Ft':T as a reference voltage, and if an n" type and p" gate FET is formed in the same channel, the n" type and p" type semiconductor Since the work function difference (constant value depending on the substance) can be set as the threshold voltage difference, it is possible to obtain a highly accurate reference voltage generation circuit that is independent of process variations.

In the following description, for convenience of explanation, the case of a p-channel FET will be taken as an example.

[Conventional technology]

FIGS. 4(1) to 4(5) are cross-sectional views illustrating, in order of steps, a conventional method of manufacturing an MO3 integrated circuit having a gate having four thicknesses of n-type and p-type.

In FIG. 4 (11), a silicon dioxide (SiO□) layer IF is formed by thermal oxidation as an isolation insulating layer in an element isolation region on an n-type silicon (n-Si) substrate l.

Next, Si was thermally oxidized as a gate insulating layer over the entire surface of the substrate.
An n2 layer 2 is formed, and undoped polycrystalline silicon (poly 5T) which becomes a gate is formed by vapor phase growth (CVD) on the n2 layer 2.
r/! Grow J3.

Next, a resist pattern 4 with an opening in the gate formation region of the +-type gate FET is formed, and using this as a mask, boron ions (Bo) are implanted into the poly-Si layer 3 as an n-type impurity.

Next, resist pattern 4 is removed.

In FIG. 4(2), a resist pattern 5 with an opening in the gate formation region of the n'' gate FET is formed.

Using this as a mask, phosphorus ions (P゛) are added as n-type impurities.
is injected into the poly-Si layer 3.

Next, resist pattern 5 is removed.

In FIG. 4(3), the poly-Si layer 3 is patterned using normal lamination, and the implanted impurity is activated and annealed to form a p' gate 3P and an n' gate 3N.

In FIG. 4 (4), a Si insulating layer is formed on the entire surface of the substrate.
, form layer 2A, pass through this layer, connect gates 1-3P and 3.
Using N as a mask, Bo for forming source/drain regions is implanted into the n-51M plate. The implanted impurities are indicated by dotted lines.

In FIG. 4(5), activation annealing of implanted impurities is performed to form ρ9 type source/drain regions IA, IB, and Ic.
.

form ID.

The above two activation annealing steps can also be replaced by a post-process heat treatment.

After that, a phosphosilicate glass (PSG) layer 6 is grown on the entire surface of the substrate by the CVD method as an interlayer insulating layer through a normal process.
Openings are made over each source/drain region.
) forming wiring 7;

[Problem to be solved by the invention]

As mentioned above, when manufacturing p-type and n-type gate MO5FETs with the same gate layer (including polySt, polycide, or a double layer of metal and polySi, etc.) 1 For example, the p-channel FIT of the above example In the case of.

During the ion implantation for forming the source and drain regions in FIG. 4(4), n-type impurities are implanted into the n-type gate 3N, so the threshold voltage of the 4-type gate 1-MOS FET is lower than the impurity impurity. becomes stable and individual F within and between wafers
There is a drawback that the variation in the ET threshold becomes large.

The reason for this is that impurities in single-crystal Si are completely compensated for, and the impurity with a higher doping amount exhibits stable conductivity, but in the case of poly-Si, the impurities injected into the grain boundaries are completely compensated for. This is thought to be due to instability due to no compensation.

The object of the present invention is to obtain a manufacturing process in which the formation of n-type and p-type agates can be completely controlled using a single impurity, thereby suppressing instability of the threshold voltage due to impurity compensation.

[Means to solve the problem]

The above problem can be solved by a step of sequentially growing a gate insulating layer, a gate layer including at least an undoped semiconductor layer, and an injection blocking layer containing an impurity of one conductivity type on a semiconductor substrate of one conductivity type, and a step of sequentially growing a gate insulating layer, a gate layer including at least an undoped semiconductor layer, and an injection blocking layer containing an impurity of one conductivity type, and the gate layer and the injection blocking layer. 9. Step of patterning to form a laminated pattern of a gate and an injection blocking layer in each gate formation region of one conductivity type gate FET and opposite conductivity type gate FHT; Then, using the injection blocking layer on the gate of one conductivity type gate FET as an implantation mask, impurities of opposite conductivity type are introduced into the gate of two opposite conductivity type gates I+ET and the substrate to form the source and drain regions of each FET. 1. A method for manufacturing a semiconductor device, comprising: forming an impurity, and diffusing an impurity of one conductivity type from the stopper layer (11) into the gate of a gate FET of one conductivity type by heat treatment.

Alternatively, a step of sequentially growing a gate insulating layer, a gate layer including at least an undoped semiconductor layer, and an injection blocking layer on a semiconductor substrate of one conductivity type, and patterning the gate layer and the injection blocking layer to form a -grip type gate. -1- Step of forming a laminated pattern of a gate and an injection blocking layer in each gate formation region of FET and opposite conductivity type gate PFT; , using the injection blocking layer on the gate of one conductivity type G1-I'ET as a mask, impurities of opposite conductivity type are introduced into the gate of five opposite conductivity type G1-FRT and the substrate to form the source and drain of each FET. forming a region and removing the injection blocking layer.

An interlayer insulating layer containing impurities of one conductivity type is deposited on the entire surface of the substrate,
A method for manufacturing a semiconductor device comprising the step of diffusing an impurity of one conductivity type from the interlayer insulating layer to the gate of a -m type gate FET by heat treatment, or a method for manufacturing a semiconductor device, comprising a step of diffusing an impurity of one conductivity type from the interlayer insulating layer to the gate of a -m type gate FET, or a method for manufacturing a semiconductor device comprising a step of diffusing an impurity of one conductivity type from the interlayer insulating layer to the gate of a -4 type gate FET; The process of sequentially growing gate layers containing layers and one opposite conductivity type gate 1-FET
A step of forming a diffusion prevention layer on the gate layer in the gate formation region of the gate FET, and applying impurities of one conductivity type to the gate layer by thermal diffusion using the diffusion prevention layer as a mask; forming an injection blocking layer on the gate layer in the gate formation region, patterning the gate layer using the injection blocking layer and the diffusion blocking layer as a mask to form a gate; and removing the diffusion blocking layer. 1. Impurities of the opposite conductivity type are added to the gate of the opposite conductivity type gate FET and the substrate, and each FE
This is achieved by a method for manufacturing a semiconductor device, which includes a step of forming a source/drain region of T.

[Effect]

In the present invention, phosphorus diffusion from PSG is used to form an n-type gate, and ion implantation of n-type impurities during source/drain formation is used to form a p+-type gate.

At this time, an injection blocking layer is formed on the n° type gate L to prevent impurity compensation from occurring (see Examples (11 and (2) below).

Furthermore, the formation of the n-type gate is performed by masking the +-type gate with an oxide film or the like and gas diffusion of n-type impurities, and the formation of the p-type gate is performed by forming an injection blocking layer on the n-type gate. ion implantation of n-type impurities at the time of forming the source and drain (see Example (3) below).

In the former method, the poly-Si layer for gate formation is patterned in an undoped state, so the poly-Si layer is patterned at one step, etc.
However, in the latter method, high concentration poly-Si formed by gas diffusion is buttered, so it has the advantage of being able to perform good buttering.

〔Example〕

Embodiment (1): Figures 1 (11 to 6) are cross-sectional views illustrating, in order of steps, a method for manufacturing a MOS integrated circuit having gates made of n° type and p+ type semicircular bodies according to an embodiment of the present invention. It is.

In FIG. 1 (11), a thick 5i02 layer IF is formed by thermal oxidation as an isolation insulating layer in the element isolation region of an n-3i substrate 1-h having a resistivity of 1 Ωcm.

Next, a 200-thick SiO□ layer 2 is formed as a gate insulating layer on the entire surface of the substrate by thermal oxidation, and on top of this, a 4,000-thick undoped poly-Si layer 3 that will become the gate and an implantation mask are formed by CVD. ps thickness of 3000 people
A c-layer 9 is grown.

In FIG. 1(2), the poly-Si layer 3 and the PSG layer 9 are patterned using normal lamination lithography.

A stacked pattern of the gate 3P and the 136th layer 9P and a stacked pattern of the gate 3N and the PSG layer 9N are formed in the gate forming portion of each FET.

In FIG. 1(3), a resist pattern 10 with an opening in the p-type gate FET forming region is formed, and using this as a mask, wet etching is performed using hydrofluoric acid to remove the upper 136 layer 9P of the laminated pattern and the exposed portion. Si02
Etch away layer 2.

Next, the resist pattern 10 is removed.

In FIG. 1 (4), SiO2 is used as an insulating layer on the entire surface of the substrate.
□N-
3+g is temporarily implanted for forming source/drain regions.

The ion implantation conditions are as follows: BF2 ions are used, the energy is 60 KeV, and the dose is 3E15 cm-2.

At this time, ions are implanted into the gate 3P.

The gate 3N is not implanted because the PSG layer 9N exists thereon as an injection blocking layer.

In Figure 1 (5), the thickness of one interlayer insulating layer is 8000 mm.
A CVD r'sG layer 6 is grown on the entire surface of the substrate.

Next, the temperature was heated to 1050°C, which also served as impurity activation annealing.
A heat treatment is performed for about 10 minutes to diffuse phosphorus from the PSG layer 9N to the gate 3N.

As a result, p' type source/drain regions IA, IB are formed.

IC, 10 is formed, the gate 3P becomes ρ' type and the gate 3N becomes n'' type.

In FIG. 1(6), a first wiring 7 is formed by opening above each source/drain region of the I'SG layer 6.

Example (2): FIG.
FIG. 2 is a cross-sectional view directly illustrating step 11 of a method for manufacturing an MO3 integrated circuit having a gate type and a p-type semiconductor.

In FIG. 2 (+,), an SiQ□ layer I is formed by thermal oxidation as an isolation insulating layer in the element isolation region on the n-3i substrate 1.
Form F.

Next, Si was thermally oxidized as a gate insulating layer over the entire surface of the substrate.
A 0g layer 2 is formed, and then a CVD method is used.

An undoped poly-Si layer 3 with a thickness of 4,000 thick serving as a gate and a SiJ layer 4 with a thickness of 1000 thick serving as an implantation mask■
Grow 1.

In FIG. 2(2), the poly-Si layer 3 and the 5iJn layer 11 are patterned using normal lamination lithography.

Each FI'iT (7) Day 1- Gate 3P and S in the formation part
Stacked pattern of i3N4 layer 11F' and gates 3N and S
A laminated pattern of layers i, N, and 11N is formed.

In FIG. 2(3), a resist pattern 10 with an opening in the ρ1 type gate FET formation region is formed, and using this as a mask, wet etching is performed using hot tantalum acid to form the two-layer Si3N4 layer 11r in the laminated pattern.

Then, the exposed portion of the SiO□ layer 2 is removed by wet etching using hydrofluoric acid.

Next, the resist pattern 10 is removed.

In FIG. 2 (4), SiO2 is used as an insulating layer on the entire surface of the substrate.
□ A layer is formed, and through this layer, B'' for forming a source/drain region is implanted into the n-3i substrate using the laminated pattern of gates 3P and 3N, Si, N, and layer 11N as a mask.

The ion implantation conditions were as follows: RF, ions were used, the energy was 60 KeV, and the dose was 3E15 cm-''.

At this time, ions are implanted into the gate 3P.

On the gate 3N, a 5iJn layer 11N is implanted Ifl
It is not implanted because it exists as a stop layer.

Next, the Si3N4 layer 11N on the gate 3N is removed.

In Figure 2 (5), the thickness of one interlayer insulating layer is 8000 mm.
A CVn PSG layer 6 is grown on the entire surface of the substrate.

Next, 1050"
C. Heat treatment is performed for about 10 minutes to diffuse phosphorus from the PSG layer 6 to the gate 3N.

As a result, ρ゛ type source drain jJT bi I
A, IB.

IC, 10 is formed, the gate 3P becomes p' type and the gate 3N becomes n' type.

In FIG. 2 (6), openings are made above each source/drain region of the PSG layer 6 and ^It! 'lc! Form cotton 7.

Embodiment (3): FIG. 3 (11 to (7)) shows a MOS having gates made of n-type and p-type semiconductors according to another embodiment of the present invention.
FIG. 3 is a cross-sectional view explaining a method for manufacturing an L-product circuit in order of steps.

In FIG. 3 (1), a thermally oxidized SiO
form.

Next, Si was thermally oxidized as a gate insulating layer over the entire surface of the substrate.
An O□ layer 2 is formed thereon by CVD.

An undoped poly-Si layer 3 with a thickness of 4,000 thick serving as a gate and an S:Oz layer I with a thickness of 2,000 thick serving as a diffusion mask.
Grow 2.

In Fig. 3 (2), S
The i02 layer 12 is patterned to leave the SiO□ layer 12P in the +-type gate forming area.

Next, using the 5-inz layer 12P as a mask, phosphorus, which is an n-type impurity, is diffused into the poly-Si layer 3 by gas diffusion to make the region other than the pear-shaped gate formation an n-type.

At this time, phosphorus has a layer resistance of approximately 60Ω/R during diffusion.

FIG. 3 (3) Niote, using the CvD method, the 5i02 layer 121' is covered and the entire surface of the substrate is coated with a thickness of 100 mm to serve as an implantation mask.
Grow 0 5iJn JFt13.

In FIG. 3(4), a resist pattern 14 is formed in the n-type gate formation region, and using this as a mask, the SiJ layer 13 is etched by ordinary dry etching.
i, N, leaving layer 13N.

Next, resist pattern 14 on Si, N4 layer 13N
remove.

In FIG. 3(5), the Si layer 121' and the Si layer are removed by dry etching using CF and O2 gas.
, N, using the layer 13 as a mask, the poly-Si layer 3 is patterned to form a gate 3P and a gate 3N.

Next, the 5i02 layer 12P is removed.

In FIG. 3(6), a Si insulating layer is formed on the entire surface of the substrate.
, a layer is formed, and through this layer, B for forming source/drain regions is implanted into the n-3i substrate using the laminated pattern of the gates 3P and 3N and the 5iJa layer 13N as a mask.

The ion implantation conditions were: BF2 ions were used, the energy was 60 Keν, and the dose was 31'! 15 cm-”.

At this time, ions are implanted into the gate 3P.

The gate 3N is not implanted because the 5iJa layer 13N exists thereon as an injection blocking layer.

Next, the Si3N4 layer 11N on the gate 3N is removed.

In Figure 3 (7), the thickness of the insulating layer between the two layers is 8000 mm.
A CVD PSG layer 6 is grown on the entire surface of the substrate.

Next, impurity activation annealing is performed at 1050°C.

Heat treatment is performed for about 10 minutes.

As a result, a p type source/drain region l^, In.

IC, 10 is formed, and the gates 1-3P become p' type.

The − side gate 3N has already become an n° type due to gas diffusion.

Next, an AI wiring 7 is formed by opening above each source/drain region of the psc layer 6.

In any of the above embodiments, the variation in threshold voltage is about ±0.05 V with respect to the center value.

This is significantly lower than the conventional level of about ±0.15 V.

In the embodiment, an n-channel FET has been described, but in the case of an n-channel FET, the same effect can be obtained simply by changing the conductivity type of the impurity, and the gist of the invention does not change.

〔Effect of the invention〕

As explained above, according to the present invention, n-type and p-type Age-1Fl'! The instability of the threshold voltage of T can be suppressed and its variations can be reduced, and a highly accurate reference voltage generation circuit can be obtained.

[Brief explanation of the drawing]

FIGS. 1 (1) to (6) are cross-sectional views illustrating the manufacturing method of a MOS integrated circuit having gates made of n° type and p° type semiconductors according to an embodiment of the present invention. Figures 2 (11 to 6) are cross-sectional views explaining step-by-step a method for manufacturing an MO3 integrated circuit having gates made of n-type and p-type semiconductors according to another embodiment of the present invention. -(7) are cross-sectional views illustrating, in order of steps, a method for manufacturing an MO5 integrated circuit having gates made of n-type and p-type semiconductors according to another embodiment of the present invention. 1A and 1B are cross-sectional views illustrating, step by step, a method for manufacturing an MO5 integrated circuit having gates consisting of n-type and ρ-type semi-dedicated gates according to a conventional example. In the figure, 1 is an n-Si substrate. 1F is an isolation insulating layer. 2 is a SiO□ layer which is a gate insulating layer. 3 is a poly-Si layer which becomes a gate. 6 is an interlayer insulating layer which is a psc layer n-3i substrate. 7 is a metal wiring. 9 is a PSG which is an injection blocking layer. layers. 10 and 14 are resist patterns. ICl3 is a Si, N layer that becomes an injection blocking layer. 12 is a SiO□ layer that becomes a diffusion mask (PtGa'rFE-D'l[,n
f Gate FE 11th 1ri・l(+)/)r side view [Pigue 1-FE 2] [Tile Nage Y F
E block]Actual direction a ike I (2)/) Cross-sectional view [P17-t FET) (n thousand caps)
1FF: 〔〔〔〕〕〕〕〕〕〕〕〕〕〕〕〕〕〕〕〕〕〕〕〕〕〕〕〕〕〕〕〕〕〕〕〕〔〕

Claims (3)

[Claims] (1) A step of sequentially growing a gate insulating layer, a gate layer including at least an undoped semiconductor layer, and an injection blocking layer containing an impurity of one conductivity type on a semiconductor substrate of one conductivity type, and patterning the gate layer and the injection blocking layer. forming a laminated pattern of a gate and an injection blocking layer in each gate formation region of one conductivity type gate FET and an opposite conductivity type gate FET; and removing the injection blocking layer on the gate of the opposite conductivity type gate FET. Then, using the injection blocking layer on the gate of one conductivity type gate FET as an implantation mask, impurities of opposite conductivity type are introduced into the gate of the opposite conductivity type gate FET and the substrate, and each FET is
A gate FET of one conductivity type is formed from the injection blocking layer through a step of forming a source/drain region and a heat treatment.
1. A method of manufacturing a semiconductor device, comprising the step of diffusing impurities of one conductivity type into the gate of the semiconductor device. (2) A step of sequentially growing a gate insulating layer, a gate layer including at least an undoped semiconductor layer, and an injection blocking layer on a semiconductor substrate of one conductivity type, and patterning the gate layer and the injection blocking layer to form a gate of one conductivity type. A step of forming a laminated pattern of a gate and an injection blocking layer in each gate formation region of the FET and the opposite conductivity type gate FET, and removing the injection blocking layer on the gate of the opposite conductivity type gate FET to form a one conductivity type gate. using the injection blocking layer on the gate of the FET as a mask, introducing impurities of opposite conductivity type into the gate of the opposite conductivity type gate FET and the substrate to form source and drain regions of each FET; and the injection blocking layer. and depositing an interlayer insulating layer containing an impurity of one conductivity type on the entire surface of the substrate, and diffusing the impurity of one conductivity type from the interlayer insulating layer to the gate of the one conductivity type gate FET by heat treatment. A method for manufacturing a featured semiconductor device. (3) A step of sequentially growing a gate insulating layer and a gate layer including at least an undoped semiconductor layer on a semiconductor substrate of one conductivity type, and forming a diffusion prevention layer on the gate layer in a gate formation region of a gate FET of an opposite conductivity type. , a step of introducing an impurity of one conductivity type into the gate layer by thermal diffusion using the diffusion blocking layer as a mask; forming an injection blocking layer on the gate layer in a gate formation region of the one conductivity type gate FFT; forming a gate by patterning the gate layer using the blocking layer and the diffusion blocking layer as a mask; removing the diffusion blocking layer and introducing impurities of the opposite conductivity type into the gate of the gate FET of the opposite conductivity type and the substrate; and each FET
1. A method of manufacturing a semiconductor device, comprising: forming a source/drain region.