JPH01306948A - Interface board - Google Patents

Abstract

PURPOSE:To process interruption from an input-output board having plural interruption generating factors without trouble even to a CPU board having no interruption acknowledge signal in its external bus by storing an interruption identifier in the memory of an interface board. CONSTITUTION:When an interruption request signal arrives from an input-output board 11, an interface board 12 returns an interruption accepting signal INTAC to the board from its own decision without inquiring a CPU board 10 about the propriety. Then an interruption identifier is sent to a data bus from the base plate 11 in response to the interruption accepting signal and the identifier is tentatively stored in a memory 13 in the board 12 in a state where the storing content of the memory 13 is accessible from the board 10. When the interruption identifier is stored in the memory 13 of the interface board 12 in such state, an interruption request signal is sent from the board 12 to the CPU board 10. As a result, the interruption identifier signal can be read from memory 13 of the board 12 from the CPU board 10 side.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides a system that is located between a CPU board and an input/output board,
This invention relates to improvements in bus conversion circuits that match both bus specifications.

(Prior Art) Fig. 2 is a block diagram showing the configuration of a microcontroller system using a conventional interface board, and shows only the minimum necessary for explaining the present invention. .

As shown in the figure, this type of microcontroller system includes a CPU board 10. It is composed of an input/output horn board 11 and an interface board 50.

The interface board 50 is provided to match the bus specifications of the bus 51 from which the CPU board 10 connects to the outside and the bus 52 to which the input/output board 11 outputs to the outside.

The CPU board 10 includes a microprocessor 53, an interrupt controller 541, an output buffer 55, and a memory and a clock (not shown in the figure).

It is equipped with a timer etc.

The interface board 50 includes a bus conversion circuit 56, a human output buffer 55, and the like to match the specifications of the buses 51 and 52.

Next, the operation when an interrupt occurs from the input/output board 11 in the microcontroller system having the above configuration will be explained.

(2) The input/output board 11 notifies the outside of the occurrence of an interrupt using the interrupt signal IRQ.

(2) The interrupt signal IRQ is input as an interrupt signal IRK to the interrupt controller 54 of the CPU board 10 via the interface board 50.

■ The interrupt controller 54 handles other interrupt signals IRO~
After checking the presence or absence of an interrupt input from IRn and checking the interrupt priority, it outputs an interrupt signal INT to the microprocessor 53.

■ The microprocessor 53 sends an interrupt signal 81 NT.
However, since the microprocessor 53 has only one interrupt input, the INT signal, the I
In order to identify which of the interrupts Ro to IRn it is, an interrupt recognition signal INTA is output.

■ When the interrupt controller 54 receives the INT'A signal, it interrupts itself (interrupt controller 1 - controller 5) according to information set in advance by the microprocessor 53.
4) is a mode for outputting an interrupt identifier (hereinafter referred to as mode 1) or a mode for outputting an interrupt identifier to the input/output board 11 (hereinafter referred to as mode 2).

Here, if the input/output board 11 has only a single interrupt factor, the interrupt controller 54 may be set to mode 1, but generally the input/output board 11 has multiple interrupt factors, and each Since the interrupt controller 54 has a function of outputting different identifiers for different factors, the interrupt controller 54 is normally set to mode 2 (here, it is also set to mode 2).

(2) The INTA signal is input to the input/output board 11 via the interface board 50 as an INTAC signal.

■ The input/output board 11 recognizes that the interrupt has been accepted by the microprocessor 53 by the INTAC signal, and
Outputs an interrupt identifier onto the data bus DBS.

° ■ The microprocessor 53 reads the interrupt identifier output to the data bus DB of the CPU board 10 via the interface board 50, and performs the corresponding interrupt processing.

Here, the bus 51 that the CPU board 10 outputs to the outside
If the interrupt recognition signal INTA is included in the interrupt recognition signal INTA, the microprocessor 53 can identify the interrupt cause generated from the input/output board 11, which has multiple interrupt generation causes, as described above. However, if there is a limit to the number of bus signals that the CPU board outputs to the outside, or if you use a CPU board that does not take into account the use of input/output boards that have multiple interrupt sources, An interrupt recognition signal INT is present in the bus.
A may not be included.

In such cases, conventional interface boards cannot support interrupts from input/output boards.

turn into.

(Problems to be Solved by the Invention) As described above, in the configuration of the conventional interface board, the CP
If the bus that the U board outputs to the outside does not include an interrupt recognition signal, it will not be possible to support interrupts from input/output boards that have multiple interrupt sources, and the microcontroller system will be incomplete. Put it away.

An object of the present invention is to provide an interface board that allows interrupt processing from an input/output board that has multiple interrupt generation factors to be performed without any problem even for a CPU board that does not have an interrupt recognition signal on an external bus. It's about doing.

[Structure of the Invention] In order to achieve the above-mentioned non-zero, the interface board of the present invention has a bus to be connected to the CPU board, a bus to be connected to the input/output board, and a bus between the two buses. A board that is equipped with at least a bus conversion circuit that matches bus specifications, and that makes independent decisions in response to interrupt request signals sent from the input/output board without making inquiries to the CPU board. A circuit that returns an interrupt recognition signal to the input/output board, a circuit that temporarily stores the interrupt identifier sent from the input/output board onto the data bus following the return of the interrupt recognition signal, and a circuit that returns an interrupt recognition signal to the input/output board.
a memory whose storage contents can be read from the PU board; and when an interrupt identifier is stored in the memory, the CP
This device is characterized by being equipped with a circuit for sending a -C interrupt request signal to the U board.

(Function) According to this configuration, when an interrupt request signal arrives from the input/output board, the interface board sends an interrupt recognition signal to the input/output board based on its own judgment without making any adjustments to the CPU board. It will be sent back.

Then, in response to this interrupt recognition signal, when an interrupt identifier is sent from the input/output board onto the data bus, this interrupt identifier is temporarily stored in the memory in the interface board, and at the same time the stored contents of this memory are can be read from the CPU board.

In this way, when the interrupt identifier is stored in the memory of the interface board, an interrupt request signal is sent from the interface board to the CPU board, and based on this, the CPU
On the U board side, the interrupt identifier can be read from the memory of the interface board.

(Embodiment) FIG. 1 is a block diagram showing the configuration of a microcontroller system using an interface board according to the present invention.

This microcontroller system uses C
PU board 10. Input/output board 1 with multiple interrupt generation factors
1 and an interface board 7 and a bus board 12 according to the present invention.

The interface board 12 is connected to the CPU board 10 by a bus 16, and the bus 16 receives an interrupt signal INT.
, data bus DB, address bus AB, control signal bus C
B, and does not include an interrupt recognition signal.

Data bus DB, address bus AB, control signal bus CB
are connected to the internal bus DB1 . of the interface board 12 via the buffer 55, respectively. A.B.I.

After becoming CBI, the input/output board 1 is connected to the bus conversion circuit 56.
Buffer 5 is converted to meet the specifications of bus 17 of
5 through DBS and ABS respectively.

It becomes a CBS and is connected to the input/output board 11.

Also, the internal data bus DBl of the interface board is F.
IFO (First In First Qut
) is connected to the data input terminal and data output terminal of the memory 13, and the internal address bus ABI is connected to the address decoder 18, and after the address is decoded, the FIFO
Connected to memory 13.

Further, a command signal within the internal control bus CBI is connected to the FIFO memory 13.

The interrupt signal IRQ output from the input/output board 11 is connected to the interrupt recognition signal generation circuit 14 via the buffer 55, and its output is connected to the 'interrupt recognition signal IN' via the buffer 55.
It is output to the input/output board 11 as a TAC, and is also connected to the write command generation circuit 19, and its output is connected to the FIF◯ memory 13.

The FIFO memory empty terminal of the FIFO memory 13 is connected to the interrupt generation circuit 15, and its output is outputted to the CPU board 10 via the buffer 55.

Next, the operation of the microcontroller system having the above configuration will be explained.

When the input/output board 11 generates an interrupt, the input/output board 11
An interrupt signal IRQ is output from the interface board 12, and this signal IRQ is input to the interrupt recognition signal generation circuit 14 of the interface board 12 via the buffer 55.

The interrupt recognition signal generation circuit 14 generates an interrupt recognition signal INTAC.
is output to the input/output board 11, and the write command generation circuit 19 is activated.

The important point here is that, unlike in the case of conventional interface boards, when returning the interrupt recognition signal INTAC, this is done based on its own judgment without making any timely arrangements with the CPIJ board.

The input/output board 11 receiving the INTCA signal sends an interrupt identifier onto the data bus DBS. This interrupt identifier is
Buffer 55. It appears on the internal data bus DBI of the interface board 12 via the bus conversion circuit 56.

Here, the write command generation circuit 19, which was activated earlier, gives a write command to the FIFO memory 13, and changes the interrupt identifier on the internal data bus DBI to the FIFO memory 13.
Store in FO memory.

This causes the FIFO memory to no longer be empty, so the FIFO
The output from the FO memory empty terminal activates the interrupt generation circuit 15, and the output generates an interrupt to the CPU board 10 via the buffer 55.

On the other hand, the interrupt controller in the CPU board 10 that detected the interrupt is set to mode 1, as described in the prior art section, and the microprocessor receives the temporary interrupt identifier and starts interrupt processing.

When software reads the FIFO memory in the interface board 12 in the interrupt processing routine of the microprocessor, an address and a read command are output from the CI-'U board 10.

Addresses are input from the address bus AB to the address decoder 18 via the buffer 55 and output to the FIFO memory, and read commands are input from the control @ signal bus CB to the FIFO memory via the buffer 55.

The FIF○ memory outputs an interrupt identifier to the internal data bus DBI in response to both signals, and the microprocessor reads this to identify by software which source of the input/output board 11 caused the interrupt. be able to.

If the interface board of this embodiment is used in this way,
Even in a microcontroller system that does not have an interrupt recognition signal on an external bus, it is possible to support interrupt processing from an input/output board that has multiple interrupt generation factors.

In particular, in this embodiment, a FIF is used for storing interrupt identifiers.
O memory is used, so even if interrupts are received continuously from the input/output board, problems such as interrupt identifiers being overwritten will not occur, and interrupts will be processed accurately in the order in which they occur. be able to.

[Effects of the Invention] As is clear from the above description, the interface board of the present invention can handle multiple types of interrupts on the input/output board even in a system that does not have an interrupt recognition signal on the external bus of the CPU board. support, and it is possible to build a flexible system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a microcontroller system including an interface board of the present invention, and FIG. 2 is a block diagram of a microcontroller system including a conventional interface board. 10...CPU board 11...I/O board 12...Interface board 13...FIFO memory 14...Interrupt recognition signal 15...Interrupt generation circuit 16...CPU board bus 17 ...Input/output board bus

Claims (1)

[Scope of Claims] At least a bus to be connected to the CPU board, a bus to be connected to the input/output board, and a bus conversion circuit for matching bus specifications between the two buses. In response to the interrupt request signal sent from the input/output board,
A circuit that returns an interrupt recognition signal to the input/output board based on its own judgment without making an inquiry to the CPU board, and a circuit that sends the interrupt recognition signal back to the data bus from the input/output board after returning the interrupt recognition signal. While temporarily storing the interrupt identifier,
a memory whose storage contents can be read from the PU board; and when an interrupt identifier is stored in the memory, the CP
An interface board comprising: a circuit for sending an interrupt request signal to a U board;