JPH01297862A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01297862A JPH01297862A JP12778988A JP12778988A JPH01297862A JP H01297862 A JPH01297862 A JP H01297862A JP 12778988 A JP12778988 A JP 12778988A JP 12778988 A JP12778988 A JP 12778988A JP H01297862 A JPH01297862 A JP H01297862A
- Authority
- JP
- Japan
- Prior art keywords
- type
- layer
- semiconductor device
- mask pattern
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 150000002500 ions Chemical class 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims 2
- 239000004020 conductor Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 22
- 238000009792 diffusion process Methods 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 11
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 11
- 239000000377 silicon dioxide Substances 0.000 abstract description 11
- 229910052796 boron Inorganic materials 0.000 abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052785 arsenic Inorganic materials 0.000 abstract description 3
- -1 arsenic ions Chemical class 0.000 abstract 2
- 238000005468 ion implantation Methods 0.000 description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 238000000605 extraction Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 150000001638 boron Chemical class 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は不純物のイオン注入工程を含む半導体装置の製
造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device including an impurity ion implantation process.
従来の技術
従来、バイポーラ型半導体装置において、半導体装置の
サイズを縮小するための二酸化シリコン膜を用いた素子
分離方法がある。この製造方法の場合、電極取り出し窓
を先に開口し、その後フォトレジスト膜マスクパターン
を用いたイオン注入法による拡散層の形成が行なわれる
。2. Description of the Related Art Conventionally, in a bipolar semiconductor device, there has been an element isolation method using a silicon dioxide film to reduce the size of the semiconductor device. In this manufacturing method, an electrode extraction window is first opened, and then a diffusion layer is formed by ion implantation using a photoresist film mask pattern.
第２図は二酸化シリコン膜を素子分離に用いたバイポー
ラ型半導体装置の代表的な従来例の断面図である。この
半導体装置を標準的な製造工程手順にしたがって述べる
と、Ｐ型シリコン基板１の上にＮ型埋込層２およびＮ型
エピタキシャル層３を形成し、そして選択的にエピタキ
シャル層を食刻した部分のみに二酸化シリコン膜４を形
成し、半導体装置形成領域を分離する。次にＮ型コレク
タ層５を形成するために、リンを拡散し、その後、薄い
二酸化シリコン膜６および薄いシリコン窒化膜７を形成
し、続いて、電極取り出し窓を開口する。次にＮ型エミ
ツタ層９を形成するために、フォトレジスト膜マスクパ
ターンを用いたイオン注入法により、砒素を拡散し、続
いて、Ｐ型ベース層１０の形成のために、同し方法てボ
ロンを拡散した後、配線電極層１１を形成し、全面に表
面安定化のための保護膜１２を順次形成する。FIG. 2 is a sectional view of a typical conventional bipolar semiconductor device using a silicon dioxide film for element isolation. This semiconductor device will be described according to standard manufacturing process procedures. An N-type buried layer 2 and an N-type epitaxial layer 3 are formed on a P-type silicon substrate 1, and a portion of the epitaxial layer is selectively etched. A silicon dioxide film 4 is formed only on the substrate to isolate the semiconductor device forming region. Next, to form an N-type collector layer 5, phosphorus is diffused, then a thin silicon dioxide film 6 and a thin silicon nitride film 7 are formed, and then an electrode extraction window is opened. Next, to form an N-type emitter layer 9, arsenic is diffused by ion implantation using a photoresist film mask pattern, and then boron is diffused by the same method to form a P-type base layer 10. After diffusing, a wiring electrode layer 11 is formed, and a protective film 12 for surface stabilization is sequentially formed on the entire surface.
発明が解決しようとする課題
このような従来の方法では、フォトレジスト膜マスクパ
ターンを用いたイオン注入法によるＮ型エミツタ層９お
よびＰ型ベース層１０を形成するには、２種類のフォト
マスクが必要なため、エミッタおよびベース領域の形成
における製造コストの上昇がある。Problems to be Solved by the Invention In such a conventional method, two types of photomasks are required to form the N-type emitter layer 9 and the P-type base layer 10 by ion implantation using a photoresist film mask pattern. There is an increase in manufacturing costs in the formation of the emitter and base regions due to the necessity.
本発明はこのような問題を解決するもので、比較的簡単
な製造工程の導入によって工程数の削減を実現し、更に
ベース領域の高耐圧化を低コストで実現することのでき
る半導体装置の製造方法を提供することを目的とするも
のである。The present invention solves these problems by introducing a relatively simple manufacturing process to reduce the number of manufacturing steps, and also to manufacture a semiconductor device that can achieve high breakdown voltage in the base region at low cost. The purpose is to provide a method.
課題を解決するための手段
この問題点を解決するために、本発明はＮ型エミツタ層
形成のイオン注入工程に用いたフォトレジスト膜マスク
パターンを除去ぜす、酸素プラズマを用いて前記フォト
レジスト膜マスクパターンの膜厚の減少とパターンの後
退を起こさせる工程と、Ｐ型ベース領域にイオン注入す
る工程と、Ｎ型エミツタ層とＰ型ベース層の拡散をする
工程とを具備した半導体装置の製造方法である。Means for Solving the Problem In order to solve this problem, the present invention removes the photoresist film mask pattern used in the ion implantation process for forming the N-type emitter layer, and then removes the photoresist film using oxygen plasma. Manufacture of a semiconductor device comprising a step of reducing the film thickness of a mask pattern and causing pattern regression, a step of implanting ions into a P-type base region, and a step of diffusing an N-type emitter layer and a P-type base layer. It's a method.
作用
本発明によると、１種類のフォトマスクで相反する２種
類の導電型の不純物イオンを注入して、エミツタ層とベ
ース層とが同時に形成でき、エミツタ層とベース層とを
形成するための拡散工程が単一化され、更にベース領域
の高耐圧化を実現した半導体装置を低コストで製造でき
る。According to the present invention, an emitter layer and a base layer can be formed simultaneously by implanting impurity ions of two types of opposite conductivity with one type of photomask, and diffusion for forming the emitter layer and base layer can be performed. The process is simplified, and a semiconductor device with a high breakdown voltage of the base region can be manufactured at low cost.
実施例
以下、本発明の一実施例を第１図の工程順断面図（ａ）
〜（ｅ）を参照して詳しく説明する。EXAMPLE Hereinafter, an example of the present invention will be described with reference to step-by-step sectional views (a) in FIG. 1.
This will be explained in detail with reference to (e).
第１図（ａ）に示すように、Ｐ型シリコン基板１の上に
Ｎ型埋込み層２およびＮ型エピタキシャル層３を形成し
、そして、選択的にエピタキシャル層を食刻し、その食
刻した部分のみに二酸化シリコン膜４を形成し、半導体
装置形成領域を分離する。次に、この半導体装置形成領
域の一部にリンを拡散し、Ｎ型コレクタ層５を形成する
。次に、薄い二酸化シリコン膜６および薄いシリコン窒
化膜７を形成し、続いて電極取り出し窓を選択的に食刻
し開口する。As shown in FIG. 1(a), an N-type buried layer 2 and an N-type epitaxial layer 3 are formed on a P-type silicon substrate 1, and the epitaxial layer is selectively etched. A silicon dioxide film 4 is formed only in that portion to isolate a semiconductor device formation region. Next, phosphorus is diffused into a part of this semiconductor device formation region to form an N-type collector layer 5. Next, a thin silicon dioxide film 6 and a thin silicon nitride film 7 are formed, and then electrode extraction windows are selectively etched to open.
次に、第１図（ｂ）に示すように、フォトレジスト膜マ
スクパターン８を形成し、続いて１８０℃の熱処理を行
い、フォトレジスト膜マスクパターンの端部をフローさ
せる。次に、拡散不純物である砒素をイオン注入法によ
り、薄い二酸化シリコン膜６および薄いシリコン窒化膜
７の開口部に注入する。Next, as shown in FIG. 1(b), a photoresist film mask pattern 8 is formed, followed by heat treatment at 180° C. to cause the ends of the photoresist film mask pattern to flow. Next, arsenic as a diffusion impurity is implanted into the openings of the thin silicon dioxide film 6 and the thin silicon nitride film 7 by ion implantation.
次に、第１図（Ｃ）に示すように、酸素プラズマを用い
、フォトレジスト膜マスクパターン８の膜厚を減少させ
、この時に酸素プラズマは等方性エツチングの性質をも
っことからフォトレジスト膜マスクパターンの端部の後
退をも起こさせる。またこの時、ベース電極取り出し窓
開口部までフォトレジスト膜マスクパターンを後退させ
るのだが、フォトレジスト膜は、次のイオン注入工程時
に不鈍物を注入したくない部分で十分な膜厚を残すため
に、あらかじめ、その膜厚を、前記の砒素イオン注入工
程（第１図（ｂ））時に十分考慮しておく。Next, as shown in FIG. 1C, the thickness of the photoresist film mask pattern 8 is reduced using oxygen plasma. This also causes the edges of the mask pattern to recede. Also, at this time, the photoresist film mask pattern is retreated to the base electrode extraction window opening, but the photoresist film is left with a sufficient film thickness in areas where it is not desired to implant inert materials during the next ion implantation process. The thickness of the film should be taken into consideration in advance during the arsenic ion implantation step (FIG. 1(b)).
次に、第１図（ｄ）に示すように、拡散不純物であるボ
ロンを、イオン注入法により、フォトレジスト膜マスク
パターンの後退して広がった開口部に注入する。次に、
フォトレジスト膜を完全に除去し、その後、熱拡散の処
理をほどこし、Ｎ型エミツタ層およびＰ型ベース層を同
時に形成し、拡散工程を完了する。またこのボロンイオ
ン注入工程時に、フォトレジスト膜マスクパターン端部
の傾斜がつき薄くなった部分ては、拡散不純物であるボ
ロンがフォトレジスト膜を突き抜けてエピタキシャル層
３に注入され、フォトレジスト膜の膜厚の差によりボロ
ン濃度が調整され、熱拡散後では図のような傾斜のつい
たＰ型ベース層１ｏが形成される。Next, as shown in FIG. 1(d), boron as a diffusion impurity is implanted into the receding and widening opening of the photoresist film mask pattern by ion implantation. next,
The photoresist film is completely removed, and then a thermal diffusion process is performed to simultaneously form an N-type emitter layer and a P-type base layer to complete the diffusion process. In addition, during this boron ion implantation process, in the sloped and thinned portions of the photoresist film mask pattern edges, boron as a diffusion impurity penetrates through the photoresist film and is implanted into the epitaxial layer 3. The boron concentration is adjusted by the difference in thickness, and after thermal diffusion, a sloped P-type base layer 1o as shown in the figure is formed.
最後に、第１図（ｅ）に示すように、全面にアルミニウ
ムなどの金属膜を蒸着し、周知のフォトリソグラフィー
技術によって、配線電極層１１を形成し、続いて、保護
膜１２を全面に被覆して、バイポーラＮＰＮ型構造の半
導体装置が完成する。Finally, as shown in FIG. 1(e), a metal film such as aluminum is deposited on the entire surface, a wiring electrode layer 11 is formed using a well-known photolithography technique, and then a protective film 12 is coated on the entire surface. As a result, a semiconductor device having a bipolar NPN structure is completed.
発明の詳細
な説明したように、本発明によれば、１種類のフォトマ
スつて相反する２種類の不純物イオンを注入することが
でき、これにより、たとえば、バイポーラ型トランジス
タのエミツタ層とベース層が同時に形成でき、拡散工程
の単一化が可能であり、更にベース領域の高耐圧化を実
現した半導体装置を、比較的容易に低コストて製造でき
る。As described in detail, according to the present invention, two types of impurity ions that conflict with each other can be implanted into one type of photomass, thereby, for example, the emitter layer and base layer of a bipolar transistor can be implanted. A semiconductor device that can be formed at the same time, can simplify the diffusion process, and has a high breakdown voltage of the base region can be manufactured relatively easily and at low cost.
第１図は、本発明の一実施例工程順断面図、第′２図は
従来例バイポーラＮＰＮ型半導体装置の断面図である。
１・・・・・・Ｐ型シリコン基板、２・・・・・・Ｎ型
埋込み層、３・・・・・・Ｎ型エピタキシャル層、４・
・・・・・分離二酸化シリコン膜、５・・・・・・Ｎ型
コレクタ層、６・・・・・・二酸化シリコン膜、７・・
・・・・シリコン窒化膜、８・・・・・フォトレジスト
膜、９・・・・・・Ｎ型不純物導入領域（エミッタ拡散
層）、１０・・・・・・Ｐ型ベース拡散層、１１・・・
・・・配線電極層、１２・・・・・・保護膜。
代理人の氏名 弁理士 中尾敏男 ほか１名ｋ （’
％Ｊ ｒつ 寸
医
らFIG. 1 is a step-by-step sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional bipolar NPN semiconductor device. 1... P-type silicon substrate, 2... N-type buried layer, 3... N-type epitaxial layer, 4...
... Separated silicon dioxide film, 5 ... N-type collector layer, 6 ... Silicon dioxide film, 7 ...
... Silicon nitride film, 8 ... Photoresist film, 9 ... N-type impurity introduced region (emitter diffusion layer), 10 ... P-type base diffusion layer, 11 ...
. . . Wiring electrode layer, 12 . . . Protective film. Name of agent: Patent attorney Toshio Nakao and one other person ('
% J rtsu doctor et al.
Claims (1)
窓を食刻開口とする工程と、前記絶縁膜上および前記電
極取り出し窓上に設けたフォトレジスト膜マスクパター
ンを用いて選択的に一導電型の不純物イオンを注入する
工程と、前記フォトレジスト膜マスクパターンの膜厚を
減少させる工程と、膜厚減少後の前記フォトレジスト膜
マスクパターンを用いて選択的に前記と反対導電型の不
純物イオンを注入する工程と、イオン注入された前記２
種の相反する導電型の不純物を同時に拡散する工程とを
有することを特徴とする半導体装置の製造方法。A step of etching an electrode take-out window into an insulating film that is in close contact with one main surface of the semiconductor substrate, and selectively etching one conductor using a photoresist film mask pattern provided on the insulating film and the electrode take-out window. a step of reducing the film thickness of the photoresist film mask pattern; and a step of selectively implanting impurity ions of the opposite conductivity type using the photoresist film mask pattern after the film thickness has been reduced. a step of implanting the ion-implanted
1. A method of manufacturing a semiconductor device, comprising the step of simultaneously diffusing impurities of opposite conductivity types.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12778988A JPH01297862A (en) | 1988-05-25 | 1988-05-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12778988A JPH01297862A (en) | 1988-05-25 | 1988-05-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01297862A true JPH01297862A (en) | 1989-11-30 |
Family
ID=14968719
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12778988A Pending JPH01297862A (en) | 1988-05-25 | 1988-05-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01297862A (en) |
-
1988
- 1988-05-25 JP JP12778988A patent/JPH01297862A/en active Pending
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